dri-devel October 2011

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[PATCH 1/7] drm/exynos: fixed overlay data updating.
by Inki Dae 14 Oct '11

14 Oct '11

this patch adds common members to overlay structure and makes each driver such as fimd or hdmi driver set them to its own structure. Signed-off-by: Inki Dae <inki.dae(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_buf.h | 3 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 101 ++++++++++++++++++----------- drivers/gpu/drm/exynos/exynos_drm_drv.h | 41 ++++++++---- drivers/gpu/drm/exynos/exynos_drm_fb.c | 20 ++---- drivers/gpu/drm/exynos/exynos_drm_fb.h | 10 --- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 31 ++++++--- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 59 ++++++++++++----- 7 files changed, 162 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.h b/drivers/gpu/drm/exynos/exynos_drm_buf.h index 9b1f0fb..045d59e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_buf.h +++ b/drivers/gpu/drm/exynos/exynos_drm_buf.h @@ -43,6 +43,9 @@ struct exynos_drm_buf_entry { struct exynos_drm_buf_entry *exynos_drm_buf_create(struct drm_device *dev, unsigned int size); +/* get physical memory information of a drm framebuffer. */ +struct exynos_drm_buf_entry *exynos_drm_fb_get_buf(struct drm_framebuffer *fb); + /* remove allocated physical memory. */ void exynos_drm_buf_destroy(struct drm_device *dev, struct exynos_drm_buf_entry *entry); diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 683ceb0..654bf3a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -32,23 +32,28 @@ #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" #include "exynos_drm_encoder.h" +#include "exynos_drm_buf.h" #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc,\ drm_crtc) /* - * @fb_x: horizontal position from framebuffer base - * @fb_y: vertical position from framebuffer base - * @base_x: horizontal position from screen base - * @base_y: vertical position from screen base - * @crtc_w: width of crtc - * @crtc_h: height of crtc + * Exynos specific crtc postion structure. + * + * @fb_x: offset x on a framebuffer to be displyed + * - the unit is screen coordinates. + * @fb_y: offset y on a framebuffer to be displayed + * - the unit is screen coordinates. + * @crtc_x: offset x on hardware screen. + * @crtc_y: offset y on hardware screen. + * @crtc_w: width of hardware screen. + * @crtc_h: height of hardware screen. */ struct exynos_drm_crtc_pos { unsigned int fb_x; unsigned int fb_y; - unsigned int base_x; - unsigned int base_y; + unsigned int crtc_x; + unsigned int crtc_y; unsigned int crtc_w; unsigned int crtc_h; }; @@ -83,42 +88,56 @@ void exynos_drm_crtc_apply(struct drm_crtc *crtc) exynos_drm_fn_encoder(crtc, NULL, exynos_drm_encoder_crtc_commit); } -static void exynos_drm_overlay_update(struct exynos_drm_overlay *overlay, +static int exynos_drm_overlay_update(struct exynos_drm_overlay *overlay, struct drm_framebuffer *fb, struct drm_display_mode *mode, struct exynos_drm_crtc_pos *pos) { - struct exynos_drm_buffer_info buffer_info; - unsigned int actual_w = pos->crtc_w; - unsigned int actual_h = pos->crtc_h; - unsigned int hw_w; - unsigned int hw_h; - - /* update buffer address of framebuffer. */ - exynos_drm_fb_update_buf_off(fb, pos->fb_x, pos->fb_y, &buffer_info); - overlay->paddr = buffer_info.paddr; - overlay->vaddr = buffer_info.vaddr; - - hw_w = mode->hdisplay - pos->base_x; - hw_h = mode->vdisplay - pos->base_y; - - if (actual_w > hw_w) - actual_w = hw_w; - if (actual_h > hw_h) - actual_h = hw_h; - - overlay->offset_x = pos->base_x; - overlay->offset_y = pos->base_y; - overlay->width = actual_w; - overlay->height = actual_h; + struct exynos_drm_buf_entry *entry; + unsigned int actual_w; + unsigned int actual_h; + + entry = exynos_drm_fb_get_buf(fb); + if (!entry) { + DRM_LOG_KMS("entry is null.\n"); + return -EFAULT; + } + + overlay->paddr = entry->paddr; + overlay->vaddr = entry->vaddr; + + DRM_DEBUG_KMS("vaddr = 0x%lx, paddr = 0x%lx\n", + (unsigned long)overlay->vaddr, + (unsigned long)overlay->paddr); + + actual_w = min((mode->hdisplay - pos->crtc_x), pos->crtc_w); + actual_h = min((mode->vdisplay - pos->crtc_y), pos->crtc_h); + + /* set drm framebuffer data. */ + overlay->fb_x = pos->fb_x; + overlay->fb_y = pos->fb_y; + overlay->fb_width = fb->width; + overlay->fb_height = fb->height; overlay->bpp = fb->bits_per_pixel; + overlay->pitch = fb->pitch; + + /* set overlay range to be displayed. */ + overlay->crtc_x = pos->crtc_x; + overlay->crtc_y = pos->crtc_y; + overlay->crtc_width = actual_w; + overlay->crtc_height = actual_h; + + /* set drm mode data. */ + overlay->mode_width = mode->hdisplay; + overlay->mode_height = mode->vdisplay; + overlay->refresh = mode->vrefresh; + overlay->scan_flag = mode->flags; DRM_DEBUG_KMS("overlay : offset_x/y(%d,%d), width/height(%d,%d)", - overlay->offset_x, overlay->offset_y, - overlay->width, overlay->height); + overlay->crtc_x, overlay->crtc_y, + overlay->crtc_width, overlay->crtc_height); - overlay->buf_offsize = fb->width - actual_w; - overlay->line_size = actual_w; + return 0; } static int exynos_drm_crtc_update(struct drm_crtc *crtc) @@ -136,14 +155,18 @@ static int exynos_drm_crtc_update(struct drm_crtc *crtc) overlay = &exynos_crtc->overlay; memset(&pos, 0, sizeof(struct exynos_drm_crtc_pos)); + + /* it means the offset of framebuffer to be displayed. */ pos.fb_x = crtc->x; pos.fb_y = crtc->y; + + /* OSD position to be displayed. */ + pos.crtc_x = 0; + pos.crtc_y = 0; pos.crtc_w = fb->width - crtc->x; pos.crtc_h = fb->height - crtc->y; - exynos_drm_overlay_update(overlay, crtc->fb, mode, &pos); - - return 0; + return exynos_drm_overlay_update(overlay, crtc->fb, mode, &pos); } static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 832b650..4ea1371 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -63,18 +63,26 @@ struct exynos_drm_overlay_ops { /* * Exynos drm common overlay structure. * - * @offset_x: offset to x position. - * @offset_y: offset to y position. - * @width: window width. - * @height: window height. + * @fb_x: offset x on a framebuffer to be displayed. + * - the unit is screen coordinates. + * @fb_y: offset y on a framebuffer to be displayed. + * - the unit is screen coordinates. + * @fb_width: width of a framebuffer. + * @fb_height: height of a framebuffer. + * @crtc_x: offset x on hardware screen. + * @crtc_y: offset y on hardware screen. + * @crtc_width: window width to be displayed (hardware screen). + * @crtc_height: window height to be displayed (hardware screen). + * @mode_width: width of screen mode. + * @mode_height: height of screen mode. + * @refresh: refresh rate. + * @scan_flag: interlace or progressive way. + * (it could be DRM_MODE_FLAG_*) * @bpp: pixel size.(in bit) * @paddr: bus(accessed by dma) physical memory address to this overlay * and this is physically continuous. * @vaddr: virtual memory addresss to this overlay. * @buf_off: start offset of framebuffer to be displayed. - * @buf_offsize: this value has result from - * (framebuffer width - display width) * bpp. - * @line_size: line size to this overlay memory in bytes. * @default_win: a window to be enabled. * @color_key: color key on or off. * @index_color: if using color key feature then this value would be used @@ -87,16 +95,23 @@ struct exynos_drm_overlay_ops { * to hardware specific overlay info. */ struct exynos_drm_overlay { - unsigned int offset_x; - unsigned int offset_y; - unsigned int width; - unsigned int height; + unsigned int fb_x; + unsigned int fb_y; + unsigned int fb_width; + unsigned int fb_height; + unsigned int crtc_x; + unsigned int crtc_y; + unsigned int crtc_width; + unsigned int crtc_height; + unsigned int mode_width; + unsigned int mode_height; + unsigned int refresh; + unsigned int scan_flag; unsigned int bpp; + unsigned int pitch; dma_addr_t paddr; void __iomem *vaddr; unsigned int buf_off; - unsigned int buf_offsize; - unsigned int line_size; bool default_win; bool color_key; diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 4505d90..48d29cf 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -220,28 +220,22 @@ struct drm_framebuffer *exynos_drm_fb_create(struct drm_device *dev, return exynos_drm_fb_init(file_priv, dev, mode_cmd); } -void exynos_drm_fb_update_buf_off(struct drm_framebuffer *fb, - unsigned int x, unsigned int y, - struct exynos_drm_buffer_info *info) +struct exynos_drm_buf_entry *exynos_drm_fb_get_buf(struct drm_framebuffer *fb) { struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); struct exynos_drm_buf_entry *entry; - unsigned long offset; DRM_DEBUG_KMS("%s\n", __FILE__); - offset = x * (fb->bits_per_pixel >> 3); - offset += y * fb->pitch; - entry = exynos_fb->entry; + if (!entry) + return NULL; - info->base_addr = entry->paddr; - info->vaddr = entry->vaddr + offset; - info->paddr = entry->paddr + offset; + DRM_DEBUG_KMS("vaddr = 0x%lx, paddr = 0x%lx\n", + (unsigned long)entry->vaddr, + (unsigned long)entry->paddr); - DRM_DEBUG_KMS("updated vaddr = 0x%lx, paddr = 0x%lx, offset = 0x%x\n", - (unsigned long)info->vaddr, (unsigned long)info->paddr, - (unsigned int)offset); + return entry; } static struct drm_mode_config_funcs exynos_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h index eaa478a..eb35931 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.h +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h @@ -28,16 +28,6 @@ #ifndef _EXYNOS_DRM_FB_H_ #define _EXYNOS_DRM_FB_H -struct exynos_drm_buffer_info { - unsigned long base_addr; - dma_addr_t paddr; - void __iomem *vaddr; -}; - -void exynos_drm_fb_update_buf_off(struct drm_framebuffer *fb, - unsigned int x, unsigned int y, - struct exynos_drm_buffer_info *info); - struct drm_framebuffer *exynos_drm_fb_create(struct drm_device *dev, struct drm_file *filp, struct drm_mode_fb_cmd *mode_cmd); diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index ac43bfc..6134515 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -33,6 +33,7 @@ #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" +#include "exynos_drm_buf.h" #define MAX_CONNECTOR 4 #define PREFERRED_BPP 32 @@ -83,7 +84,7 @@ static struct fb_ops exynos_drm_fb_ops = { .fb_setcmap = drm_fb_helper_setcmap, }; -static void exynos_drm_fbdev_update(struct drm_fb_helper *helper, +static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, struct drm_framebuffer *fb, unsigned int fb_width, unsigned int fb_height) @@ -91,8 +92,9 @@ static void exynos_drm_fbdev_update(struct drm_fb_helper *helper, struct fb_info *fbi = helper->fbdev; struct drm_device *dev = helper->dev; struct exynos_drm_fbdev *exynos_fb = to_exynos_fbdev(helper); - struct exynos_drm_buffer_info buffer_info; + struct exynos_drm_buf_entry *entry; unsigned int size = fb_width * fb_height * (fb->bits_per_pixel >> 3); + unsigned long offset; DRM_DEBUG_KMS("%s\n", __FILE__); @@ -101,15 +103,22 @@ static void exynos_drm_fbdev_update(struct drm_fb_helper *helper, drm_fb_helper_fill_fix(fbi, fb->pitch, fb->depth); drm_fb_helper_fill_var(fbi, helper, fb_width, fb_height); - exynos_drm_fb_update_buf_off(fb, fbi->var.xoffset, fbi->var.yoffset, - &buffer_info); + entry = exynos_drm_fb_get_buf(fb); + if (!entry) { + DRM_LOG_KMS("entry is null.\n"); + return -EFAULT; + } - dev->mode_config.fb_base = buffer_info.base_addr; + offset = fbi->var.xoffset * (fb->bits_per_pixel >> 3); + offset += fbi->var.yoffset * fb->pitch; - fbi->screen_base = buffer_info.vaddr; + dev->mode_config.fb_base = entry->paddr; + fbi->screen_base = entry->vaddr + offset; + fbi->fix.smem_start = entry->paddr + offset; fbi->screen_size = size; - fbi->fix.smem_start = buffer_info.paddr; fbi->fix.smem_len = size; + + return 0; } static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, @@ -162,8 +171,10 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, goto out; } - exynos_drm_fbdev_update(helper, helper->fb, sizes->fb_width, + ret = exynos_drm_fbdev_update(helper, helper->fb, sizes->fb_width, sizes->fb_height); + if (ret < 0) + fb_dealloc_cmap(&fbi->cmap); /* * if failed, all resources allocated above would be released by @@ -224,10 +235,8 @@ static int exynos_drm_fbdev_recreate(struct drm_fb_helper *helper, } helper->fb = exynos_fbdev->fb; - exynos_drm_fbdev_update(helper, helper->fb, sizes->fb_width, + return exynos_drm_fbdev_update(helper, helper->fb, sizes->fb_width, sizes->fb_height); - - return 0; } static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper, diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 620ad2d..623ba33 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -59,8 +59,10 @@ struct fimd_win_data { unsigned int offset_x; unsigned int offset_y; - unsigned int width; - unsigned int height; + unsigned int ovl_width; + unsigned int ovl_height; + unsigned int fb_width; + unsigned int fb_height; unsigned int bpp; dma_addr_t paddr; void __iomem *vaddr; @@ -233,6 +235,7 @@ static void fimd_win_mode_set(struct device *dev, { struct fimd_context *ctx = get_fimd_context(dev); struct fimd_win_data *win_data; + unsigned long offset; DRM_DEBUG_KMS("%s\n", __FILE__); @@ -241,17 +244,35 @@ static void fimd_win_mode_set(struct device *dev, return; } + offset = overlay->fb_x * (overlay->bpp >> 3); + offset += overlay->fb_y * overlay->pitch; + + DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); + win_data = &ctx->win_data[ctx->default_win]; - win_data->offset_x = overlay->offset_x; - win_data->offset_y = overlay->offset_y; - win_data->width = overlay->width; - win_data->height = overlay->height; - win_data->paddr = overlay->paddr; - win_data->vaddr = overlay->vaddr; + win_data->offset_x = overlay->crtc_x; + win_data->offset_y = overlay->crtc_y; + win_data->ovl_width = overlay->crtc_width; + win_data->ovl_height = overlay->crtc_height; + win_data->fb_width = overlay->fb_width; + win_data->fb_height = overlay->fb_height; + win_data->paddr = overlay->paddr + offset; + win_data->vaddr = overlay->vaddr + offset; win_data->bpp = overlay->bpp; - win_data->buf_offsize = overlay->buf_offsize * (overlay->bpp >> 3); - win_data->line_size = overlay->line_size * (overlay->bpp >> 3); + win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * + (overlay->bpp >> 3); + win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); + + DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", + win_data->offset_x, win_data->offset_y); + DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", + win_data->ovl_width, win_data->ovl_height); + DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n", + (unsigned long)win_data->paddr, + (unsigned long)win_data->vaddr); + DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", + overlay->fb_width, overlay->crtc_width); } static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) @@ -365,12 +386,14 @@ static void fimd_win_commit(struct device *dev) writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); /* buffer end address */ - size = win_data->width * win_data->height * (win_data->bpp >> 3); + size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); val = win_data->paddr + size; writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", (unsigned long)win_data->paddr, val, size); + DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", + win_data->ovl_width, win_data->ovl_height); /* buffer size */ val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | @@ -382,14 +405,16 @@ static void fimd_win_commit(struct device *dev) VIDOSDxA_TOPLEFT_Y(win_data->offset_y); writel(val, ctx->regs + VIDOSD_A(win)); - val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x + win_data->width - 1) | - VIDOSDxB_BOTRIGHT_Y(win_data->offset_y + win_data->height - 1); + val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x + + win_data->ovl_width - 1) | + VIDOSDxB_BOTRIGHT_Y(win_data->offset_y + + win_data->ovl_height - 1); writel(val, ctx->regs + VIDOSD_B(win)); - DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %x\n", + DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", win_data->offset_x, win_data->offset_y, - win_data->offset_x + win_data->width - 1, - win_data->offset_y + win_data->height - 1); + win_data->offset_x + win_data->ovl_width - 1, + win_data->offset_y + win_data->ovl_height - 1); /* hardware window 0 doesn't support alpha channel. */ if (win != 0) { @@ -406,7 +431,7 @@ static void fimd_win_commit(struct device *dev) u32 offset = VIDOSD_D(win); if (win == 0) offset = VIDOSD_C_SIZE_W0; - val = win_data->width * win_data->height; + val = win_data->ovl_width * win_data->ovl_height; writel(val, ctx->regs + offset); DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); -- 1.7.4.1

1 0

[PATCH 0/7] drm/exynos: add two devices support.
by Inki Dae 14 Oct '11

14 Oct '11

the patch sets are as the following. - updated common overlay structure to support hdmi. - fixed page flip feature for two devices to be supported. - fixed a bug that fbdev reinitialization is failed. - added comments and code clean. this patch is based on git repository below: git://people.freedesktop.org/~airlied/linux.git branch name: drm-next commit-id: b07759bf41d52aaecd5de92c7d725d6834b23349 Inki Dae (5): drm/exynos: fixed overlay data updating. drm/exynos: added device object as argument of subdrv_probe(). drm/exynos: fixed bug to exynos_drm_fb_dev_reinit(). drm/exynos: added comments and code clean. drm/exynos: fixed build warnings and comments. Seung-Woo Kim (1): drm/exynos: fixed page flip bug. Joonyoung Shim (1): drm/exynos: fixed overlay updating time at page flip. drivers/gpu/drm/exynos/exynos_drm_buf.h | 3 + drivers/gpu/drm/exynos/exynos_drm_core.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 123 +++++++++++++++++++---------- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 1 - drivers/gpu/drm/exynos/exynos_drm_drv.c | 14 +++ drivers/gpu/drm/exynos/exynos_drm_drv.h | 50 +++++++----- drivers/gpu/drm/exynos/exynos_drm_fb.c | 20 ++--- drivers/gpu/drm/exynos/exynos_drm_fb.h | 10 --- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 39 ++++++--- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 89 ++++++++++++--------- 10 files changed, 215 insertions(+), 136 deletions(-) -- 1.7.4.1

1 0

[PATCH] drm/i915/panel: Alwyas record the backlight level again (but cleverly)
by Takashi Iwai 13 Oct '11

13 Oct '11

The commit 47356eb67285014527a5ab87543ba1fae3d1e10a introduced a mechanism to record the backlight level only at disabling time, but it also introduced a regression. Since intel_lvds_enable() may be called without disabling (e.g. intel_lvds_commit() calls it unconditionally), the backlight gets back to the last recorded value. For example, this happens when you dim the backlight, close the lid and open the lid, then the backlight suddenly goes to the brightest. This patch fixes the bug by recording the backlight level always when changed but only when dev_priv->backlight_enabled is set. In this way, the bogus value for disabling backlight can be skipped. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- Feel free to add Cc to stable kernel, as this is a regression fix. I've tested only a few machines here so more tests would be appreciated, because the backlight issue is SOOO sensitive :) drivers/gpu/drm/i915/intel_panel.c | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index a9e0c7b..269d526 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -233,6 +233,9 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level) DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); + if (dev_priv->backlight_enabled) + dev_priv->backlight_level = level; + if (HAS_PCH_SPLIT(dev)) return intel_pch_panel_set_backlight(dev, level); @@ -258,11 +261,7 @@ void intel_panel_disable_backlight(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (dev_priv->backlight_enabled) { - dev_priv->backlight_level = intel_panel_get_backlight(dev); - dev_priv->backlight_enabled = false; - } - + dev_priv->backlight_enabled = false; intel_panel_set_backlight(dev, 0); } @@ -273,8 +272,8 @@ void intel_panel_enable_backlight(struct drm_device *dev) if (dev_priv->backlight_level == 0) dev_priv->backlight_level = intel_panel_get_max_backlight(dev); - intel_panel_set_backlight(dev, dev_priv->backlight_level); dev_priv->backlight_enabled = true; + intel_panel_set_backlight(dev, dev_priv->backlight_level); } static void intel_panel_init_backlight(struct drm_device *dev) -- 1.7.7

2 4

drm/radeon/kms: improve performance of blit-copy
by Ilija Hadzic 13 Oct '11

13 Oct '11

The following set of patches will improve the performance of blit-copy functions for Radeon GPUs based on R600, R700, Evergreen and NI ASICs. The foundation for improvement is the use of tiled mode access (which for copying bo's can be used regardless of whether the content is tiled or not), and segmenting the memory block being copied into rectangles whose edge ratio is between 1:1 and 1:2. This maximizes the number of PCIe transactions that use maximum payload size (typically 128 bytes) and also creates a memory access pattern that is more favorable for both VRAM and host DRAM than what's currently in the kernel. To come up with the new blit-copy code, I did a lot of PCIe traffic analysis with the bus analyzer and also had many discussions with Alex, trying to explain what's going on (thanks to Alex for his time). Below (at the end of this note) are the results of some benchmarks that I did with various GPUs (all in the same host: Intel i7 CPU, X58 chipset, three DRAM channels). To run the tests on your machine load the radeon module with 'benchmark=1 pcie_gen2=1' parameters. Most significant improvement is in the upstream (VRAM to GART) direction because that's where the PCIe transactions were fragmented and also where memory access pattern was such that it created a lot of backpressure from the host. It is also interesting that high-end devices (e.g. Cayman) exhibit the least improvement and were the worst to begin with. This is because high-end devices copy more tiles in parallel which in turn can create bank conflicts on host memory and cause the host to do lots of bank-close/precharge/bank-open cycles. As an added "bonus", I also did some code cleanup and consolidated the repeated code into common function, so r600 and evergreen/NI parts now share the blit-copy code. I also expanded on the benchmark coverage, so the module now takes benckmark parameter value between 1 and 8 and each results in running a different benchmark. For details, see the commit log messages and the code. I have been running with these patches for a few months (and I kept rebasing them to drm-core-next as the public git progressed) and I used them in a system setup that does *many* copying of this kind (and does them frequently); I have not seen instabilities introduced by these patches. I also verified the correctness of the copy using test=1 parameter for each GPU that I had and the test passed. I would welcome some feedback and if you run the benchmarks with the new blit code, I would very much like to hear what kind of improvement you are seeing. BENCHMARK RESULTS: ================== 1) VRAM to GTT ============== Card (ASIC) VRAM Before After --------------------------------------------- 5570 (Redwood) DDR3 1600MHZ 454 3912 6450 (Caicos) DDR5 3200MHz 3718 5090 6570 (Turks) DDR3 1800MHz 484 4144 5450 (Cedar) DDR3 1600MHz 3679 5090 5450 (Cedar) DDR2 800MHz 2695 4639 E4690 (RV730) DDR3 1400MHZ 485 4969 E6760 (Turks) DDR5 3200MHz 474 4177 V5700 (RV730) DDR3 ????MHz 488 4297 2260 (RV620) DDR2 ????MHz 494 3093 6870 (Barts) DDR5 4200MHz 475 1113 6970 (Cayman) DDR5 4200MHz 473 710 2) GTT to VRAM ============== Card (ASIC) VRAM Before After --------------------------------------------- 5570 (Redwood) DDR3 1600MHz 3158 3360 6450 (Caicos) DDR5 3200MHz 2995 3393 6570 (Turks) DDR3 1800MHz 3039 3339 5450 (Cedar) DDR3 1600MHz 3246 3404 5450 (Cedar) DDR2 800MHz 2614 3371 E4690 (RV730) DDR3 1400MHz 3084 3426 E6760 (Turks) DDR5 3200MHz 2443 2570 V5700 (RV730) DDR3 ????MHz 3187 3506 2260 (RV620) DDR2 ????MHz 584 3246 6870 (Barts) DDR5 4200MHz 2472 2601 6970 (Cayman) DDR5 4200MHz 2460 2737

2 12

xf86-video-modesetting cursor patch
by James Simmons 13 Oct '11

13 Oct '11

Hi! I tried the xf86-video-modesetting driver with the new via KMS driver. It worked well but I had to turn off the cursor since I haven't finished the cursor in the kernel driver yet. By default the SWCursor option is set to false but when I placed that option in my xorg.conf file it never set SWCursor to TRUE. Also a buffer was still being allocated even with the software curor. This patch address this issue. P.S I also tried the xorg driver on a i915 device with a LVDS but the screen was distored. It looks like a incorrect pitch size. I didn't see that with my via driver. diff --git a/src/driver.c b/src/driver.c index bde690c..1d62b7a 100644 --- a/src/driver.c +++ b/src/driver.c @@ -471,7 +471,7 @@ PreInit(ScrnInfoPtr pScrn, int flags) memcpy(ms->Options, Options, sizeof(Options)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, ms->Options); - if (xf86ReturnOptValBool(ms->Options, OPTION_SW_CURSOR, FALSE)) { + if (xf86ReturnOptValBool(ms->Options, OPTION_SW_CURSOR, TRUE)) { ms->SWCursor = TRUE; } @@ -551,7 +551,8 @@ CreateScreenResources(ScreenPtr pScreen) drmmode_uevent_init(pScrn, &ms->drmmode); - drmmode_map_cursor_bos(pScrn, &ms->drmmode); + if (!ms->SWCursor) + drmmode_map_cursor_bos(pScrn, &ms->drmmode); pixels = drmmode_map_front_bo(&ms->drmmode); if (!pixels) return FALSE;

1 0

[PATCH] drm/radeon/kms: Simplify I2C post_xfer function
by Jean Delvare 13 Oct '11

13 Oct '11

There is no point in re-doing in post_xfer all the initialization that was already done by pre_xfer. Instead, only do the work which differs from pre_xfer. Signed-off-by: Jean Delvare <jdelvare(a)suse.de> Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/radeon/radeon_i2c.c | 48 ++++++++++++++++------------------- 1 file changed, 22 insertions(+), 26 deletions(-) --- linux-3.0.orig/drivers/gpu/drm/radeon/radeon_i2c.c 2011-10-06 18:39:04.000000000 +0200 +++ linux-3.0/drivers/gpu/drm/radeon/radeon_i2c.c 2011-10-06 18:45:27.000000000 +0200 @@ -81,8 +81,9 @@ bool radeon_ddc_probe(struct radeon_conn /* bit banging i2c */ -static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) +static int pre_xfer(struct i2c_adapter *i2c_adap) { + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); struct radeon_device *rdev = i2c->dev->dev_private; struct radeon_i2c_bus_rec *rec = &i2c->rec; uint32_t temp; @@ -137,19 +138,30 @@ static void radeon_i2c_do_lock(struct ra WREG32(rec->en_data_reg, temp); /* mask the gpio pins for software use */ - temp = RREG32(rec->mask_clk_reg); - if (lock_state) - temp |= rec->mask_clk_mask; - else - temp &= ~rec->mask_clk_mask; + temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; WREG32(rec->mask_clk_reg, temp); temp = RREG32(rec->mask_clk_reg); + temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; + WREG32(rec->mask_data_reg, temp); temp = RREG32(rec->mask_data_reg); - if (lock_state) - temp |= rec->mask_data_mask; - else - temp &= ~rec->mask_data_mask; + + return 0; +} + +static void post_xfer(struct i2c_adapter *i2c_adap) +{ + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct radeon_device *rdev = i2c->dev->dev_private; + struct radeon_i2c_bus_rec *rec = &i2c->rec; + uint32_t temp; + + /* unmask the gpio pins for software use */ + temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; + WREG32(rec->mask_clk_reg, temp); + temp = RREG32(rec->mask_clk_reg); + + temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; WREG32(rec->mask_data_reg, temp); temp = RREG32(rec->mask_data_reg); } @@ -209,22 +221,6 @@ static void set_data(void *i2c_priv, int WREG32(rec->en_data_reg, val); } -static int pre_xfer(struct i2c_adapter *i2c_adap) -{ - struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); - - radeon_i2c_do_lock(i2c, 1); - - return 0; -} - -static void post_xfer(struct i2c_adapter *i2c_adap) -{ - struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); - - radeon_i2c_do_lock(i2c, 0); -} - /* hw i2c */ static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) -- Jean Delvare Suse L3

1 0

[Bug 36777] radeon 0000:01:00.0: IH ring buffer overflow (0xFFFFFFFF, 15, 65550)
by bugzilla-daemon＠freedesktop.org 13 Oct '11

13 Oct '11

https://bugs.freedesktop.org/show_bug.cgi?id=36777 Cedric Sodhi <manday(a)gmx.net> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution| |FIXED -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

1 0

[PATCH 1/3] drm/radeon/kms/DCE4.1: fix dig encoder to transmitter mapping
by alexdeucher＠gmail.com 12 Oct '11

12 Oct '11

From: Alex Deucher <alexander.deucher(a)amd.com> llano has fully routeable dig encoders similar to DCE3.2 while ontario has a hardcoded mapping similar to DCE4.0. Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/radeon/radeon_encoders.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 8a171b2..a90d9ee 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -1756,10 +1756,15 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) if (ASIC_IS_DCE4(rdev)) { dig = radeon_encoder->enc_priv; if (ASIC_IS_DCE41(rdev)) { - if (dig->linkb) - return 1; - else - return 0; + /* ontario follows DCE4 */ + if (rdev->family == CHIP_PALM) { + if (dig->linkb) + return 1; + else + return 0; + } else + /* llano follows DCE3.2 */ + return radeon_crtc->crtc_id; } else { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: -- 1.7.1.1

1 3

Power profiles low and mid are identical on Radeon HD6470M
by Wolfgang Fritz 12 Oct '11

12 Oct '11

Hello, I have an HP Elitebook 8560p with Radeon HD7470M graphics, running Debian sid with kernel 3.0.4. I noticed that the power profiles low and mid are setting identical clocks and voltage, the lowest possible values: default engine clock: 750000 kHz current engine clock: 99990 kHz default memory clock: 900000 kHz current memory clock: 149970 kHz voltage: 900 mV Looking at the code, this seems to be intentional at least for the mobility chips, but the chip provides more modes: [ 9.361401] [drm] R600: Number of power states = 7 [ 9.361402] [drm] Is mobility = YES [ 9.361403] [drm] ps #0 type 0, modes=3 [ 9.361404] [drm] 0: mclk=90000, sclk=75000, volt=1100, vddci=0 [ 9.361406] [drm] 1: mclk=90000, sclk=75000, volt=1100, vddci=0 [ 9.361407] [drm] 2: mclk=90000, sclk=75000, volt=1100, vddci=0 [ 9.361409] [drm] ps #1 type 4, modes=3 [ 9.361410] [drm] 0: mclk=15000, sclk=10000, volt=900, vddci=0 [ 9.361411] [drm] 1: mclk=90000, sclk=40000, volt=1000, vddci=0 [ 9.361413] [drm] 2: mclk=90000, sclk=75000, volt=1100, vddci=0 [ 9.361414] [drm] ps #2 type 0, modes=3 [ 9.361415] [drm] 0: mclk=90000, sclk=70000, volt=1100, vddci=0 [ 9.361417] [drm] 1: mclk=90000, sclk=70000, volt=1100, vddci=0 [ 9.361418] [drm] 2: mclk=90000, sclk=70000, volt=1100, vddci=0 [ 9.361419] [drm] ps #3 type 2, modes=3 [ 9.361420] [drm] 0: mclk=15000, sclk=10000, volt=900, vddci=0 [ 9.361422] [drm] 1: mclk=15000, sclk=10000, volt=900, vddci=0 [ 9.361423] [drm] 2: mclk=30000, sclk=30000, volt=900, vddci=0 [ 9.361424] [drm] ps #4 type 2, modes=3 [ 9.361426] [drm] 0: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361427] [drm] 1: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361428] [drm] 2: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361430] [drm] ps #5 type 2, modes=3 [ 9.361431] [drm] 0: mclk=30000, sclk=30000, volt=900, vddci=0 [ 9.361433] [drm] 1: mclk=30000, sclk=30000, volt=900, vddci=0 [ 9.361434] [drm] 2: mclk=30000, sclk=30000, volt=900, vddci=0 [ 9.361435] [drm] ps #6 type 0, modes=3 [ 9.361436] [drm] 0: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361438] [drm] 1: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361439] [drm] 2: mclk=65000, sclk=40000, volt=900, vddci=0 [ 9.361440] [drm] NOT CHIP_R600 (dmesg output from patched radeon module) Questions: 1. Is this a bug or a feature? (I see that it is not obvious which power state to choose) 2. What do the 3 clock/voltage modes per power state mean? Regards, Wolfgang

2 2

[Bug 36003] [Radeon HD 5650 and 5470] Driver crash during recovery boot and in normal boot (Regression from 2.6.38-3 to -4)
by bugzilla-daemon＠freedesktop.org 12 Oct '11

12 Oct '11

https://bugs.freedesktop.org/show_bug.cgi?id=36003 Jeremy Huddleston <jeremyhu(a)freedesktop.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution| |FIXED --- Comment #20 from Jeremy Huddleston <jeremyhu(a)freedesktop.org> 2011-10-12 10:00:48 PDT --- Thanks. Closing based on the above comment. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

1 0

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dri-devel October 2011