dri-devel March 2011

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[Bug 35471] [r300g]3d apps crashing
by bugzilla-daemon＠freedesktop.org 22 Mar '11

22 Mar '11

https://bugs.freedesktop.org/show_bug.cgi?id=35471 Marek Olšák <maraeo(a)gmail.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Resolution|FIXED |NOTOURBUG --- Comment #4 from Marek Olšák <maraeo(a)gmail.com> 2011-03-22 14:08:25 PDT --- -> NOTOURBUG -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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[Bug 35471] [r300g]3d apps crashing
by bugzilla-daemon＠freedesktop.org 22 Mar '11

22 Mar '11

https://bugs.freedesktop.org/show_bug.cgi?id=35471 Marek Olšák <maraeo(a)gmail.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution| |FIXED --- Comment #3 from Marek Olšák <maraeo(a)gmail.com> 2011-03-22 14:07:58 PDT --- Alright then. I am closing this bug. It seems to be an issue with the PPA. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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[Bug 35471] [r300g]3d apps crashing
by bugzilla-daemon＠freedesktop.org 22 Mar '11

22 Mar '11

https://bugs.freedesktop.org/show_bug.cgi?id=35471 Maciej Jagiełło <himek_imp(a)o2.pl> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |himek_imp(a)o2.pl --- Comment #2 from Maciej Jagiełło <himek_imp(a)o2.pl> 2011-03-22 13:24:31 PDT --- (In reply to comment #1) > I can't reproduce this bug with r300g from git. > > What driver are you using? Please attach your glxinfo. > > Can you by any chance try the r300 gallium3d driver from Mesa git? No crashes with mesa (and drm) from git. Thanks. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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Re: [RFC PATCH] HDMI:Support for EDID parsing in kernel.
by Alex Deucher 22 Mar '11

22 Mar '11

Adding dri-devel. On Tue, Mar 22, 2011 at 1:32 PM, Mythri P K <mythripk(a)ti.com> wrote: > Adding support for common EDID parsing in kernel. > > EDID - Extended display identification data is a data structure provided by > a digital display to describe its capabilities to a video source, This a > standard supported by CEA and VESA. > > There are several custom implementations for parsing EDID in kernel, some > of them are present in fbmon.c, drm_edid.c, sh_mobile_hdmi.c, Ideally > parsing of EDID should be done in a library, which is agnostic of the > framework (V4l2, DRM, FB) which is using the functionality, just based on > the raw EDID pointer with size/segment information. > > With other RFC's such as the one below, which tries to standardize HDMI API's > It would be better to have a common EDID code in one place.It also helps to > provide better interoperability with variety of TV/Monitor may be even by > listing out quirks which might get missed with several custom implementation > of EDID. > http://permalink.gmane.org/gmane.linux.drivers.video-input-infrastructure/3… > > This patch tries to add functions to parse some portion EDID (detailed timing, > monitor limits, AV delay information, deep color mode support, Audio and VSDB) > If we can align on this library approach i can enhance this library to parse > other blocks and probably we could also add quirks from other implementation > as well. > > Signed-off-by: Mythri P K <mythripk(a)ti.com> > --- > arch/arm/include/asm/edid.h | 243 ++++++++++++++++++++++++++++++ > drivers/video/edid.c | 340 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 583 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/include/asm/edid.h > create mode 100644 drivers/video/edid.c > > diff --git a/arch/arm/include/asm/edid.h b/arch/arm/include/asm/edid.h > new file mode 100644 > index 0000000..843346a > --- /dev/null > +++ b/arch/arm/include/asm/edid.h > @@ -0,0 +1,243 @@ > +/* > + * edid.h > + * > + * Copyright (C) 2011 Texas Instruments > + * Author: Mythri P K <mythripk(a)ti.com> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published by > + * the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + * History: > + */ > + > +#ifndef _EDID_H_ > +#define _EDID_H_ > + > +/* HDMI EDID Length */ > +#define HDMI_EDID_MAX_LENGTH 512 > + > +/* HDMI EDID Extension Data Block Tags */ > +#define HDMI_EDID_EX_DATABLOCK_TAG_MASK 0xE0 > +#define HDMI_EDID_EX_DATABLOCK_LEN_MASK 0x1F > + > +#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 > +#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 > +#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 > +#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 > +#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 > + > +/* EDID Detailed Timing Info 0 begin offset */ > +#define HDMI_EDID_DETAILED_TIMING_OFFSET 0x36 > + > +#define HDMI_EDID_PIX_CLK_OFFSET 0 > +#define HDMI_EDID_H_ACTIVE_OFFSET 2 > +#define HDMI_EDID_H_BLANKING_OFFSET 3 > +#define HDMI_EDID_V_ACTIVE_OFFSET 5 > +#define HDMI_EDID_V_BLANKING_OFFSET 6 > +#define HDMI_EDID_H_SYNC_OFFSET 8 > +#define HDMI_EDID_H_SYNC_PW_OFFSET 9 > +#define HDMI_EDID_V_SYNC_OFFSET 10 > +#define HDMI_EDID_V_SYNC_PW_OFFSET 11 > +#define HDMI_EDID_H_IMAGE_SIZE_OFFSET 12 > +#define HDMI_EDID_V_IMAGE_SIZE_OFFSET 13 > +#define HDMI_EDID_H_BORDER_OFFSET 15 > +#define HDMI_EDID_V_BORDER_OFFSET 16 > +#define HDMI_EDID_FLAGS_OFFSET 17 > + > +/* HDMI EDID DTDs */ > +#define HDMI_EDID_MAX_DTDS 4 > + > +/* HDMI EDID DTD Tags */ > +#define HDMI_EDID_DTD_TAG_MONITOR_NAME 0xFC > +#define HDMI_EDID_DTD_TAG_MONITOR_SERIALNUM 0xFF > +#define HDMI_EDID_DTD_TAG_MONITOR_LIMITS 0xFD > +#define HDMI_EDID_DTD_TAG_STANDARD_TIMING_DATA 0xFA > +#define HDMI_EDID_DTD_TAG_COLOR_POINT_DATA 0xFB > +#define HDMI_EDID_DTD_TAG_ASCII_STRING 0xFE > + > +#define HDMI_IMG_FORMAT_MAX_LENGTH 20 > +#define HDMI_AUDIO_FORMAT_MAX_LENGTH 10 > + > +/* HDMI EDID Extenion Data Block Values: Video */ > +#define HDMI_EDID_EX_VIDEO_NATIVE 0x80 > +#define HDMI_EDID_EX_VIDEO_MASK 0x7F > +#define HDMI_EDID_EX_VIDEO_MAX 35 > + > +#define STANDARD_HDMI_TIMINGS_NB 34 > +#define STANDARD_HDMI_TIMINGS_VESA_START 15 > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +enum extension_edid_db { > + DATABLOCK_AUDIO = 1, > + DATABLOCK_VIDEO = 2, > + DATABLOCK_VENDOR = 3, > + DATABLOCK_SPEAKERS = 4, > +}; > + > +struct img_edid { > + bool pref; > + int code; > +}; > + > +struct image_format { > + int length; > + struct img_edid fmt[HDMI_IMG_FORMAT_MAX_LENGTH]; > +}; > + > +struct audio_edid { > + int num_of_ch; > + int format; > +}; > + > +struct audio_format { > + int length; > + struct audio_edid fmt[HDMI_AUDIO_FORMAT_MAX_LENGTH]; > +}; > + > +struct latency { > + /* vid: if indicated, value=1+ms/2 with a max of 251 meaning 500ms */ > + int vid_latency; > + int aud_latency; > + int int_vid_latency; > + int int_aud_latency; > +}; > + > +struct deep_color { > + bool bit_30; > + bool bit_36; > + int max_tmds_freq; > +}; > + > +/* Video Descriptor Block */ > +struct HDMI_EDID_DTD_VIDEO { > + u16 pixel_clock; /* 54-55 */ > + u8 horiz_active; /* 56 */ > + u8 horiz_blanking; /* 57 */ > + u8 horiz_high; /* 58 */ > + u8 vert_active; /* 59 */ > + u8 vert_blanking; /* 60 */ > + u8 vert_high; /* 61 */ > + u8 horiz_sync_offset; /* 62 */ > + u8 horiz_sync_pulse; /* 63 */ > + u8 vert_sync_pulse; /* 64 */ > + u8 sync_pulse_high; /* 65 */ > + u8 horiz_image_size; /* 66 */ > + u8 vert_image_size; /* 67 */ > + u8 image_size_high; /* 68 */ > + u8 horiz_border; /* 69 */ > + u8 vert_border; /* 70 */ > + u8 misc_settings; /* 71 */ > +}; > + > +/* Monitor Limits Descriptor Block */ > +struct HDMI_EDID_DTD_MONITOR { > + u16 pixel_clock; /* 54-55*/ > + u8 _reserved1; /* 56 */ > + u8 block_type; /* 57 */ > + u8 _reserved2; /* 58 */ > + u8 min_vert_freq; /* 59 */ > + u8 max_vert_freq; /* 60 */ > + u8 min_horiz_freq; /* 61 */ > + u8 max_horiz_freq; /* 62 */ > + u8 pixel_clock_mhz; /* 63 */ > + u8 GTF[2]; /* 64 -65 */ > + u8 start_horiz_freq; /* 66 */ > + u8 C; /* 67 */ > + u8 M[2]; /* 68-69 */ > + u8 K; /* 70 */ > + u8 J; /* 71 */ > + > +} __packed; > + > +/* Text Descriptor Block */ > +struct HDMI_EDID_DTD_TEXT { > + u16 pixel_clock; /* 54-55 */ > + u8 _reserved1; /* 56 */ > + u8 block_type; /* 57 */ > + u8 _reserved2; /* 58 */ > + u8 text[13]; /* 59-71 */ > +} __packed; > + > +/* DTD Union */ > +union HDMI_EDID_DTD { > + struct HDMI_EDID_DTD_VIDEO video; > + struct HDMI_EDID_DTD_TEXT monitor_name; > + struct HDMI_EDID_DTD_TEXT monitor_serial_number; > + struct HDMI_EDID_DTD_TEXT ascii; > + struct HDMI_EDID_DTD_MONITOR monitor_limits; > +} __packed; > + > +/* EDID struct */ > +struct HDMI_EDID { > + u8 header[8]; /* 00-07 */ > + u16 manufacturerID; /* 08-09 */ > + u16 product_id; /* 10-11 */ > + u32 serial_number; /* 12-15 */ > + u8 week_manufactured; /* 16 */ > + u8 year_manufactured; /* 17 */ > + u8 edid_version; /* 18 */ > + u8 edid_revision; /* 19 */ > + u8 video_in_definition; /* 20 */ > + u8 max_horiz_image_size; /* 21 */ > + u8 max_vert_image_size; /* 22 */ > + u8 display_gamma; /* 23 */ > + u8 power_features; /* 24 */ > + u8 chroma_info[10]; /* 25-34 */ > + u8 timing_1; /* 35 */ > + u8 timing_2; /* 36 */ > + u8 timing_3; /* 37 */ > + u8 std_timings[16]; /* 38-53 */ > + union HDMI_EDID_DTD DTD[4]; /* 54-125 */ > + u8 extension_edid; /* 126 */ > + u8 checksum; /* 127 */ > + u8 extension_tag; /* 00 (extensions follow EDID) */ > + u8 extention_rev; /* 01 */ > + u8 offset_dtd; /* 02 */ > + u8 num_dtd; /* 03 */ > + u8 data_block[123]; /* 04 - 126 */ > + u8 extension_checksum; /* 127 */ > + > + u8 ext_datablock[256]; > +} __packed; > + > +struct hdmi_timings { > + > + u16 x_res; > + u16 y_res; > + u32 pixel_clock; /* pixel clock in KHz */ > + u16 hsw; /* Horizontal synchronization pulse width */ > + u16 hfp; /* Horizontal front porch */ > + u16 hbp; /* Horizontal back porch */ > + u16 vsw; /* Vertical synchronization pulse width */ > + u16 vfp; /* Vertical front porch */ > + u16 vbp; /* Vertical back porch */ > +}; > + > +int get_edid_timing_info(union HDMI_EDID_DTD *edid_dtd, > + struct hdmi_timings *timings); > +void get_eedid_timing_info(int current_descriptor_addrs, u8 *edid , > + struct hdmi_timings *timings); > +int hdmi_get_datablock_offset(u8 *edid, enum extension_edid_db datablock, > + int *offset); > +int hdmi_get_image_format(u8 *edid, struct image_format *format); > +int hdmi_get_audio_format(u8 *edid, struct audio_format *format); > +void hdmi_get_av_delay(u8 *edid, struct latency *lat); > +void hdmi_deep_color_support_info(u8 *edid, struct deep_color *format); > +bool hdmi_tv_yuv_supported(u8 *edid); > + > +#ifdef __cplusplus > +}; > +#endif > + > +#endif > diff --git a/drivers/video/edid.c b/drivers/video/edid.c > new file mode 100644 > index 0000000..4eb2074 > --- /dev/null > +++ b/drivers/video/edid.c > @@ -0,0 +1,340 @@ > +/* > + * edid.c > + * > + * Copyright (C) 2011 Texas Instruments > + * Author: Mythri P K <mythripk(a)ti.com> > + * With EDID parsing for DVI Monitor from Rob Clark <rob(a)ti.com> > + * > + * EDID.c to parse the EDID content. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published by > + * the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + * History: > + * > + */ > + > +#include <linux/kernel.h> > +#include <linux/err.h> > +#include <linux/string.h> > +#include <linux/slab.h> > +#include <asm/edid.h> > + > +/* Standard HDMI/VESA timings */ > +const struct hdmi_timings standard_hdmi_timings[STANDARD_HDMI_TIMINGS_NB] = { > + {640, 480, 25200, 96, 16, 48, 2, 10, 33}, > + {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, > + {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, > + {720, 480, 27027, 62, 16, 60, 6, 9, 30}, > + {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, > + {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, > + {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, > + {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, > + {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, > + {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, > + {720, 576, 27000, 64, 12, 68, 5, 5, 39}, > + {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, > + {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, > + {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, > + {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, > + /* Vesa frome here */ > + {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, > + {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, > + {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, > + {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, > + {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, > + {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, > + {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, > + {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, > + {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, > + {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, > + {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, > + {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, > + {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, > + {1920, 1080, 148500, 44, 88, 80, 5, 4, 36}, > + {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, > + {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, > + {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, > + {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, > + {1280, 720, 74250, 40, 110, 220, 5, 5, 20} > +}; > + > +int get_edid_timing_info(union HDMI_EDID_DTD *edid_dtd, > + struct hdmi_timings *timings) > +{ > + if (edid_dtd->video.pixel_clock) { > + struct HDMI_EDID_DTD_VIDEO *vid = &edid_dtd->video; > + > + timings->pixel_clock = 10 * vid->pixel_clock; > + timings->x_res = vid->horiz_active | > + (((u16)vid->horiz_high & 0xf0) << 4); > + timings->y_res = vid->vert_active | > + (((u16)vid->vert_high & 0xf0) << 4); > + timings->hfp = vid->horiz_sync_offset | > + (((u16)vid->sync_pulse_high & 0xc0) << 2); > + timings->hsw = vid->horiz_sync_pulse | > + (((u16)vid->sync_pulse_high & 0x30) << 4); > + timings->hbp = (vid->horiz_blanking | > + (((u16)vid->horiz_high & 0x0f) << 8)) - > + (timings->hfp + timings->hsw); > + timings->vfp = ((vid->vert_sync_pulse & 0xf0) >> 4) | > + ((vid->sync_pulse_high & 0x0f) << 2); > + timings->vsw = (vid->vert_sync_pulse & 0x0f) | > + ((vid->sync_pulse_high & 0x03) << 4); > + timings->vbp = (vid->vert_blanking | > + (((u16)vid->vert_high & 0x0f) << 8)) - > + (timings->vfp + timings->vsw); > + return 0; > + } > + > + switch (edid_dtd->monitor_name.block_type) { > + case HDMI_EDID_DTD_TAG_STANDARD_TIMING_DATA: > + printk(KERN_INFO "standard timing data\n"); > + return -EINVAL; > + case HDMI_EDID_DTD_TAG_COLOR_POINT_DATA: > + printk(KERN_INFO "color point data\n"); > + return -EINVAL; > + case HDMI_EDID_DTD_TAG_MONITOR_NAME: > + printk(KERN_INFO "monitor name: %s\n", > + edid_dtd->monitor_name.text); > + return -EINVAL; > + case HDMI_EDID_DTD_TAG_MONITOR_LIMITS: > + { > + int i, max_area = 0, best_idx = -1; > + struct HDMI_EDID_DTD_MONITOR *limits = > + &edid_dtd->monitor_limits; > + > + printk(KERN_DEBUG " monitor limits\n"); > + printk(KERN_DEBUG " min_vert_freq=%d\n", > + limits->min_vert_freq); > + printk(KERN_DEBUG " max_vert_freq=%d\n", > + limits->max_vert_freq); > + printk(KERN_DEBUG " min_horiz_freq=%d\n", > + limits->min_horiz_freq); > + printk(KERN_DEBUG " max_horiz_freq=%d\n", > + limits->max_horiz_freq); > + printk(KERN_DEBUG " pixel_clock_mhz=%d\n", > + limits->pixel_clock_mhz * 10); > + > + /* find the highest matching resolution (w*h) */ > + > + /* > + * XXX since this is mainly for DVI monitors, should we only > + * support VESA timings? My monitor at home would pick > + * 1920x1080 otherwise, but that seems to not work well (monitor > + * blanks out and comes back, and picture doesn't fill full > + * screen, but leaves a black bar on left (native res is > + * 2048x1152). However if I only consider VESA timings, it picks > + * 1680x1050 and the picture is stable and fills whole screen > + */ > + for (i = STANDARD_HDMI_TIMINGS_VESA_START; > + i < STANDARD_HDMI_TIMINGS_NB; i++) { > + const struct hdmi_timings *timings = > + &standard_hdmi_timings[i]; > + int hz, hscan, pixclock; > + int vtotal, htotal; > + htotal = timings->hbp + timings->hfp + > + timings->hsw + timings->x_res; > + vtotal = timings->vbp + timings->vfp + > + timings->vsw + timings->y_res; > + > + /* NOTE: We don't support interlaced mode for VESA */ > + pixclock = timings->pixel_clock * 1000; > + hscan = (pixclock + htotal / 2) / htotal; > + hscan = (hscan + 500) / 1000 * 1000; > + hz = (hscan + vtotal / 2) / vtotal; > + hscan /= 1000; > + pixclock /= 1000000; > + if ((pixclock < (limits->pixel_clock_mhz * 10)) && > + (limits->min_horiz_freq <= hscan) && > + (hscan <= limits->max_horiz_freq) && > + (limits->min_vert_freq <= hz) && > + (hz <= limits->max_vert_freq)) { > + int area = timings->x_res * timings->y_res; > + printk(KERN_INFO " -> %d: %dx%d\n", i, > + timings->x_res, timings->y_res); > + if (area > max_area) { > + max_area = area; > + best_idx = i; > + } > + } > + } > + if (best_idx > 0) { > + *timings = standard_hdmi_timings[best_idx]; > + printk(KERN_DEBUG "found best resolution: %dx%d (%d)\n", > + timings->x_res, timings->y_res, best_idx); > + } > + return 0; > + } > + case HDMI_EDID_DTD_TAG_ASCII_STRING: > + printk(KERN_INFO "ascii string: %s\n", edid_dtd->ascii.text); > + return -EINVAL; > + case HDMI_EDID_DTD_TAG_MONITOR_SERIALNUM: > + printk(KERN_INFO "monitor serialnum: %s\n", > + edid_dtd->monitor_serial_number.text); > + return -EINVAL; > + default: > + printk(KERN_INFO "unsupported EDID descriptor block format\n"); > + return -EINVAL; > + } > +} > + > +void get_eedid_timing_info(int current_descriptor_addrs, u8 *edid , > + struct hdmi_timings *timings) > +{ > + timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) > + | edid[current_descriptor_addrs + 2]); > + timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) > + | edid[current_descriptor_addrs + 5]); > + timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) > + | edid[current_descriptor_addrs]); > + timings->pixel_clock = 10 * timings->pixel_clock; > + timings->hfp = edid[current_descriptor_addrs + 8]; > + timings->hsw = edid[current_descriptor_addrs + 9]; > + timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) > + | edid[current_descriptor_addrs + 3]) - > + (timings->hfp + timings->hsw); > + timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4); > + timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F); > + timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) > + | edid[current_descriptor_addrs + 6]) - > + (timings->vfp + timings->vsw); > +} > + > +int hdmi_get_datablock_offset(u8 *edid, enum extension_edid_db datablock, > + int *offset) > +{ > + int current_byte, disp, i = 0, length = 0; > + > + if (edid[0x7e] == 0x00) > + return -EINVAL; > + > + disp = edid[(0x80) + 2]; > + if (disp == 0x4) > + return -EINVAL; > + > + i = 0x80 + 0x4; > + printk(KERN_INFO "%x\n", i); > + while (i < (0x80 + disp)) { > + current_byte = edid[i]; > + if ((current_byte >> 5) == datablock) { > + *offset = i; > + printk(KERN_INFO "datablock %d %d\n", > + datablock, *offset); > + return 0; > + } else { > + length = (current_byte & > + HDMI_EDID_EX_DATABLOCK_LEN_MASK) + 1; > + i += length; > + } > + } > + return -EINVAL; > +} > + > +int hdmi_get_image_format(u8 *edid, struct image_format *format) > +{ > + int offset, current_byte, j = 0, length = 0; > + enum extension_edid_db vsdb = DATABLOCK_VIDEO; > + format->length = 0; > + > + memset(format->fmt, 0, sizeof(format->fmt)); > + if (!hdmi_get_datablock_offset(edid, vsdb, &offset)) { > + current_byte = edid[offset]; > + length = current_byte & HDMI_EDID_EX_DATABLOCK_LEN_MASK; > + > + if (length >= HDMI_IMG_FORMAT_MAX_LENGTH) > + format->length = HDMI_IMG_FORMAT_MAX_LENGTH; > + else > + format->length = length; > + > + for (j = 1 ; j < length ; j++) { > + current_byte = edid[offset+j]; > + format->fmt[j-1].code = current_byte & 0x7F; > + format->fmt[j-1].pref = current_byte & 0x80; > + } > + } > + return 0; > +} > + > +int hdmi_get_audio_format(u8 *edid, struct audio_format *format) > +{ > + int offset, current_byte, j = 0, length = 0; > + enum extension_edid_db vsdb = DATABLOCK_AUDIO; > + > + format->length = 0; > + memset(format->fmt, 0, sizeof(format->fmt)); > + > + if (!hdmi_get_datablock_offset(edid, vsdb, &offset)) { > + current_byte = edid[offset]; > + length = current_byte & HDMI_EDID_EX_DATABLOCK_LEN_MASK; > + > + if (length >= HDMI_AUDIO_FORMAT_MAX_LENGTH) > + format->length = HDMI_AUDIO_FORMAT_MAX_LENGTH; > + else > + format->length = length; > + > + for (j = 1 ; j < length ; j++) { > + if (j%3 == 1) { > + current_byte = edid[offset + j]; > + format->fmt[j-1].format = current_byte & 0x78; > + format->fmt[j-1].num_of_ch = > + (current_byte & 0x07) + 1; > + } > + } > + } > + return 0; > +} > + > +void hdmi_get_av_delay(u8 *edid, struct latency *lat) > +{ > + int offset, current_byte, length = 0; > + enum extension_edid_db vsdb = DATABLOCK_VENDOR; > + > + if (!hdmi_get_datablock_offset(edid, vsdb, &offset)) { > + current_byte = edid[offset]; > + length = current_byte & HDMI_EDID_EX_DATABLOCK_LEN_MASK; > + if (length >= 8 && ((current_byte + 8) & 0x80)) { > + lat->vid_latency = (edid[offset + 8] - 1) * 2; > + lat->aud_latency = (edid[offset + 9] - 1) * 2; > + } > + if (length >= 8 && ((current_byte + 8) & 0xC0)) { > + lat->int_vid_latency = (edid[offset + 10] - 1) * 2; > + lat->int_aud_latency = (edid[offset + 11] - 1) * 2; > + } > + } > +} > + > +void hdmi_deep_color_support_info(u8 *edid, struct deep_color *format) > +{ > + int offset, current_byte, length = 0; > + enum extension_edid_db vsdb = DATABLOCK_VENDOR; > + memset(format, 0, sizeof(*format)); > + > + if (!hdmi_get_datablock_offset(edid, vsdb, &offset)) { > + current_byte = edid[offset]; > + length = current_byte & HDMI_EDID_EX_DATABLOCK_LEN_MASK; > + if (length >= 6) { > + format->bit_30 = (edid[offset + 6] & 0x10); > + format->bit_36 = (edid[offset + 6] & 0x20); > + } > + if (length >= 7) > + format->max_tmds_freq = (edid[offset + 7]) * 5; > + } > +} > + > +bool hdmi_tv_yuv_supported(u8 *edid) > +{ > + if (edid[0x7e] != 0x00 && edid[0x83] & 0x30) { > + printk(KERN_INFO "YUV supported"); > + return true; > + } > + return false; > +} > -- > 1.5.6.3 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-media" in > the body of a message to majordomo(a)vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >

1 0

[PATCH] xf86-video-ati: vblank wait on crtc > 1
by Ilija Hadzic 22 Mar '11

22 Mar '11

Hi Alex, Below is a patch against the master branch of xf86-video-ati that adds support for waits on vblank events on CRTCs that are greater than 1 (and thus cannot be represented using current primary/secondary flags interface). The patch makes use of GET_CAP ioctl to check whether vblanks on crtc > 1 are supported by the kernel. If they are not falls back to legacy behavior. Otherwise, it uses correct crtc numbers when waiting on vblank and thus corrects the problem seen in certain multiscreen configurations. The issue was discussed on the dri-devel list in these two threads http://lists.freedesktop.org/archives/dri-devel/2011-March/009009.html http://lists.freedesktop.org/archives/dri-devel/2011-March/009025.html regards, Ilija Reviewed-by: Mario Kleiner <mario.kleiner at tuebingen.mpg.de> Acked-by: Mario Kleiner <mario.kleiner at tuebingen.mpg.de> diff --git a/src/radeon.h b/src/radeon.h index a6d20d7..1a746c7 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -931,6 +931,9 @@ typedef struct { RADEONFBLayout CurrentLayout; +#ifdef RADEON_DRI2 + Bool high_crtc_works; +#endif #ifdef XF86DRI Bool directRenderingEnabled; Bool directRenderingInited; diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c index 66df03c..ed27dad 100644 --- a/src/radeon_dri2.c +++ b/src/radeon_dri2.c @@ -783,6 +783,7 @@ static int radeon_dri2_get_msc(DrawablePtr draw, CARD64 *ust, CARD64 *msc) drmVBlank vbl; int ret; int crtc = radeon_dri2_drawable_crtc(draw); + int high_crtc = 0; /* Drawable not displayed, make up a value */ if (crtc == -1) { @@ -791,8 +792,16 @@ static int radeon_dri2_get_msc(DrawablePtr draw, CARD64 *ust, CARD64 *msc) return TRUE; } vbl.request.type = DRM_VBLANK_RELATIVE; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); @@ -825,6 +834,7 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, drmVBlank vbl; int ret, crtc = radeon_dri2_drawable_crtc(draw); CARD64 current_msc; + int high_crtc = 0; /* Truncate to match kernel interfaces; means occasional overflow * misses, but that's generally not a big deal */ @@ -855,8 +865,16 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, /* Get current count */ vbl.request.type = DRM_VBLANK_RELATIVE; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { @@ -882,8 +900,16 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, if (current_msc >= target_msc) target_msc = current_msc; vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = target_msc; vbl.request.signal = (unsigned long)wait_info; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); @@ -903,8 +929,16 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, * so we queue an event that will satisfy the divisor/remainder equation. */ vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = current_msc - (current_msc % divisor) + remainder; @@ -1029,6 +1063,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, CARD64 current_msc; BoxRec box; RegionRec region; + int high_crtc = 0; /* Truncate to match kernel interfaces; means occasional overflow * misses, but that's generally not a big deal */ @@ -1068,8 +1103,16 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, /* Get current count */ vbl.request.type = DRM_VBLANK_RELATIVE; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = 0; ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); if (ret) { @@ -1111,8 +1154,16 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, */ if (flip == 0) vbl.request.type |= DRM_VBLANK_NEXTONMISS; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; /* If target_msc already reached or passed, set it to * current_msc to ensure we return a reasonable value back @@ -1145,8 +1196,16 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT; if (flip == 0) vbl.request.type |= DRM_VBLANK_NEXTONMISS; - if (crtc > 0) + if (crtc == 1) vbl.request.type |= DRM_VBLANK_SECONDARY; + else if (crtc > 1) { + if (info->high_crtc_works) { + high_crtc = (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) & + DRM_VBLANK_HIGH_CRTC_MASK; + } else + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + vbl.request.type |= high_crtc; vbl.request.sequence = current_msc - (current_msc % divisor) + remainder; @@ -1217,6 +1276,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen) DRI2InfoRec dri2_info = { 0 }; #ifdef USE_DRI2_SCHEDULING const char *driverNames[1]; + uint64_t cap_value; #endif if (!info->useEXA) { @@ -1248,6 +1308,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen) #endif dri2_info.CopyRegion = radeon_dri2_copy_region; + info->high_crtc_works = FALSE; #ifdef USE_DRI2_SCHEDULING if (info->dri->pKernelDRMVersion->version_minor >= 4) { dri2_info.version = 4; @@ -1261,6 +1322,20 @@ radeon_dri2_screen_init(ScreenPtr pScreen) xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for sync extension\n"); } + if (info->drmmode.mode_res->count_crtcs > 2) { + if (drmGetCap(info->dri2.drm_fd, DRM_CAP_HIGH_CRTC, &cap_value)) { + info->high_crtc_works = FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for VBLANKs on CRTC>1\n"); + } else { + if (cap_value) { + info->high_crtc_works = TRUE; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Your kernel does not handle VBLANKs on CRTC>1\n"); + info->high_crtc_works = FALSE; + } + } + } + if (pRADEONEnt->dri2_info_cnt == 0) { #if HAS_DIXREGISTERPRIVATEKEY if (!dixRegisterPrivateKey(DRI2ClientEventsPrivateKey, PRIVATE_CLIENT, sizeof(DRI2ClientEventsRec))) {

4 10

[PATCH 1/2] i915: Remove 'pipe A force' quirk for 855GM and 845G
by Ben Hutchings 22 Mar '11

22 Mar '11

Applying this quirk to the 855GM in all systems causes regressions (Debian bugs #493096, #619019). Instead, apply the quirk to specific models as listed in the old X driver. I don't see any explanation for this quirk being applied to the 845G, except perhaps that VT switching used to hang if pipe A was turned off. However, that seems to be a problem only when using UMS. So remove the quirk for the 845G as well. Signed-off-by: Ben Hutchings <ben(a)decadent.org.uk> --- Needs people to test it, as I can't. Ben. drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++++++++---- 1 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3106c0d..a490f75 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7345,19 +7345,34 @@ struct intel_quirk intel_quirks[] = { /* Thinkpad R31 needs pipe A force quirk */ { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, + /* Dell Latitude D400 needs pipe A force quirk (LP: #228519) */ + { 0x3582, 0x1028, 0x0139, quirk_pipea_force }, + /* Dell Latitude D500 needs pipe A force quirk */ + { 0x3582, 0x1028, 0x0152, quirk_pipea_force }, + /* Dell Latitude D505 needs pipe A force quirk (LP: #235643) */ + { 0x3582, 0x1028, 0x0163, quirk_pipea_force }, + /* Dell Latitude X300 needs pipe A force quirk */ + { 0x3582, 0x1028, 0x014f, quirk_pipea_force }, + /* Dell Inspiron 510m needs pipe A force quirk */ + { 0x3582, 0x1028, 0x0164, quirk_pipea_force }, + /* Toshiba Satellite A30 needs pipe A force quirk */ + { 0x3582, 0x1179, 0xff00, quirk_pipea_force }, /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, + /* Intel 855GM hardware (See LP: #216490) */ + { 0x3582, 0x1028, 0x00c8, quirk_pipea_force }, + /* Intel 855GM hardware (See Novell Bugzilla #406123) */ + { 0x3582, 0x10cf, 0x1215, quirk_pipea_force }, + /* HP Pavilion ze4944ea needs pipe A force quirk (See LP: #242389) */ + { 0x3582, 0x103c, 0x3084, quirk_pipea_force }, /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, /* ThinkPad X40 needs pipe A force quirk */ + { 0x3582, 0x1014, 0x0557, quirk_pipea_force }, /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, - - /* 855 & before need to leave pipe A & dpll A up */ - { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, - { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, }; static void intel_init_quirks(struct drm_device *dev) -- 1.7.4.1

3 7

[RFC PATCH v2] Utilize the PCI API in the TTM framework.
by Konrad Rzeszutek Wilk 22 Mar '11

22 Mar '11

Attached is a set of patches that make it possible for drivers using TTM API (nouveau and radeon graphic drivers) to work under Xen. The explanation is a bit complex and I am not sure if I am explaining it that well..so if something is unclear please do ping me. Changes since v1: [https://lkml.org/lkml/2010/12/6/516] - Cleaned up commit message (forgot to add my SoB). Short explanation of problem: What we are hitting under Xen is that instead of programming the GART with the physical DMA address of the TTM page, we end up programming the bounce buffer DMA (bus) address! Long explanation: The reason we end up doing this is that: 1). alloc_page with GFP_DMA32 does not allocate "real" (Machine Frame Numbers - MFN) under the 4GB in Xen. That is b/c if actually made the pages underneath 4GB available to the the Linux page allocator we would not be able to give those to other guest devices. This would mean if we tried to pass in a USB device to one guest and in another were running the Xorg server we wouldn't be able to do so as we would run out of pages under 4GB. So pages that we get from alloc_page have a PFN that is under 4GB but in reality the real physical address (MFN) is above 4GB. Ugh.. 2). The backends for "struct ttm_backend_func" utilize the PCI API. When they get a page allocated via alloc_page, the use 'pci_map_page' and program the DMA (bus) address in the GART - which is correct. But then the calls that kick off the graphic driver to process the pages do not use the pci_page_sync_* calls. If the physical address of the page is the same as the DMA bus address returned from pci_map_page then there are no trouble. But if they are different: virt_to_phys(page_address(p)) != pci_map_page(p,..) then the graphic card fetches data from the DMA (bus) address (so the value returned from pci_map_page). The data however that the user wrote to (the page p) ends up being untouched. You are probably saying: "What? Nonsense, we stitch the page in ttm_bo_vm_fault using the PFN and .. and even if the virt_to_phys(page_address(p)) != pci_map_page(p) the GART ends up with the bus (DMA) address of the PFN!" That is true. But if you combine this with 1) where you end up with page that is above the dma_mask (even if you called it with GFP_DMA32) and then make a call on pci_map_page you would end up with a bounce buffer! The problem above can be easily reproduced on bare-metal if you pass in "swiotlb=force iommu=soft". There are two ways of fixing this: 1). Use the 'dma_alloc_coherent' (or pci_alloc_consistent if there is struct pcidev present), instead of alloc_page for GFP_DMA32. The 'dma_alloc_coherent' guarantees that the allocated page fits within the device dma_mask (or uses the default DMA32 if no device is passed in). This also guarantees that any subsequent call to the PCI API for this page will return the same DMA (bus) address as the first call (so pci_alloc_consistent, and then pci_map_page will give the same DMA bus address). 2). Use the pci_sync_range_* after sending a page to the graphics engine. If the bounce buffer is used then we end up copying the pages. 3). This one I really don't want to think about, but I should mention it. Alter the alloc_page and its backend to know about Xen. The pushback from the MM guys will be probably: "why not use the PCI API.." So attached is a draft set of patches that use solution #1. I've tested this on baremetal (and Xen) on PCIe Radeon and nouveau cards with success. 1) The 'NULL' when doing dma_alloc_coherent is unsightly. I was toying with modifying the TTM API to pass in 'struct device' or 'struct pci_device' but figured it would make first sense to get your guys input before heading that route. This patch-set is also available at: git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen.git devel/ttm.pci-api.v3 Konrad Rzeszutek Wilk (5): ttm: Introduce a placeholder for DMA (bus) addresses. tm: Utilize the dma_addr_t array for pages that are to in DMA32 pool. ttm: Expand (*populate) to support an array of DMA addresses. radeon/ttm/PCIe: Use dma_addr if TTM has set it. nouveau/ttm/PCIe: Use dma_addr if TTM has set it. And diffstat: drivers/gpu/drm/nouveau/nouveau_sgdma.c | 31 +++++++++++++++++++------- drivers/gpu/drm/radeon/radeon.h | 4 ++- drivers/gpu/drm/radeon/radeon_gart.c | 36 ++++++++++++++++++++++-------- drivers/gpu/drm/radeon/radeon_ttm.c | 8 +++++- drivers/gpu/drm/ttm/ttm_agp_backend.c | 3 +- drivers/gpu/drm/ttm/ttm_page_alloc.c | 35 +++++++++++++++++++++++++----- drivers/gpu/drm/ttm/ttm_tt.c | 12 +++++++-- drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c | 3 +- include/drm/ttm/ttm_bo_driver.h | 6 ++++- include/drm/ttm/ttm_page_alloc.h | 8 +++++- 10 files changed, 111 insertions(+), 35 deletions(-)

6 38

[PATCH] kernel/drm: vblank wait on crtc > 1
by Ilija Hadzic 22 Mar '11

22 Mar '11

Hi Dave, Below is a patch against drm-next branch of 2.6.38-rc8+ kernel that adds the capability to wait on vblank events for CRTCs that are greater than 1 and thus cannot be represented with primary/secondary flags in the legacy interface. It was discussed on the dri-devel list in these two threads: http://lists.freedesktop.org/archives/dri-devel/2011-March/009009.html http://lists.freedesktop.org/archives/dri-devel/2011-March/009025.html This patch extends the interface to drm_wait_vblank ioctl so that crtc>1 can be represented. It also adds a new capability to drm_getcap ioctl so that the user space can check whether the new interface to drm_wait_vblank is supported (and fall back to the legacy interface if not) Regards, Ilija Reviewed-by: Mario Kleiner <mario.kleiner at tuebingen.mpg.de> Acked-by: Mario Kleiner <mario.kleiner at tuebingen.mpg.de> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 7f6912a..3617b4c 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -280,6 +280,9 @@ int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv) if (dev->driver->dumb_create) req->value = 1; break; + case DRM_CAP_HIGH_CRTC: + req->value = 1; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index a34ef97..c725088 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -1125,7 +1125,7 @@ int drm_wait_vblank(struct drm_device *dev, void *data, { union drm_wait_vblank *vblwait = data; int ret = 0; - unsigned int flags, seq, crtc; + unsigned int flags, seq, crtc, high_crtc; if ((!drm_dev_to_irq(dev)) || (!dev->irq_enabled)) return -EINVAL; @@ -1134,16 +1134,21 @@ int drm_wait_vblank(struct drm_device *dev, void *data, return -EINVAL; if (vblwait->request.type & - ~(_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK)) { + ~(_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK | + _DRM_VBLANK_HIGH_CRTC_MASK)) { DRM_ERROR("Unsupported type value 0x%x, supported mask 0x%x\n", vblwait->request.type, - (_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK)); + (_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK | + _DRM_VBLANK_HIGH_CRTC_MASK)); return -EINVAL; } flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK; - crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0; - + high_crtc = (vblwait->request.type & _DRM_VBLANK_HIGH_CRTC_MASK); + if (high_crtc) + crtc = high_crtc >> _DRM_VBLANK_HIGH_CRTC_SHIFT; + else + crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0; if (crtc >= dev->num_crtcs) return -EINVAL; diff --git a/include/drm/drm.h b/include/drm/drm.h index 9ac4313..99cd074 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -469,6 +469,8 @@ enum drm_vblank_seq_type { _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ }; +#define _DRM_VBLANK_HIGH_CRTC_SHIFT 16 +#define _DRM_VBLANK_HIGH_CRTC_MASK 0x001F0000 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ @@ -753,6 +755,7 @@ struct drm_event_vblank { }; #define DRM_CAP_DUMB_BUFFER 0x1 +#define DRM_CAP_HIGH_CRTC 0x2 /* typedef area */ #ifndef __KERNEL__

6 14

[Bug 35471] [r300g]3d apps crashing
by bugzilla-daemon＠freedesktop.org 22 Mar '11

22 Mar '11

https://bugs.freedesktop.org/show_bug.cgi?id=35471 --- Comment #1 from Marek Olšák <maraeo(a)gmail.com> 2011-03-22 05:46:45 PDT --- I can't reproduce this bug with r300g from git. What driver are you using? Please attach your glxinfo. Can you by any chance try the r300 gallium3d driver from Mesa git? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

1 0

[Bug 35471] [r300g]3d apps crashing
by bugzilla-daemon＠freedesktop.org 22 Mar '11

22 Mar '11

1 0

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dri-devel March 2011