dri-devel July 2011

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443 discussions

[PATCH 3/6] drm/radeon: Writeback endian fixes
by Benjamin Herrenschmidt 14 Jul '11

14 Jul '11

The writeback ring pointer and IH ring pointer are read using le32_to_cpu so we do not want the chip to byteswap them on big-endian. We still want to byteswap the ring itself and the IBs, so we don't touch that but we remove setting of the byteswap bits in CP_RB_RPTR_ADDR and IH_CNTL. In general, for things like that where we control all the accessors easily, we are better off doing the swap in SW rather than HW. Paradoxally, it does keep the code closer to x86 and avoid using poorly tested HW features. I also changed the use of RADEON_ to R600_ in a couple of cases to be more consistent with the surrounding code. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- (resent adding dri-devel to the CC list to hit patchwork) drivers/gpu/drm/radeon/evergreen.c | 3 --- drivers/gpu/drm/radeon/r600.c | 7 ------- drivers/gpu/drm/radeon/r600_cp.c | 23 +++++++++-------------- 3 files changed, 9 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index e8a5ffb..23cf089 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1359,9 +1359,6 @@ int evergreen_cp_resume(struct radeon_device *rdev) /* set the wb address wether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, -#ifdef __BIG_ENDIAN - RB_RPTR_SWAP(2) | -#endif ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index f79d2cc..3c86b15 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2212,9 +2212,6 @@ int r600_cp_resume(struct radeon_device *rdev) /* set the wb address whether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, -#ifdef __BIG_ENDIAN - RB_RPTR_SWAP(2) | -#endif ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); @@ -2993,10 +2990,6 @@ int r600_irq_init(struct radeon_device *rdev) /* RPTR_REARM only works if msi's are enabled */ if (rdev->msi_enabled) ih_cntl |= RPTR_REARM; - -#ifdef __BIG_ENDIAN - ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); -#endif WREG32(IH_CNTL, ih_cntl); /* force the active interrupt state to all disabled */ diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index c3ab959..45fd592 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -1802,8 +1802,8 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, /* Set ring buffer size */ #ifdef __BIG_ENDIAN RADEON_WRITE(R600_CP_RB_CNTL, - RADEON_BUF_SWAP_32BIT | - RADEON_RB_NO_UPDATE | + R600_BUF_SWAP_32BIT | + R600_RB_NO_UPDATE | (dev_priv->ring.rptr_update_l2qw << 8) | dev_priv->ring.size_l2qw); #else @@ -1820,15 +1820,15 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, #ifdef __BIG_ENDIAN RADEON_WRITE(R600_CP_RB_CNTL, - RADEON_BUF_SWAP_32BIT | - RADEON_RB_NO_UPDATE | - RADEON_RB_RPTR_WR_ENA | + R600_BUF_SWAP_32BIT | + R600_RB_NO_UPDATE | + R600_RB_RPTR_WR_ENA | (dev_priv->ring.rptr_update_l2qw << 8) | dev_priv->ring.size_l2qw); #else RADEON_WRITE(R600_CP_RB_CNTL, - RADEON_RB_NO_UPDATE | - RADEON_RB_RPTR_WR_ENA | + R600_RB_NO_UPDATE | + R600_RB_RPTR_WR_ENA | (dev_priv->ring.rptr_update_l2qw << 8) | dev_priv->ring.size_l2qw); #endif @@ -1851,13 +1851,8 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, - ((unsigned long) dev->sg->virtual) + dev_priv->gart_vm_start; } - RADEON_WRITE(R600_CP_RB_RPTR_ADDR, -#ifdef __BIG_ENDIAN - (2 << 0) | -#endif - (rptr_addr & 0xfffffffc)); - RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, - upper_32_bits(rptr_addr)); + RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc)); + RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); #ifdef __BIG_ENDIAN RADEON_WRITE(R600_CP_RB_CNTL,

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[PATCH] i915: slab shrinker have to return -1 if it can't shrink any objects
by KOSAKI Motohiro 14 Jul '11

14 Jul '11

Now, i915_gem_inactive_shrink() should return -1 instead of 0 if it can't take a lock. Otherwise, vmscan is getting a lot of confusing because vmscan can't distinguish "can't take a lock temporary" and "we've shrank all of i915 objects". Signed-off-by: KOSAKI Motohiro <kosaki.motohiro(a)jp.fujitsu.com> Cc: Keith Packard <keithp(a)keithp.com> Cc: David Airlie <airlied(a)linux.ie> Cc: dri-devel(a)lists.freedesktop.org --- I've found this issue by reviewing. I hope i915 developers confirm this. Thx. drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 94c84d7..2f9a9b2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4104,7 +4104,7 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) int cnt; if (!mutex_trylock(&dev->struct_mutex)) - return 0; + return nr_to_scan ? -1 : 0; /* "fast-path" to count number of available objects */ if (nr_to_scan == 0) { -- 1.7.3.1

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[RFC] drm platform multi-device support
by Rob Clark 14 Jul '11

14 Jul '11

From: Rob Clark <robdclark(a)gmail.com> Include the minor device id in the bus-id to give userspace a way to open the correct "cardN" when there are multiple device instances. --- It may seem a bit strange to have multiple platform device instances, but we have a use-case for this. And this relatively simple patch does the trick. drivers/gpu/drm/drm_ioctl.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 47db4df..075024b 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -165,14 +165,15 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv) drm_unset_busid(dev, master); if (drm_core_check_feature(dev, DRIVER_USE_PLATFORM_DEVICE)) { - master->unique_len = 10 + strlen(dev->platformdev->name); + master->unique_len = 13 + strlen(dev->platformdev->name); + master->unique_size = master->unique_len; master->unique = kmalloc(master->unique_len + 1, GFP_KERNEL); if (master->unique == NULL) return -ENOMEM; len = snprintf(master->unique, master->unique_len, - "platform:%s", dev->platformdev->name); + "platform:%s:%02d", dev->platformdev->name, dev->primary->index); if (len > master->unique_len) { DRM_ERROR("Unique buffer overflowed\n"); -- 1.7.1

4 6

[PATCH 2/6] drm/radeon: ATOM Endian fix for atombios_crtc_program_pll()
by Benjamin Herrenschmidt 14 Jul '11

14 Jul '11

v6 of the structure was programmed incorrectly: args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); ulPixelClock is a 24-bit bitfield. This statement would thus do a 32-bit swap of (clock / 10) and drop the top 8 bits which are ... the LSB. Not what we want. Instead use masks & shifts. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- (resent adding dri-devel to the CC list to hit patchwork) drivers/gpu/drm/radeon/atombios_crtc.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 9541995..c742944 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -764,7 +764,7 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, } static void atombios_crtc_program_pll(struct drm_crtc *crtc, - int crtc_id, + u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, @@ -851,8 +851,7 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, args.v5.ucPpll = pll_id; break; case 6: - args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id; - args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); + args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); args.v6.ucRefDiv = ref_div; args.v6.usFbDiv = cpu_to_le16(fb_div); args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);

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[PATCH v2 1/2] radeon: Don't generate new fence for page flip.
by Michel Dänzer 14 Jul '11

14 Jul '11

From: Michel Dänzer <michel.daenzer(a)amd.com> Use the fence of the new frontbuffer, if any. Generating a new fence could cause us to wait for completely unrelated rendering to finish before performing the flip. Signed-off-by: Michel Dänzer <michel.daenzer(a)amd.com> --- v2: * Rebase against drm-core-next. * Leave radeon_fence_unref() call in error path, or we leak the fence there. drivers/gpu/drm/radeon/radeon_display.c | 33 +++++------------------------- 1 files changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 292f73f..ffce85a 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -282,7 +282,7 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) spin_lock_irqsave(&rdev->ddev->event_lock, flags); work = radeon_crtc->unpin_work; if (work == NULL || - !radeon_fence_signaled(work->fence)) { + (work->fence && !radeon_fence_signaled(work->fence))) { spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); return; } @@ -348,7 +348,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, struct radeon_framebuffer *new_radeon_fb; struct drm_gem_object *obj; struct radeon_bo *rbo; - struct radeon_fence *fence; struct radeon_unpin_work *work; unsigned long flags; u32 tiling_flags, pitch_pixels; @@ -359,16 +358,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, if (work == NULL) return -ENOMEM; - r = radeon_fence_create(rdev, &fence); - if (unlikely(r != 0)) { - kfree(work); - DRM_ERROR("flip queue: failed to create fence.\n"); - return -ENOMEM; - } work->event = event; work->rdev = rdev; work->crtc_id = radeon_crtc->crtc_id; - work->fence = radeon_fence_ref(fence); old_radeon_fb = to_radeon_framebuffer(crtc->fb); new_radeon_fb = to_radeon_framebuffer(fb); /* schedule unpin of the old buffer */ @@ -377,6 +369,10 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, drm_gem_object_reference(obj); rbo = gem_to_radeon_bo(obj); work->old_rbo = rbo; + obj = new_radeon_fb->obj; + rbo = gem_to_radeon_bo(obj); + if (rbo->tbo.sync_obj) + work->fence = radeon_fence_ref(rbo->tbo.sync_obj); INIT_WORK(&work->work, radeon_unpin_work_func); /* We borrow the event spin lock for protecting unpin_work */ @@ -391,9 +387,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, spin_unlock_irqrestore(&dev->event_lock, flags); /* pin the new buffer */ - obj = new_radeon_fb->obj; - rbo = gem_to_radeon_bo(obj); - DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", work->old_rbo, rbo); @@ -461,25 +454,11 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, goto pflip_cleanup1; } - /* 32 ought to cover us */ - r = radeon_ring_lock(rdev, 32); - if (r) { - DRM_ERROR("failed to lock the ring before flip\n"); - goto pflip_cleanup2; - } - - /* emit the fence */ - radeon_fence_emit(rdev, fence); /* set the proper interrupt */ radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); - /* fire the ring */ - radeon_ring_unlock_commit(rdev); return 0; -pflip_cleanup2: - drm_vblank_put(dev, radeon_crtc->crtc_id); - pflip_cleanup1: r = radeon_bo_reserve(rbo, false); if (unlikely(r != 0)) { @@ -501,7 +480,7 @@ pflip_cleanup: unlock_free: drm_gem_object_unreference_unlocked(old_radeon_fb->obj); spin_unlock_irqrestore(&dev->event_lock, flags); - radeon_fence_unref(&fence); + radeon_fence_unref(&work->fence); kfree(work); return r; -- 1.7.5.4

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[PATCH] drm/i915: Add quirk to disable SSC on Lenovo U160 LVDS
by Keith Packard 13 Jul '11

13 Jul '11

We've tried several times to make this machine 'just work', but every patch that does causes many other machines to fail. This adds a quirk which special cases this hardware and forces ssc to be disabled. There's no way to override this from the command line; that would be a significantly more invasive change. Signed-off-by: Keith Packard <keithp(a)keithp.com> Tested-by: Robse <rob-se(a)live.de> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++++++- 2 files changed, 15 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f245c58..6042921 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -262,6 +262,7 @@ enum intel_pch { }; #define QUIRK_PIPEA_FORCE (1<<0) +#define QUIRK_LVDS_SSC_DISABLE (1<<1) struct intel_fbdev; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 21b6f93..252c6f0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4305,7 +4305,8 @@ static void intel_update_watermarks(struct drm_device *dev) static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) { - return dev_priv->lvds_use_ssc && i915_panel_use_ssc; + return dev_priv->lvds_use_ssc && i915_panel_use_ssc + && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); } static int i9xx_crtc_mode_set(struct drm_crtc *crtc, @@ -7810,6 +7811,15 @@ static void quirk_pipea_force (struct drm_device *dev) DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); } +/* + * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason + */ +static void quirk_ssc_force_disable (struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; +} + struct intel_quirk { int device; int subsystem_vendor; @@ -7838,6 +7848,9 @@ struct intel_quirk intel_quirks[] = { /* 855 & before need to leave pipe A & dpll A up */ { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, + + /* Lenovo U160 cannot use SSC on LVDS */ + { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, }; static void intel_init_quirks(struct drm_device *dev) -- 1.7.5.4 -- keith.packard(a)intel.com

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[PULL] drm-intel-next
by Keith Packard 13 Jul '11

13 Jul '11

Here's most of the patches I'm hoping to land after 3.0: * FBC cleanups from Chris Wilson. Fixes 'missing' CPU writes to the front buffer. We've enabled FBC by default, if we find regressions again, we'll turn it off before the release. * DP and HDMI support for formats other than 8bpc from Jesse Barnes. Supports depth 30 frame buffers at 10bpc. * Shared LLC support (SNB, IVB) from Eric Anholt and Chris Wilson. Shares the LLC between CPU and GPU, avoiding main memory traffic latencies. * Ring frequency scaling (SNB, IVB) from Jesse Barnes. This makes memory bus speed track the GPU clock in addition to the CPU clock, keeping memory running at full speed when the GPU is busy and the CPU is idle. * Disable hangcheck module parameter from Ben Widawsky. This exports a module parameter to keep the kernel from resetting the GPU. It's useful for GPU debugging where the GPU may be stuck waiting for the debugger. The following changes since commit a94919eaddaa3fede1df8563ce4d761a75374645: drm/i915/ringbuffer: Idling requires waiting for the ring to be empty (2011-07-12 10:35:45 -0700) are available in the git repository at: ssh://master.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6.git drm-intel-next Ben Widawsky (1): drm/i915: hangcheck disable parameter Chris Wilson (14): drm/i915: Introduce i915_gem_object_finish_gpu() drm/i915: Introduce i915_gem_object_finish_gtt() drm/i915/gtt: Split out i915_gem_gtt_rebind_object() drm/i915: Add an interface to dynamically change the cache level drm/i915: Mark the cursor and the overlay as being part of the display planes drm/i915: Combine pinning with setting to the display plane drm/i915: Only export the generic intel_disable_fbc() interface drm/i915: Replace direct calls to vfunc.disable_fbc with intel_disable_fbc() drm/i915: Remove vestigial pitch from post-gen2 FBC control routines drm/i915: Use of a CPU fence is mandatory to update FBC regions upon CPU writes drm/i915: Set persistent-mode for ILK/SNB framebuffer compression drm/i915: Disable FBC across page-flipping drm/i915: Perform intel_enable_fbc() from a delayed task drm/i915: Share the common work of disabling active FBC before updating Eric Anholt (2): drm/i915: Use the uncached domain for the display planes drm/i915: Use the LLC mode on gen6 for everything but display. Hugh Dickins (1): drm/i915: more struct_mutex locking Jesse Barnes (13): cpufreq: expose a cpufreq_quick_get_max routine drm/i915: load a ring frequency scaling table v3 drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3 drm/i915: don't set SDVO color range on ILK+ drm/i915: don't set transcoder bpc on CougarPoint drm/i915: set bpc for DP transcoder drm/i915: split out Ironlake pipe bpp picking code drm/i915: split out plane update code drm/i915: use pipe bpp in DP link bandwidth calculations drm/i915: use pipe bpp when setting HDMI bpc drm: bpp and depth changes require full mode sets drm/i915: check for supported depth at fb init time drm/i915: use pipe bpp in DP link bandwidth calculation Keith Packard (14): drm/i915: i915_gem_object_finish_gtt must always release gtt mmap drm/i915: Enable i915 frame buffer compression by default drivers/cpufreq/cpufreq.c | 20 + drivers/gpu/drm/drm_crtc_helper.c | 5 + drivers/gpu/drm/i915/i915_debugfs.c | 41 ++- drivers/gpu/drm/i915/i915_dma.c | 4 +- drivers/gpu/drm/i915/i915_drv.c | 5 +- drivers/gpu/drm/i915/i915_drv.h | 27 +- drivers/gpu/drm/i915/i915_gem.c | 191 ++++++++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +- drivers/gpu/drm/i915/i915_irq.c | 13 +- drivers/gpu/drm/i915/i915_reg.h | 5 +- drivers/gpu/drm/i915/i915_suspend.c | 8 +- drivers/gpu/drm/i915/intel_display.c | 699 +++++++++++++++++++++++-------- drivers/gpu/drm/i915/intel_dp.c | 17 +- drivers/gpu/drm/i915/intel_drv.h | 9 + drivers/gpu/drm/i915/intel_hdmi.c | 8 +- drivers/gpu/drm/i915/intel_overlay.c | 6 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +- include/linux/cpufreq.h | 5 + 18 files changed, 842 insertions(+), 266 deletions(-) -- keith.packard(a)intel.com

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Unchecked memory allocations in Intel driver
by Alan Cox 13 Jul '11

13 Jul '11

Found this going over intel_bios.c and cross comparing it with the Intel/IMG driver intel_bios.c temp_mode = kzalloc(sizeof(*temp_mode), GFP_KERNEL); temp_downclock = panel_fixed_mode->clock; /* * enumerate the LVDS panel timing info entry in VBT to check whether * the LVDS downclock is found. */ for (i = 0; i < 16; i++) { entry = (struct bdb_lvds_lfp_data_entry *) ((uint8_t *)lvds_lfp_data->data + (lfp_data_size * i)); dvo_timing = (struct lvds_dvo_timing *) ((unsigned char *)entry + dvo_timing_offset); fill_detail_timing_data(temp_mode, dvo_timing); The one for IMG devices (GMA500 etc) has an additional unchecked kmalloc which the i915 driver has fixed.

3 4

drm_lock()->block_all_signals() is broken
by Oleg Nesterov 13 Jul '11

13 Jul '11

Hello. I tried many times to ask about the supposed behaviour of block_all_signals() in drm, but it seems nobody can answer. So I am going to send the patch which simply removes block_all_signals() and friends. There are numeruous problems with this interace, I can't even enumerate them. But I think that it is enough to mention that block_all_signals() simply can not work. AT ALL. I am wondering, was it ever tested and how. So. ioctl()->drm_lock() "blocks" the stop signals. Probably to ensure the task can't be stopped until it does DRM_IOCTL_UNLOCK. And what does this mean? Yes, the task won't stop if it receives, say, SIGTSTP. But! Instead it will loop forever in kernel mode until it receives another unblocked/non-ignored signal which should be numerically less than SIGSTOP. Why do we need this? Once again. block_all_signals(SIGTSTP) only means that the caller will burn cpu instead of sleeping in TASK_STOPPED after ^Z. What is the point? And once again, there are other problems. For example, even if block_all_signals() actually blocked SIGSTOP/etc, this can not help if the caller is multithreaded. I strongly believe block_all_signals() should die. Given that it doesn't work, could somebody please explain me what will be broken? Just in case... Please look at the debugging patch below. With this patch, $ perl -le 'syscall 157,666 and die $!; sleep 1, print while ++$_' 1 2 3 ^Z Hang. So it does react to ^Z anyway, just it is looping in the endless loop in the kernel. It can only look as if ^Z is ignored, because obviously bash doesn't see it stopped. Now lets look at drm_notifier(). If it returns 0 it does: /* Otherwise, set flag to force call to drmUnlock */ drmUnlock? grep shows nothing... do { old = s->lock->lock; new = old | _DRM_LOCK_CONT; prev = cmpxchg(&s->lock->lock, old, new); } while (prev != old); return 0; OK. So, if block_all_signals() makes any sense, it seems that this is only because we add _DRM_LOCK_CONT. Who checks _DRM_LOCK_CONT? _DRM_LOCK_IS_CONT(), but it has no users. Hmm. Looks like via_release_futex() is the only user, but it doesn't look as "force call to drmUnlock" and it is CONFIG_DRM_VIA only. I am totally confused. But block_all_signals() should die anyway. We can probably implement something like 'i-am-going-to-stop' or even 'can-i-stop' per-thread notifiers, although this all looks like the user-space problem to me (yes, I know absolutely nothing about drm/etc). If nothing else. We can change drm_lock/drm_unlock to literally block/unblock SIGSTOP/etc (or perhaps we only should worry about the signals from tty?). This is the awful hack and this can't work with the multithreaded tasks too, but still it is better than what we have now. Oleg. --- a/kernel/sys.c~ 2011-06-16 20:12:18.000000000 +0200 +++ b/kernel/sys.c 2011-07-12 16:24:50.000000000 +0200 @@ -1614,6 +1614,11 @@ SYSCALL_DEFINE1(umask, int, mask) return mask; } +static int notifier(void *arg) +{ + return 0; +} + SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, unsigned long, arg4, unsigned long, arg5) { @@ -1627,6 +1632,13 @@ SYSCALL_DEFINE5(prctl, int, option, unsi error = 0; switch (option) { + case 666: { + sigset_t *pmask = kmalloc(sizeof(*pmask), GFP_KERNEL); + siginitset(pmask, sigmask(SIGTSTP)); + block_all_signals(notifier, NULL, pmask); + break; + } + case PR_SET_PDEATHSIG: if (!valid_signal(arg2)) { error = -EINVAL;

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[PATCH 5/6] drm/radeon: Do an MMIO read on interrupts when not uisng MSIs
by Benjamin Herrenschmidt 13 Jul '11

13 Jul '11

When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- (resent adding dri-devel to the CC list to hit patchwork) drivers/gpu/drm/radeon/r600.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7e5c801..25b2dab 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -3300,6 +3300,10 @@ int r600_irq_process(struct radeon_device *rdev) if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE; + /* No MSIs, need a dummy read to flush PCI DMAs */ + if (!rdev->msi_enabled) + RREG32(IH_RB_WPTR); + wptr = r600_get_ih_wptr(rdev); rptr = rdev->ih.rptr; DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);

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dri-devel July 2011