dri-devel October 2012

dri-devel@lists.freedesktop.org

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712 discussions

[RFC libdrm] freedreno: add freedreno DRM
by Rob Clark 08 Oct '12

08 Oct '12

The libdrm_freedreno helper layer for use by xf86-video-freedreno, fdre (freedreno r/e library and tests for driving gpu), and eventual gallium driver for the Adreno GPU. This uses the msm gpu driver from QCOM's android kernel tree. Note that current msm kernel driver is a bit strange. It provides a DRM interface for GEM, which is basically sufficient to have DRI2 working. But it does not provide KMS. And interface to 2d and 3d cores is via different other devices (/dev/kgsl-*). This is not quite how I'd write a DRM driver, but at this stage it is useful for xf86-video-freedreno and fdre (and eventual gallium driver) to be able to work on existing kernel driver from QCOM, to allow to capture cmdstream dumps from the binary blob drivers without having to reboot. So libdrm_freedreno attempts to hide most of the crazy. The intention is that when there is a proper kernel driver, it will be mostly just changes in libdrm_freedreno to adapt the gallium driver and xf86-video-freedreno (ignoring the fbdev->KMS changes). So don't look at freedreno as an example of how to write a libdrm module or a DRM driver.. it is just an attempt to paper over a non- standard kernel driver architecture. Signed-off-by: Rob Clark <robclark(a)freedesktop.org> --- .gitignore | 1 + Makefile.am | 6 +- configure.ac | 13 + freedreno/Makefile.am | 19 ++ freedreno/README | 16 ++ freedreno/freedreno_bo.c | 229 +++++++++++++++++ freedreno/freedreno_device.c | 45 ++++ freedreno/freedreno_drmif.h | 97 +++++++ freedreno/freedreno_pipe.c | 163 ++++++++++++ freedreno/freedreno_priv.h | 90 +++++++ freedreno/freedreno_ringbuffer.c | 123 +++++++++ freedreno/freedreno_ringbuffer.h | 75 ++++++ freedreno/kgsl_drm.h | 192 ++++++++++++++ freedreno/libdrm_freedreno.pc.in | 11 + freedreno/msm_kgsl.h | 519 ++++++++++++++++++++++++++++++++++++++ 15 files changed, 1598 insertions(+), 1 deletion(-) create mode 100644 freedreno/Makefile.am create mode 100644 freedreno/README create mode 100644 freedreno/freedreno_bo.c create mode 100644 freedreno/freedreno_device.c create mode 100644 freedreno/freedreno_drmif.h create mode 100644 freedreno/freedreno_pipe.c create mode 100644 freedreno/freedreno_priv.h create mode 100644 freedreno/freedreno_ringbuffer.c create mode 100644 freedreno/freedreno_ringbuffer.h create mode 100644 freedreno/kgsl_drm.h create mode 100644 freedreno/libdrm_freedreno.pc.in create mode 100644 freedreno/msm_kgsl.h diff --git a/.gitignore b/.gitignore index 243457e..a20a3eb 100644 --- a/.gitignore +++ b/.gitignore @@ -42,6 +42,7 @@ libdrm.pc libdrm_intel.pc libdrm_nouveau.pc libdrm_radeon.pc +libdrm_freedreno.pc libkms.pc libtool ltmain.sh diff --git a/Makefile.am b/Makefile.am index 8ecd9d9..ebf2ae2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -49,7 +49,11 @@ if HAVE_EXYNOS EXYNOS_SUBDIR = exynos endif -SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) tests include man +if HAVE_FREEDRENO +FREEDRENO_SUBDIR = freedreno +endif + +SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) $(FREEDRENO_SUBDIR) tests include man libdrm_la_LTLIBRARIES = libdrm.la libdrm_ladir = $(libdir) diff --git a/configure.ac b/configure.ac index 290362c..8ce6011 100644 --- a/configure.ac +++ b/configure.ac @@ -114,6 +114,11 @@ AC_ARG_ENABLE(exynos-experimental-api, [Enable support for EXYNOS's experimental API (default: disabled)]), [EXYNOS=$enableval], [EXYNOS=no]) +AC_ARG_ENABLE(freedreno-experimental-api, + AS_HELP_STRING([--enable-freedreno-experimental-api], + [Enable support for freedreno's experimental API (default: disabled)]), + [FREEDRENO=$enableval], [FREEDRENO=no]) + dnl =========================================================================== dnl check compiler flags AC_DEFUN([LIBDRM_CC_TRY_FLAG], [ @@ -222,6 +227,11 @@ if test "x$EXYNOS" = xyes; then AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support]) fi +AM_CONDITIONAL(HAVE_FREEDRENO, [test "x$FREEDRENO" = xyes]) +if test "x$FREEDRENO" = xyes; then + AC_DEFINE(HAVE_FREEDRENO, 1, [Have freedreno support]) +fi + PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) if test "x$HAVE_CAIRO" = xyes; then AC_DEFINE(HAVE_CAIRO, 1, [Have cairo support]) @@ -346,6 +356,8 @@ AC_CONFIG_FILES([ omap/libdrm_omap.pc exynos/Makefile exynos/libdrm_exynos.pc + freedreno/Makefile + freedreno/libdrm_freedreno.pc tests/Makefile tests/modeprint/Makefile tests/modetest/Makefile @@ -368,4 +380,5 @@ echo " Radeon API $RADEON" echo " Nouveau API $NOUVEAU" echo " OMAP API $OMAP" echo " EXYNOS API $EXYNOS" +echo " Freedreno API $FREEDRENO" echo "" diff --git a/freedreno/Makefile.am b/freedreno/Makefile.am new file mode 100644 index 0000000..f46a780 --- /dev/null +++ b/freedreno/Makefile.am @@ -0,0 +1,19 @@ +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/freedreno \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_freedreno_la_LTLIBRARIES = libdrm_freedreno.la +libdrm_freedreno_ladir = $(libdir) +libdrm_freedreno_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_freedreno_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ + +libdrm_freedreno_la_SOURCES = freedreno_device.c freedreno_pipe.c freedreno_ringbuffer.c freedreno_bo.c + +libdrm_freedrenocommonincludedir = ${includedir}/freedreno +libdrm_freedrenocommoninclude_HEADERS = freedreno_drmif.h freedreno_ringbuffer.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm_freedreno.pc diff --git a/freedreno/README b/freedreno/README new file mode 100644 index 0000000..ae22e01 --- /dev/null +++ b/freedreno/README @@ -0,0 +1,16 @@ +Note that current msm kernel driver is a bit strange. It provides a +DRM interface for GEM, which is basically sufficient to have DRI2 +working. But it does not provide KMS. And interface to 2d and 3d +cores is via different other devices (/dev/kgsl-*). This is not +quite how I'd write a DRM driver, but at this stage it is useful for +xf86-video-freedreno and fdre (and eventual gallium driver) to be +able to work on existing kernel driver from QCOM, to allow to +capture cmdstream dumps from the binary blob drivers without having +to reboot. So libdrm_freedreno attempts to hide most of the crazy. +The intention is that when there is a proper kernel driver, it will +be mostly just changes in libdrm_freedreno to adapt the gallium +driver and xf86-video-freedreno (ignoring the fbdev->KMS changes). + +So don't look at freedreno as an example of how to write a libdrm +module or a DRM driver.. it is just an attempt to paper over a non- +standard kernel driver architecture. diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c new file mode 100644 index 0000000..84526d5 --- /dev/null +++ b/freedreno/freedreno_bo.c @@ -0,0 +1,229 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#include "freedreno_drmif.h" +#include "freedreno_priv.h" + +static struct fd_bo * bo_from_handle(struct fd_device *dev, + uint32_t size, uint32_t handle) +{ + struct fd_bo *bo = calloc(1, sizeof(*bo)); + if (!bo) + return NULL; + bo->dev = dev; + bo->size = size; + bo->handle = handle; + return bo; +} + +static int set_memtype(struct fd_bo *bo, uint32_t flags) +{ + struct drm_kgsl_gem_memtype req = { + .handle = bo->handle, + .type = flags & DRM_FREEDRENO_GEM_TYPE_MEM_MASK, + }; + + return drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_SETMEMTYPE, + &req, sizeof(req)); +} + +static int bo_alloc(struct fd_bo *bo) +{ + if (!bo->offset) { + struct drm_kgsl_gem_alloc req = { + .handle = bo->handle, + }; + int ret; + + /* if the buffer is already backed by pages then this + * doesn't actually do anything (other than giving us + * the offset) + */ + ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_ALLOC, + &req, sizeof(req)); + if (ret) { + ERROR_MSG("alloc failed: %s", strerror(errno)); + return ret; + } + + bo->offset = req.offset; + } + return 0; +} + +struct fd_bo * fd_bo_new(struct fd_device *dev, + uint32_t size, uint32_t flags) +{ + struct drm_kgsl_gem_create req = { + .size = size, + }; + struct fd_bo *bo = NULL; + + if (drmCommandWriteRead(dev->fd, DRM_KGSL_GEM_CREATE, + &req, sizeof(req))) { + return NULL; + } + + bo = bo_from_handle(dev, size, req.handle); + if (!bo) { + goto fail; + } + + if (set_memtype(bo, flags)) { + goto fail; + } + + return bo; +fail: + if (bo) + fd_bo_del(bo); + return NULL; +} + +/* don't use this... it is just needed to get a bo from the + * framebuffer (pre-dmabuf) + */ +struct fd_bo * fd_bo_from_fbdev(struct fd_device *dev, + int fbfd, uint32_t size) +{ + struct drm_kgsl_gem_create_fd req = { + .fd = fbfd, + }; + + if (drmCommandWriteRead(dev->fd, DRM_KGSL_GEM_CREATE_FD, + &req, sizeof(req))) { + return NULL; + } + + return bo_from_handle(dev, size, req.handle); +} + +struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name) +{ + struct drm_gem_open req = { + .name = name, + }; + + if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) { + return NULL; + } + + return bo_from_handle(dev, req.size, req.handle); +} + +void fd_bo_del(struct fd_bo *bo) +{ + if (bo->map) { + munmap(bo->map, bo->size); + } + + if (bo->handle) { + struct drm_gem_close req = { + .handle = bo->handle, + }; + drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req); + } + + free(bo); +} + +int fd_bo_get_name(struct fd_bo *bo, uint32_t *name) +{ + if (!bo->name) { + struct drm_gem_flink req = { + .handle = bo->handle, + }; + int ret; + + ret = drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_FLINK, &req); + if (ret) { + return ret; + } + + bo->name = req.name; + } + + *name = bo->name; + + return 0; +} + +uint32_t fd_bo_handle(struct fd_bo *bo) +{ + return bo->handle; +} + +uint32_t fd_bo_size(struct fd_bo *bo) +{ + return bo->size; +} + +void * fd_bo_map(struct fd_bo *bo) +{ + if (!bo->map) { + int ret; + + ret = bo_alloc(bo); + if (ret) { + return NULL; + } + + bo->map = mmap(0, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED, + bo->dev->fd, bo->offset); + if (bo->map == MAP_FAILED) { + ERROR_MSG("mmap failed: %s", strerror(errno)); + bo->map = NULL; + } + } + return bo->map; +} + +uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset) +{ + if (!bo->gpuaddr) { + struct drm_kgsl_gem_bufinfo req = { + .handle = bo->handle, + }; + int ret; + + ret = bo_alloc(bo); + if (ret) { + return ret; + } + + ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO, + &req, sizeof(req)); + if (ret) { + ERROR_MSG("alloc failed: %s", strerror(errno)); + return ret; + } + + bo->gpuaddr = req.gpuaddr[0]; + } + return bo->gpuaddr + offset; +} diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c new file mode 100644 index 0000000..0a9ef9f --- /dev/null +++ b/freedreno/freedreno_device.c @@ -0,0 +1,45 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#include "freedreno_drmif.h" +#include "freedreno_priv.h" + +struct fd_device * fd_device_new(int fd) +{ + struct fd_device *dev = calloc(1, sizeof(*dev)); + if (!dev) + return NULL; + dev->fd = fd; + return dev; +} + +void fd_device_del(struct fd_device *dev) +{ + free(dev); +} + diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h new file mode 100644 index 0000000..10273a3 --- /dev/null +++ b/freedreno/freedreno_drmif.h @@ -0,0 +1,97 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#ifndef FREEDRENO_DRMIF_H_ +#define FREEDRENO_DRMIF_H_ + +#include <xf86drm.h> +#include <stdint.h> + +struct fd_bo; +struct fd_pipe; +struct fd_device; + +enum fd_pipe_id { + FD_PIPE_3D = 1, + FD_PIPE_2D = 2, + /* some devices have two 2d blocks.. not really sure how to + * use that yet, so just ignoring the 2nd 2d pipe for now + */ + FD_PIPE_MAX +}; + +enum fd_param { + FD_DEVICE_ID, + FD_GMEM_SIZE, +}; + +/* bo flags: */ +#define DRM_FREEDRENO_GEM_TYPE_SMI 0x00000001 +#define DRM_FREEDRENO_GEM_TYPE_KMEM 0x00000002 +#define DRM_FREEDRENO_GEM_TYPE_MEM_MASK 0x0000000f +#define DRM_FREEDRENO_GEM_CACHE_NONE 0x00000000 +#define DRM_FREEDRENO_GEM_CACHE_WCOMBINE 0x00100000 +#define DRM_FREEDRENO_GEM_CACHE_WTHROUGH 0x00200000 +#define DRM_FREEDRENO_GEM_CACHE_WBACK 0x00400000 +#define DRM_FREEDRENO_GEM_CACHE_WBACKWA 0x00800000 +#define DRM_FREEDRENO_GEM_CACHE_MASK 0x00f00000 +#define DRM_FREEDRENO_GEM_GPUREADONLY 0x01000000 + + +/* device functions: + */ + +struct fd_device * fd_device_new(int fd); +void fd_device_del(struct fd_device *dev); + + +/* pipe functions: + */ + +struct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id); +void fd_pipe_del(struct fd_pipe *pipe); +int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param param, + uint64_t *value); +int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp); + + +/* buffer-object functions: + */ + +struct fd_bo * fd_bo_new(struct fd_device *dev, + uint32_t size, uint32_t flags); +struct fd_bo * fd_bo_from_fbdev(struct fd_device *dev, + int fbfd, uint32_t size); +struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name); +void fd_bo_del(struct fd_bo *bo); +int fd_bo_get_name(struct fd_bo *bo, uint32_t *name); +uint32_t fd_bo_handle(struct fd_bo *bo); +uint32_t fd_bo_size(struct fd_bo *bo); +void * fd_bo_map(struct fd_bo *bo); + +#endif /* FREEDRENO_DRMIF_H_ */ diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c new file mode 100644 index 0000000..ed0928d --- /dev/null +++ b/freedreno/freedreno_pipe.c @@ -0,0 +1,163 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#include "freedreno_drmif.h" +#include "freedreno_priv.h" + + +static int getprop(int fd, enum kgsl_property_type type, + void *value, int sizebytes) +{ + struct kgsl_device_getproperty req = { + .type = type, + .value = value, + .sizebytes = sizebytes, + }; + return ioctl(fd, IOCTL_KGSL_DEVICE_GETPROPERTY, &req); +} + +#define GETPROP(fd, prop, x) do { \ + if (getprop((fd), KGSL_PROP_##prop, &(x), sizeof(x))) { \ + ERROR_MSG("failed to get property: " #prop); \ + goto fail; \ + } } while (0) + + +struct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) +{ + static const char *paths[] = { + [FD_PIPE_3D] = "/dev/kgsl-3d0", + [FD_PIPE_2D] = "/dev/kgsl-2d0", + }; + struct kgsl_drawctxt_create req = { + .flags = 0x2000, /* ??? */ + }; + struct fd_pipe *pipe = NULL; + int ret, fd; + + if (id > FD_PIPE_MAX) { + ERROR_MSG("invalid pipe id: %d", id); + goto fail; + } + + fd = open(paths[id], O_RDWR); + if (fd < 0) { + ERROR_MSG("could not open %s device: %d (%s)", + paths[id], fd, strerror(errno)); + goto fail; + } + + ret = ioctl(fd, IOCTL_KGSL_DRAWCTXT_CREATE, &req); + if (ret) { + ERROR_MSG("failed to allocate context: %d (%s)", + ret, strerror(errno)); + goto fail; + } + + pipe = calloc(1, sizeof(*pipe)); + if (!pipe) { + ERROR_MSG("allocation failed"); + goto fail; + } + + pipe->dev = dev; + pipe->fd = fd; + pipe->drawctxt_id = req.drawctxt_id; + + GETPROP(fd, VERSION, pipe->version); + GETPROP(fd, DEVICE_INFO, pipe->devinfo); + + INFO_MSG("Pipe Info:"); + INFO_MSG(" Device: %s", paths[id]); + INFO_MSG(" Chip-id: %d.%d.%d.%d", + (pipe->devinfo.chip_id >> 24) & 0xff, + (pipe->devinfo.chip_id >> 16) & 0xff, + (pipe->devinfo.chip_id >> 8) & 0xff, + (pipe->devinfo.chip_id >> 0) & 0xff); + INFO_MSG(" Device-id: %d", pipe->devinfo.device_id); + INFO_MSG(" GPU-id: %d", pipe->devinfo.gpu_id); + INFO_MSG(" MMU enabled: %d", pipe->devinfo.mmu_enabled); + INFO_MSG(" GMEM Base addr: 0x%08x", pipe->devinfo.gmem_gpubaseaddr); + INFO_MSG(" GMEM size: 0x%08x", pipe->devinfo.gmem_sizebytes); + INFO_MSG(" Driver version: %d.%d", + pipe->version.drv_major, pipe->version.drv_minor); + INFO_MSG(" Device version: %d.%d", + pipe->version.dev_major, pipe->version.dev_minor); + + return pipe; +fail: + if (pipe) + fd_pipe_del(pipe); + return NULL; +} + +void fd_pipe_del(struct fd_pipe *pipe) +{ + struct kgsl_drawctxt_destroy req = { + .drawctxt_id = pipe->drawctxt_id, + }; + + if (pipe->drawctxt_id) + ioctl(pipe->fd, IOCTL_KGSL_DRAWCTXT_DESTROY, &req); + + if (pipe->fd) + close(pipe->fd); + + free(pipe); +} + +int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param param, + uint64_t *value) +{ + switch (param) { + case FD_DEVICE_ID: + *value = pipe->devinfo.device_id; + return 0; + case FD_GMEM_SIZE: + *value = pipe->devinfo.gmem_sizebytes; + return 0; + default: + ERROR_MSG("invalid param id: %d", param); + return -1; + } +} + +int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp) +{ + struct kgsl_device_waittimestamp req = { + .timestamp = timestamp, + .timeout = 5000, + }; + int ret; + + ret = ioctl(pipe->fd, IOCTL_KGSL_DEVICE_WAITTIMESTAMP, &req); + if (ret) + ERROR_MSG("waittimestamp failed! %d (%s)", ret, strerror(errno)); + + return ret; +} diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h new file mode 100644 index 0000000..68bd5a6 --- /dev/null +++ b/freedreno/freedreno_priv.h @@ -0,0 +1,90 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#ifndef FREEDRENO_PRIV_H_ +#define FREEDRENO_PRIV_H_ + +#include <stdlib.h> +#include <errno.h> +#include <string.h> +#include <unistd.h> +#include <errno.h> +#include <fcntl.h> +#include <sys/ioctl.h> +#include <sys/mman.h> + +#include "freedreno_drmif.h" +#include "msm_kgsl.h" +#include "kgsl_drm.h" + +struct fd_device { + int fd; +}; + +struct fd_pipe { + struct fd_device *dev; + int fd; + uint32_t drawctxt_id; + + /* device properties: */ + struct kgsl_version version; + struct kgsl_devinfo devinfo; +}; + +struct fd_bo { + struct fd_device *dev; + uint32_t size; + uint32_t handle; + uint32_t name; + uint32_t gpuaddr; + void *map; + uint64_t offset; +}; + +/* not exposed publicly, because won't be needed when we have + * a proper kernel driver + */ +uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset); + + +#define enable_debug 1 /* TODO make dynamic */ + +#define INFO_MSG(fmt, ...) \ + do { drmMsg("[I] "fmt " (%s:%d)\n", \ + ##__VA_ARGS__, __FUNCTION__, __LINE__); } while (0) +#define DEBUG_MSG(fmt, ...) \ + do if (enable_debug) { printf("[D] "fmt " (%s:%d)\n", \ + ##__VA_ARGS__, __FUNCTION__, __LINE__); } while (0) +#define WARN_MSG(fmt, ...) \ + do { drmMsg("[W] "fmt " (%s:%d)\n", \ + ##__VA_ARGS__, __FUNCTION__, __LINE__); } while (0) +#define ERROR_MSG(fmt, ...) \ + do { drmMsg("[E] " fmt " (%s:%d)\n", \ + ##__VA_ARGS__, __FUNCTION__, __LINE__); } while (0) + +#endif /* FREEDRENO_PRIV_H_ */ diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c new file mode 100644 index 0000000..93ca843 --- /dev/null +++ b/freedreno/freedreno_ringbuffer.c @@ -0,0 +1,123 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#include "freedreno_drmif.h" +#include "freedreno_priv.h" +#include "freedreno_ringbuffer.h" + +struct fd_ringbuffer * fd_ringbuffer_new(struct fd_pipe *pipe, + uint32_t size) +{ + struct fd_ringbuffer *ring = NULL; + + ring = calloc(1, sizeof(*ring)); + if (!ring) { + ERROR_MSG("allocation failed"); + goto fail; + } + + ring->bo = fd_bo_new(pipe->dev, size, DRM_FREEDRENO_GEM_GPUREADONLY | + DRM_FREEDRENO_GEM_TYPE_KMEM); + if (!ring->bo) { + ERROR_MSG("ringbuffer allocation failed"); + goto fail; + } + + ring->pipe = pipe; + ring->start = fd_bo_map(ring->bo); + ring->end = &(ring->start[size/4]); + + fd_ringbuffer_reset(ring); + + return ring; +fail: + if (ring) + fd_ringbuffer_del(ring); + return NULL; +} + +void fd_ringbuffer_del(struct fd_ringbuffer *ring) +{ + if (ring->bo) + fd_bo_del(ring->bo); + free(ring); +} + +void fd_ringbuffer_reset(struct fd_ringbuffer *ring) +{ + ring->cur = ring->last_start = ring->start; +} + +int fd_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t flags, + uint32_t *timestamp) +{ + struct kgsl_ibdesc ibdesc = { + .gpuaddr = fd_bo_gpuaddr(ring->bo, ring->last_start - ring->start), + .hostptr = ring->last_start, + .sizedwords = ring->cur - ring->last_start, + }; + struct kgsl_ringbuffer_issueibcmds req = { + .drawctxt_id = ring->pipe->drawctxt_id, + .ibdesc_addr = (unsigned long)&ibdesc, + .numibs = 1, + .flags = flags, + }; + int ret; + + ret = ioctl(ring->pipe->fd, IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS, &req); + if (ret) + ERROR_MSG("issueibcmds failed! %d (%s)", ret, strerror(errno)); + + *timestamp = req.timestamp; + ring->last_start = ring->cur; + + return ret; +} + +int fd_ringbuffer_begin(struct fd_ringbuffer *ring, int ndwords) +{ + int ret; + if ((ring->cur + ndwords) >= ring->end) { + uint32_t timestamp; + /* this probably won't really work if we have multiple tiles.. + * but it is ok for 2d.. we might need different behavior + * depending on 2d or 3d pipe. + */ + WARN_MSG("unexpected flush"); + ret = fd_ringbuffer_flush(ring, 0, &timestamp); + fd_ringbuffer_reset(ring); + return ret; + } + return 0; +} + +void fd_ringbuffer_emit_reloc(struct fd_ringbuffer *ring, + struct fd_bo *bo, uint32_t offset) +{ + fd_ringbuffer_emit(ring, fd_bo_gpuaddr(bo, offset)); +} diff --git a/freedreno/freedreno_ringbuffer.h b/freedreno/freedreno_ringbuffer.h new file mode 100644 index 0000000..c502202 --- /dev/null +++ b/freedreno/freedreno_ringbuffer.h @@ -0,0 +1,75 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2012 Rob Clark <robclark(a)freedesktop.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <robclark(a)freedesktop.org> + */ + +#ifndef FREEDRENO_RINGBUFFER_H_ +#define FREEDRENO_RINGBUFFER_H_ + +#include <freedreno_drmif.h> + +/* the ringbuffer object is not opaque so that OUT_RING() type stuff + * can be inlined. Note that users should not make assumptions about + * the size of this struct.. more stuff will be added when we eventually + * have a kernel driver that can deal w/ reloc's.. + */ + +struct fd_ringbuffer { + int size; + uint32_t *cur, *end, *start, *last_start; + struct fd_pipe *pipe; + struct fd_bo *bo; +}; + +/* ringbuffer flush flags: + * SAVE_GMEM - GMEM contents not preserved to system memory + * in cmds flushed so if there is a context switch after + * this flush and before the next one the kernel must + * save GMEM contents + * SUBMIT_IB_LIST - tbd.. + */ +#define DRM_FREEDRENO_CONTEXT_SAVE_GMEM 1 +#define DRM_FREEDRENO_CONTEXT_SUBMIT_IB_LIST 4 + + +struct fd_ringbuffer * fd_ringbuffer_new(struct fd_pipe *pipe, + uint32_t size); +void fd_ringbuffer_del(struct fd_ringbuffer *ring); +void fd_ringbuffer_reset(struct fd_ringbuffer *ring); +int fd_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t flags, + uint32_t *timestamp); +int fd_ringbuffer_begin(struct fd_ringbuffer *ring, int ndwords); + +static inline void fd_ringbuffer_emit(struct fd_ringbuffer *ring, + uint32_t data) +{ + (*ring->cur++) = data; +} + +void fd_ringbuffer_emit_reloc(struct fd_ringbuffer *ring, + struct fd_bo *bo, uint32_t offset); + +#endif /* FREEDRENO_RINGBUFFER_H_ */ diff --git a/freedreno/kgsl_drm.h b/freedreno/kgsl_drm.h new file mode 100644 index 0000000..f1c7f4e --- /dev/null +++ b/freedreno/kgsl_drm.h @@ -0,0 +1,192 @@ +#ifndef _KGSL_DRM_H_ +#define _KGSL_DRM_H_ + +#include "drm.h" + +#define DRM_KGSL_GEM_CREATE 0x00 +#define DRM_KGSL_GEM_PREP 0x01 +#define DRM_KGSL_GEM_SETMEMTYPE 0x02 +#define DRM_KGSL_GEM_GETMEMTYPE 0x03 +#define DRM_KGSL_GEM_MMAP 0x04 +#define DRM_KGSL_GEM_ALLOC 0x05 +#define DRM_KGSL_GEM_BIND_GPU 0x06 +#define DRM_KGSL_GEM_UNBIND_GPU 0x07 + +#define DRM_KGSL_GEM_GET_BUFINFO 0x08 +#define DRM_KGSL_GEM_SET_BUFCOUNT 0x09 +#define DRM_KGSL_GEM_SET_ACTIVE 0x0A +#define DRM_KGSL_GEM_LOCK_HANDLE 0x0B +#define DRM_KGSL_GEM_UNLOCK_HANDLE 0x0C +#define DRM_KGSL_GEM_UNLOCK_ON_TS 0x0D +#define DRM_KGSL_GEM_CREATE_FD 0x0E + +#define DRM_IOCTL_KGSL_GEM_CREATE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE, struct drm_kgsl_gem_create) + +#define DRM_IOCTL_KGSL_GEM_PREP \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_PREP, struct drm_kgsl_gem_prep) + +#define DRM_IOCTL_KGSL_GEM_SETMEMTYPE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SETMEMTYPE, \ +struct drm_kgsl_gem_memtype) + +#define DRM_IOCTL_KGSL_GEM_GETMEMTYPE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GETMEMTYPE, \ +struct drm_kgsl_gem_memtype) + +#define DRM_IOCTL_KGSL_GEM_MMAP \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_MMAP, struct drm_kgsl_gem_mmap) + +#define DRM_IOCTL_KGSL_GEM_ALLOC \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_ALLOC, struct drm_kgsl_gem_alloc) + +#define DRM_IOCTL_KGSL_GEM_BIND_GPU \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_BIND_GPU, struct drm_kgsl_gem_bind_gpu) + +#define DRM_IOCTL_KGSL_GEM_UNBIND_GPU \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNBIND_GPU, \ +struct drm_kgsl_gem_bind_gpu) + +#define DRM_IOCTL_KGSL_GEM_GET_BUFINFO \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_BUFINFO, \ + struct drm_kgsl_gem_bufinfo) + +#define DRM_IOCTL_KGSL_GEM_SET_BUFCOUNT \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_BUFCOUNT, \ + struct drm_kgsl_gem_bufcount) + +#define DRM_IOCTL_KGSL_GEM_SET_ACTIVE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_ACTIVE, \ + struct drm_kgsl_gem_active) + +#define DRM_IOCTL_KGSL_GEM_LOCK_HANDLE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_LOCK_HANDLE, \ +struct drm_kgsl_gem_lock_handles) + +#define DRM_IOCTL_KGSL_GEM_UNLOCK_HANDLE \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_HANDLE, \ +struct drm_kgsl_gem_unlock_handles) + +#define DRM_IOCTL_KGSL_GEM_UNLOCK_ON_TS \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_ON_TS, \ +struct drm_kgsl_gem_unlock_on_ts) + +#define DRM_IOCTL_KGSL_GEM_CREATE_FD \ +DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FD, \ +struct drm_kgsl_gem_create_fd) + +/* Maximum number of sub buffers per GEM object */ +#define DRM_KGSL_GEM_MAX_BUFFERS 2 + +/* Memory types - these define the source and caching policies + of the GEM memory chunk */ + +/* Legacy definitions left for compatability */ + +#define DRM_KGSL_GEM_TYPE_EBI 0 +#define DRM_KGSL_GEM_TYPE_SMI 1 +#define DRM_KGSL_GEM_TYPE_KMEM 2 +#define DRM_KGSL_GEM_TYPE_KMEM_NOCACHE 3 +#define DRM_KGSL_GEM_TYPE_MEM_MASK 0xF + +/* Contiguous memory (PMEM) */ +#define DRM_KGSL_GEM_TYPE_PMEM 0x000100 + +/* PMEM memory types */ +#define DRM_KGSL_GEM_PMEM_EBI 0x001000 +#define DRM_KGSL_GEM_PMEM_SMI 0x002000 + +/* Standard paged memory */ +#define DRM_KGSL_GEM_TYPE_MEM 0x010000 + +/* Caching controls */ +#define DRM_KGSL_GEM_CACHE_NONE 0x000000 +#define DRM_KGSL_GEM_CACHE_WCOMBINE 0x100000 +#define DRM_KGSL_GEM_CACHE_WTHROUGH 0x200000 +#define DRM_KGSL_GEM_CACHE_WBACK 0x400000 +#define DRM_KGSL_GEM_CACHE_WBACKWA 0x800000 +#define DRM_KGSL_GEM_CACHE_MASK 0xF00000 + +/* FD based objects */ +#define DRM_KGSL_GEM_TYPE_FD_FBMEM 0x1000000 +#define DRM_KGSL_GEM_TYPE_FD_MASK 0xF000000 + +/* Timestamp types */ +#define DRM_KGSL_GEM_TS_3D 0x00000430 +#define DRM_KGSL_GEM_TS_2D 0x00000180 + + +struct drm_kgsl_gem_create { + uint32_t size; + uint32_t handle; +}; + +struct drm_kgsl_gem_prep { + uint32_t handle; + uint32_t phys; + uint64_t offset; +}; + +struct drm_kgsl_gem_memtype { + uint32_t handle; + uint32_t type; +}; + +struct drm_kgsl_gem_mmap { + uint32_t handle; + uint32_t size; + uint32_t hostptr; + uint64_t offset; +}; + +struct drm_kgsl_gem_alloc { + uint32_t handle; + uint64_t offset; +}; + +struct drm_kgsl_gem_bind_gpu { + uint32_t handle; + uint32_t gpuptr; +}; + +struct drm_kgsl_gem_bufinfo { + uint32_t handle; + uint32_t count; + uint32_t active; + uint32_t offset[DRM_KGSL_GEM_MAX_BUFFERS]; + uint32_t gpuaddr[DRM_KGSL_GEM_MAX_BUFFERS]; +}; + +struct drm_kgsl_gem_bufcount { + uint32_t handle; + uint32_t bufcount; +}; + +struct drm_kgsl_gem_active { + uint32_t handle; + uint32_t active; +}; + +struct drm_kgsl_gem_lock_handles { + uint32_t num_handles; + uint32_t *handle_list; + uint32_t pid; + uint32_t lock_id; /* Returned lock id used for unlocking */ +}; + +struct drm_kgsl_gem_unlock_handles { + uint32_t lock_id; +}; + +struct drm_kgsl_gem_unlock_on_ts { + uint32_t lock_id; + uint32_t timestamp; /* This field is a hw generated ts */ + uint32_t type; /* Which pipe to check for ts generation */ +}; + +struct drm_kgsl_gem_create_fd { + uint32_t fd; + uint32_t handle; +}; + +#endif diff --git a/freedreno/libdrm_freedreno.pc.in b/freedreno/libdrm_freedreno.pc.in new file mode 100644 index 0000000..95ec1c3 --- /dev/null +++ b/freedreno/libdrm_freedreno.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_freedreno +Description: Userspace interface to freedreno kernel DRM services +Version: 0.6 +Libs: -L${libdir} -ldrm_freedreno +Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/freedreno +Requires.private: libdrm diff --git a/freedreno/msm_kgsl.h b/freedreno/msm_kgsl.h new file mode 100644 index 0000000..e67190f --- /dev/null +++ b/freedreno/msm_kgsl.h @@ -0,0 +1,519 @@ +#ifndef _MSM_KGSL_H +#define _MSM_KGSL_H + +#define KGSL_VERSION_MAJOR 3 +#define KGSL_VERSION_MINOR 11 + +/*context flags */ +#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 +#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 +#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 +#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 +#define KGSL_CONTEXT_PREAMBLE 0x00000010 +#define KGSL_CONTEXT_TRASH_STATE 0x00000020 +#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 + +#define KGSL_CONTEXT_INVALID 0xffffffff + +/* Memory allocayion flags */ +#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 + +/* generic flag values */ +#define KGSL_FLAGS_NORMALMODE 0x00000000 +#define KGSL_FLAGS_SAFEMODE 0x00000001 +#define KGSL_FLAGS_INITIALIZED0 0x00000002 +#define KGSL_FLAGS_INITIALIZED 0x00000004 +#define KGSL_FLAGS_STARTED 0x00000008 +#define KGSL_FLAGS_ACTIVE 0x00000010 +#define KGSL_FLAGS_RESERVED0 0x00000020 +#define KGSL_FLAGS_RESERVED1 0x00000040 +#define KGSL_FLAGS_RESERVED2 0x00000080 +#define KGSL_FLAGS_SOFT_RESET 0x00000100 +#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 + +/* Clock flags to show which clocks should be controled by a given platform */ +#define KGSL_CLK_SRC 0x00000001 +#define KGSL_CLK_CORE 0x00000002 +#define KGSL_CLK_IFACE 0x00000004 +#define KGSL_CLK_MEM 0x00000008 +#define KGSL_CLK_MEM_IFACE 0x00000010 +#define KGSL_CLK_AXI 0x00000020 + +/* + * Reset status values for context + */ +enum kgsl_ctx_reset_stat { + KGSL_CTX_STAT_NO_ERROR = 0x00000000, + KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, + KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, + KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 +}; + +#define KGSL_MAX_PWRLEVELS 5 + +#define KGSL_CONVERT_TO_MBPS(val) \ + (val*1000*1000U) + +/* device id */ +enum kgsl_deviceid { + KGSL_DEVICE_3D0 = 0x00000000, + KGSL_DEVICE_2D0 = 0x00000001, + KGSL_DEVICE_2D1 = 0x00000002, + KGSL_DEVICE_MAX = 0x00000003 +}; + +enum kgsl_user_mem_type { + KGSL_USER_MEM_TYPE_PMEM = 0x00000000, + KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, + KGSL_USER_MEM_TYPE_ADDR = 0x00000002, + KGSL_USER_MEM_TYPE_ION = 0x00000003, + KGSL_USER_MEM_TYPE_MAX = 0x00000004, +}; + +struct kgsl_devinfo { + + unsigned int device_id; + /* chip revision id + * coreid:8 majorrev:8 minorrev:8 patch:8 + */ + unsigned int chip_id; + unsigned int mmu_enabled; + unsigned int gmem_gpubaseaddr; + /* + * This field contains the adreno revision + * number 200, 205, 220, etc... + */ + unsigned int gpu_id; + unsigned int gmem_sizebytes; +}; + +/* this structure defines the region of memory that can be mmap()ed from this + driver. The timestamp fields are volatile because they are written by the + GPU +*/ +struct kgsl_devmemstore { + volatile unsigned int soptimestamp; + unsigned int sbz; + volatile unsigned int eoptimestamp; + unsigned int sbz2; + volatile unsigned int ts_cmp_enable; + unsigned int sbz3; + volatile unsigned int ref_wait_ts; + unsigned int sbz4; + unsigned int current_context; + unsigned int sbz5; +}; + +#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \ + ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \ + offsetof(struct kgsl_devmemstore, field)) + +/* timestamp id*/ +enum kgsl_timestamp_type { + KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */ + KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/ + KGSL_TIMESTAMP_QUEUED = 0x00000003, +}; + +/* property types - used with kgsl_device_getproperty */ +enum kgsl_property_type { + KGSL_PROP_DEVICE_INFO = 0x00000001, + KGSL_PROP_DEVICE_SHADOW = 0x00000002, + KGSL_PROP_DEVICE_POWER = 0x00000003, + KGSL_PROP_SHMEM = 0x00000004, + KGSL_PROP_SHMEM_APERTURES = 0x00000005, + KGSL_PROP_MMU_ENABLE = 0x00000006, + KGSL_PROP_INTERRUPT_WAITS = 0x00000007, + KGSL_PROP_VERSION = 0x00000008, + KGSL_PROP_GPU_RESET_STAT = 0x00000009, + KGSL_PROP_PWRCTRL = 0x0000000E, +}; + +struct kgsl_shadowprop { + unsigned int gpuaddr; + unsigned int size; + unsigned int flags; /* contains KGSL_FLAGS_ values */ +}; + +struct kgsl_pwrlevel { + unsigned int gpu_freq; + unsigned int bus_freq; + unsigned int io_fraction; +}; + +struct kgsl_version { + unsigned int drv_major; + unsigned int drv_minor; + unsigned int dev_major; + unsigned int dev_minor; +}; + +#ifdef __KERNEL__ + +#define KGSL_3D0_REG_MEMORY "kgsl_3d0_reg_memory" +#define KGSL_3D0_IRQ "kgsl_3d0_irq" +#define KGSL_2D0_REG_MEMORY "kgsl_2d0_reg_memory" +#define KGSL_2D0_IRQ "kgsl_2d0_irq" +#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory" +#define KGSL_2D1_IRQ "kgsl_2d1_irq" + +enum kgsl_iommu_context_id { + KGSL_IOMMU_CONTEXT_USER = 0, + KGSL_IOMMU_CONTEXT_PRIV = 1, +}; + +struct kgsl_iommu_ctx { + const char *iommu_ctx_name; + enum kgsl_iommu_context_id ctx_id; +}; + +struct kgsl_device_iommu_data { + const struct kgsl_iommu_ctx *iommu_ctxs; + int iommu_ctx_count; + unsigned int physstart; + unsigned int physend; +}; + +struct kgsl_device_platform_data { + struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS]; + int init_level; + int num_levels; + int (*set_grp_async)(void); + unsigned int idle_timeout; + bool strtstp_sleepwake; + unsigned int nap_allowed; + unsigned int clk_map; + unsigned int idle_needed; + struct msm_bus_scale_pdata *bus_scale_table; + struct kgsl_device_iommu_data *iommu_data; + int iommu_count; + struct msm_dcvs_core_info *core_info; +}; + +#endif + +/* structure holds list of ibs */ +struct kgsl_ibdesc { + unsigned int gpuaddr; + void *hostptr; + unsigned int sizedwords; + unsigned int ctrl; +}; + +/* ioctls */ +#define KGSL_IOC_TYPE 0x09 + +/* get misc info about the GPU + type should be a value from enum kgsl_property_type + value points to a structure that varies based on type + sizebytes is sizeof() that structure + for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo + this structure contaings hardware versioning info. + for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop + this is used to find mmap() offset and sizes for mapping + struct kgsl_memstore into userspace. +*/ +struct kgsl_device_getproperty { + unsigned int type; + void *value; + unsigned int sizebytes; +}; + +#define IOCTL_KGSL_DEVICE_GETPROPERTY \ + _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) + +/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012 + */ + +/* block until the GPU has executed past a given timestamp + * timeout is in milliseconds. + */ +struct kgsl_device_waittimestamp { + unsigned int timestamp; + unsigned int timeout; +}; + +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \ + _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) + +struct kgsl_device_waittimestamp_ctxtid { + unsigned int context_id; + unsigned int timestamp; + unsigned int timeout; +}; + +#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \ + _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) + +/* issue indirect commands to the GPU. + * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE + * ibaddr and sizedwords must specify a subset of a buffer created + * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM + * flags may be a mask of KGSL_CONTEXT_ values + * timestamp is a returned counter value which can be passed to + * other ioctls to determine when the commands have been executed by + * the GPU. + */ +struct kgsl_ringbuffer_issueibcmds { + unsigned int drawctxt_id; + unsigned int ibdesc_addr; + unsigned int numibs; + unsigned int timestamp; /*output param */ + unsigned int flags; +}; + +#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \ + _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) + +/* read the most recently executed timestamp value + * type should be a value from enum kgsl_timestamp_type + */ +struct kgsl_cmdstream_readtimestamp { + unsigned int type; + unsigned int timestamp; /*output param */ +}; + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \ + _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \ + _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) + +/* free memory when the GPU reaches a given timestamp. + * gpuaddr specify a memory region created by a + * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call + * type should be a value from enum kgsl_timestamp_type + */ +struct kgsl_cmdstream_freememontimestamp { + unsigned int gpuaddr; + unsigned int type; + unsigned int timestamp; +}; + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \ + _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) + +/* Previous versions of this header had incorrectly defined + IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead + of a write only ioctl. To ensure binary compatability, the following + #define will be used to intercept the incorrect ioctl +*/ + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \ + _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) + +/* create a draw context, which is used to preserve GPU state. + * The flags field may contain a mask KGSL_CONTEXT_* values + */ +struct kgsl_drawctxt_create { + unsigned int flags; + unsigned int drawctxt_id; /*output param */ +}; + +#define IOCTL_KGSL_DRAWCTXT_CREATE \ + _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) + +/* destroy a draw context */ +struct kgsl_drawctxt_destroy { + unsigned int drawctxt_id; +}; + +#define IOCTL_KGSL_DRAWCTXT_DESTROY \ + _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) + +/* add a block of pmem, fb, ashmem or user allocated address + * into the GPU address space */ +struct kgsl_map_user_mem { + int fd; + unsigned int gpuaddr; /*output param */ + unsigned int len; + unsigned int offset; + unsigned int hostptr; /*input param */ + enum kgsl_user_mem_type memtype; + unsigned int reserved; /* May be required to add + params for another mem type */ +}; + +#define IOCTL_KGSL_MAP_USER_MEM \ + _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) + +struct kgsl_cmdstream_readtimestamp_ctxtid { + unsigned int context_id; + unsigned int type; + unsigned int timestamp; /*output param */ +}; + +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \ + _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) + +struct kgsl_cmdstream_freememontimestamp_ctxtid { + unsigned int context_id; + unsigned int gpuaddr; + unsigned int type; + unsigned int timestamp; +}; + +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \ + _IOW(KGSL_IOC_TYPE, 0x17, \ + struct kgsl_cmdstream_freememontimestamp_ctxtid) + +/* add a block of pmem or fb into the GPU address space */ +struct kgsl_sharedmem_from_pmem { + int pmem_fd; + unsigned int gpuaddr; /*output param */ + unsigned int len; + unsigned int offset; +}; + +#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \ + _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) + +/* remove memory from the GPU's address space */ +struct kgsl_sharedmem_free { + unsigned int gpuaddr; +}; + +#define IOCTL_KGSL_SHAREDMEM_FREE \ + _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) + +struct kgsl_cff_user_event { + unsigned char cff_opcode; + unsigned int op1; + unsigned int op2; + unsigned int op3; + unsigned int op4; + unsigned int op5; + unsigned int __pad[2]; +}; + +#define IOCTL_KGSL_CFF_USER_EVENT \ + _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) + +struct kgsl_gmem_desc { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int pitch; +}; + +struct kgsl_buffer_desc { + void *hostptr; + unsigned int gpuaddr; + int size; + unsigned int format; + unsigned int pitch; + unsigned int enabled; +}; + +struct kgsl_bind_gmem_shadow { + unsigned int drawctxt_id; + struct kgsl_gmem_desc gmem_desc; + unsigned int shadow_x; + unsigned int shadow_y; + struct kgsl_buffer_desc shadow_buffer; + unsigned int buffer_id; +}; + +#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \ + _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) + +/* add a block of memory into the GPU address space */ +struct kgsl_sharedmem_from_vmalloc { + unsigned int gpuaddr; /*output param */ + unsigned int hostptr; + unsigned int flags; +}; + +#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \ + _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) + +#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \ + _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) + +struct kgsl_drawctxt_set_bin_base_offset { + unsigned int drawctxt_id; + unsigned int offset; +}; + +#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \ + _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) + +enum kgsl_cmdwindow_type { + KGSL_CMDWINDOW_MIN = 0x00000000, + KGSL_CMDWINDOW_2D = 0x00000000, + KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */ + KGSL_CMDWINDOW_MMU = 0x00000002, + KGSL_CMDWINDOW_ARBITER = 0x000000FF, + KGSL_CMDWINDOW_MAX = 0x000000FF, +}; + +/* write to the command window */ +struct kgsl_cmdwindow_write { + enum kgsl_cmdwindow_type target; + unsigned int addr; + unsigned int data; +}; + +#define IOCTL_KGSL_CMDWINDOW_WRITE \ + _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) + +struct kgsl_gpumem_alloc { + unsigned long gpuaddr; + size_t size; + unsigned int flags; +}; + +#define IOCTL_KGSL_GPUMEM_ALLOC \ + _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) + +struct kgsl_cff_syncmem { + unsigned int gpuaddr; + unsigned int len; + unsigned int __pad[2]; /* For future binary compatibility */ +}; + +#define IOCTL_KGSL_CFF_SYNCMEM \ + _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) + +/* + * A timestamp event allows the user space to register an action following an + * expired timestamp. + */ + +struct kgsl_timestamp_event { + int type; /* Type of event (see list below) */ + unsigned int timestamp; /* Timestamp to trigger event on */ + unsigned int context_id; /* Context for the timestamp */ + void *priv; /* Pointer to the event specific blob */ + size_t len; /* Size of the event specific blob */ +}; + +#define IOCTL_KGSL_TIMESTAMP_EVENT \ + _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) + +/* A genlock timestamp event releases an existing lock on timestamp expire */ + +#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 + +struct kgsl_timestamp_event_genlock { + int handle; /* Handle of the genlock lock to release */ +}; + +/* + * Set a property within the kernel. Uses the same structure as + * IOCTL_KGSL_GETPROPERTY + */ + +#define IOCTL_KGSL_SETPROPERTY \ + _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) + +#ifdef __KERNEL__ +#ifdef CONFIG_MSM_KGSL_DRM +int kgsl_gem_obj_addr(int drm_fd, int handle, unsigned long *start, + unsigned long *len); +#else +#define kgsl_gem_obj_addr(...) 0 +#endif +#endif +#endif /* _MSM_KGSL_H */ -- 1.7.9.5

1 0

[PATCH] drm/i915: remove duplicated include from intel_modes.c
by Wei Yongjun 07 Oct '12

07 Oct '12

From: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> Remove duplicated include. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> --- drivers/gpu/drm/i915/intel_modes.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c index cabd84b..8c97b7a 100644 --- a/drivers/gpu/drm/i915/intel_modes.c +++ b/drivers/gpu/drm/i915/intel_modes.c @@ -28,7 +28,6 @@ #include <linux/fb.h> #include <drm/drm_edid.h> #include <drm/drmP.h> -#include <drm/drm_edid.h> #include "intel_drv.h" #include "i915_drv.h"

2 1

question about drivers/gpu/drm/i915/dvo_ch7xxx.c
by Julia Lawall 07 Oct '12

07 Oct '12

Hello, I am looking at introducing some macros for i2c_msg initialization, and Ryan Mallon suggested that sometimes it could be useful to at the same time replace explicit lengths with the size of the associated buffer. But in some cases the sizes are not the same. An example is as follows, in drivers/gpu/drm/i915/dvo_ch7xxx.c: static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) { struct ch7xxx_priv *ch7xxx = dvo->dev_priv; struct i2c_adapter *adapter = dvo->i2c_bus; u8 out_buf[2]; u8 in_buf[2]; struct i2c_msg msgs[] = { { .addr = dvo->slave_addr, .flags = 0, .len = 1, .buf = out_buf, }, { .addr = dvo->slave_addr, .flags = I2C_M_RD, .len = 1, .buf = in_buf, } }; out_buf[0] = addr; out_buf[1] = 0; if (i2c_transfer(adapter, msgs, 2) == 2) { *ch = in_buf[0]; return true; }; if (!ch7xxx->quiet) { DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", addr, adapter->name, dvo->slave_addr); } return false; } The buffers both have size 2, but only one byte is asked to be read or written. Is there any need for the buffers to have size 2 in this case? Unrelatedly, is it correct that ch has type uint8_t and out_buf and in_buf have type u8? julia

2 1

[3.2.y] drm/i915: add Ivy Bridge GT2 Server entries
by Jonathan Nieder 07 Oct '12

07 Oct '12

Hi Ben, Please consider cc22a938fc1d drm/i915: add Ivy Bridge GT2 Server entries, 2012-03-29 for application to the 3.2.y tree. It adds a PCI id to the i915 driver, making kms work. It was applied during the 3.4-rc2 cycle, so newer stable kernels don't need it. Maik Zumstrull tried it[1] on top of 3.2.30 and found it to work ok (thanks!). Note that pre-2.4.34 versions of libdrm don't cope well with that card, with or without this patch: - without this patch, modern X errors out instead of starting, because the intel driver requires kms. (In a hypothetical better world, userspace would know to fall back to vesa or something.) - with this patch and with libdrm patch 2.4.34~22 (intel: add Ivy Bridge GT2 server variant, 2012-03-29), X should work great - with this patch, without libdrm 2.4.34~22, but with libdrm patch 2.4.38~10 (intel: Bail gracefully if we encounter an unknown Intel device, 2012-07-25) applied, X should error out instead of starting - with this patch, and with libdrm lacking 2.4.34~22 and 2.4.38~10, X freezes at startup. "No regressions" means you probably shouldn't take this patch without a safety to work around the old X userspace, unless you can shout enough in release notes to get people to apply 2.4.38~10 to libdrm and maintain sanity. ;) Hmm? Jonathan [1] http://bugs.debian.org/684767

5 7

[PATCH 1/5] dma-buf: remove fallback for !CONFIG_DMA_SHARED_BUFFER
by Maarten Lankhorst 07 Oct '12

07 Oct '12

Documentation says that code requiring dma-buf should add it to select, so inline fallbacks are not going to be used. A link error will make it obvious what went wrong, instead of silently doing nothing at runtime. Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)canonical.com> --- include/linux/dma-buf.h | 99 ----------------------------------------------- 1 file changed, 99 deletions(-) diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h index eb48f38..bd2e52c 100644 --- a/include/linux/dma-buf.h +++ b/include/linux/dma-buf.h @@ -156,7 +156,6 @@ static inline void get_dma_buf(struct dma_buf *dmabuf) get_file(dmabuf->file); } -#ifdef CONFIG_DMA_SHARED_BUFFER struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, struct device *dev); void dma_buf_detach(struct dma_buf *dmabuf, @@ -184,103 +183,5 @@ int dma_buf_mmap(struct dma_buf *, struct vm_area_struct *, unsigned long); void *dma_buf_vmap(struct dma_buf *); void dma_buf_vunmap(struct dma_buf *, void *vaddr); -#else - -static inline struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, - struct device *dev) -{ - return ERR_PTR(-ENODEV); -} - -static inline void dma_buf_detach(struct dma_buf *dmabuf, - struct dma_buf_attachment *dmabuf_attach) -{ - return; -} - -static inline struct dma_buf *dma_buf_export(void *priv, - const struct dma_buf_ops *ops, - size_t size, int flags) -{ - return ERR_PTR(-ENODEV); -} - -static inline int dma_buf_fd(struct dma_buf *dmabuf, int flags) -{ - return -ENODEV; -} - -static inline struct dma_buf *dma_buf_get(int fd) -{ - return ERR_PTR(-ENODEV); -} - -static inline void dma_buf_put(struct dma_buf *dmabuf) -{ - return; -} - -static inline struct sg_table *dma_buf_map_attachment( - struct dma_buf_attachment *attach, enum dma_data_direction write) -{ - return ERR_PTR(-ENODEV); -} - -static inline void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, - struct sg_table *sg, enum dma_data_direction dir) -{ - return; -} - -static inline int dma_buf_begin_cpu_access(struct dma_buf *dmabuf, - size_t start, size_t len, - enum dma_data_direction dir) -{ - return -ENODEV; -} - -static inline void dma_buf_end_cpu_access(struct dma_buf *dmabuf, - size_t start, size_t len, - enum dma_data_direction dir) -{ -} - -static inline void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, - unsigned long pnum) -{ - return NULL; -} - -static inline void dma_buf_kunmap_atomic(struct dma_buf *dmabuf, - unsigned long pnum, void *vaddr) -{ -} - -static inline void *dma_buf_kmap(struct dma_buf *dmabuf, unsigned long pnum) -{ - return NULL; -} - -static inline void dma_buf_kunmap(struct dma_buf *dmabuf, - unsigned long pnum, void *vaddr) -{ -} - -static inline int dma_buf_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma, - unsigned long pgoff) -{ - return -ENODEV; -} - -static inline void *dma_buf_vmap(struct dma_buf *dmabuf) -{ - return NULL; -} - -static inline void dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr) -{ -} -#endif /* CONFIG_DMA_SHARED_BUFFER */ #endif /* __DMA_BUF_H__ */

4 26

[PATCH] drm/nouveau: remove duplicated include from nouveau_drm.c
by Wei Yongjun 07 Oct '12

07 Oct '12

From: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> Remove duplicated include. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: Wei Yongjun <yongjun_wei(a)trendmicro.com.cn> --- drivers/gpu/drm/nouveau/nouveau_drm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index ccae8c2..f5c8ccf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -49,7 +49,6 @@ #include "nouveau_fbcon.h" #include "nouveau_fence.h" -#include "nouveau_ttm.h" MODULE_PARM_DESC(config, "option string to pass to driver core"); static char *nouveau_config;

1 0

[git pull] drm merge for rc1 (part 1)
by Dave Airlie 07 Oct '12

07 Oct '12

Hi Linus, So first of all my tree and uapi stuff has a conflict mess, its my fault as the nouveau stuff didn't hit -next as were trying to rebase regressions out of it before we merged. So this pull is for my drm-next-merged branch which is my drm-next branch merged with your tree, and some fixups applied to the merge. Highlights: SH mobile modesetting driver and associated helpers some DRM core documentation i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write combined pte writing, ilk rc6 support, nouveau: major driver rework into a hw core driver, makes features like SLI a lot saner to implement, psb: add eDP/DP support for Cedarview radeon: 2 layer page tables, async VM pte updates, better PLL selection for > 2 screens, better ACPI interactions The rest is general grab bag of fixes. So why part 1? well I have the exynos pull req which came in a bit late but was waiting for me to do something they shouldn't have and it looks fairly safe, and David Howells has some more header cleanups he'd like me to pull, that seem like a good idea, but I'd like to get this merge out of the way so -next dosen't get blocked. Dave. The following changes since commit 3a494318b14b1bc0f59d2d6ce84c505c74d82d2a: Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace (2012-10-03 16:09:09 -0700) are available in the git repository at: git://people.freedesktop.org/~airlied/linux drm-next-merged for you to fetch changes up to a8d5415b0aac6b9fac34c752ed9e09312545f487: drm: Merge remote-tracking branch 'pfdo/drm-next' into linus (2012-10-04 13:25:34 +1000) ---------------------------------------------------------------- Akinobu Mita (1): gpu/drm/ttm: use copy_highpage Alan Cox (6): gma500: Add the support of display port on CDV gma500/cdv: add the bits that don't need the new code gma500/cdv: sync up and add the displayport code to the build gma500/cdv: enable the DisplayPort support gma500/cdv: Fix call to cdv_intel_dp_set_m_n gma500: Fix frequency detection Alex Deucher (45): drm/radeon/dce4+: don't use radeon_crtc for vblank callback drm/radeon: clean up evergreen_get_vblank_counter drm/radeon/r1xx-r4xx: don't use radeon_crtc for vblank callback drm/radeon/r5xx-r7xx: don't use radeon_crtc for vblank callback (v2) drm/radeon: properly handle mc_stop/mc_resume on evergreen+ (v2) drm/radeon/dynpm: wait for fences on all rings when reclocking drm/radeon: remove gui_idle interrupt infrastructure drm/radeon: add new AMD ACPI header and update relevant code (v2) drm/radeon: add a license header to radeon_apci.c drm/radeon: track whether the GPU controls the backlight (v2) drm/radeon: rework legacy backlight control drm/radeon: add backlight control for atom devices (v2) drm/radeon: re-organize the acpi notifier callback drm/radeon: document radeon_acpi.c drm/radeon: update ATPX verify interface handling (v2) drm/radeon: reorganize ATPX support (v2) drm/radeon: document radeon_atpx_handler.c (v2) drm/radeon: add initial support for ATCS ACPI methods drm/radeon: rework the backlight control to be an asic callback drm/radeon/atom: add consolidate bpc code drm/radeon: document async VM changes in ni.c drm/radeon: implement bounds checking on thermal controller lookup drm/radeon: remove dead function def drm/radeon: clean up encoder dp checks drm/radeon: white space cleanup in transmitter setup drm/radeon/atom: fix typo in SetPixelClock handling drm/radeon: fix typo in atombios_get_encoder_mode drm/radeon: rework pll selection (v4) drm/radeon/dce3: use a single PPLL for all DP displays drm/radeon: allow PPLL sharing on non-DP displays drm/radeon: rework crtc pll setup to better support PPLL sharing drm/radeon: store the encoder in the radeon_crtc drm/radeon: make non-DP PPLL sharing more robust drm/radeon: work around KMS modeset limitations in PLL allocation (v2) drm/radeon: validate PPLL in crtc fixup drm/radeon: only adjust default clocks on NI GPUs drm/radeon: add get_backlight_level callback drm/radeon: restore backlight level on resume drm/radeon: Add MSI quirk for gateway RS690 drm/radeon: force MSIs on RS690 asics drm/radeon: fix radeon power state debug output drm/radeon/pm: fix multi-head profile handling on BTC+ (v2) drm/radeon: use WRITE_DATA packets for vm flush on SI drm/radeon: rework the vm_flush interface drm/radeon: add vm set_page() callback for SI Andy Shevchenko (1): drm: use %*ph to dump small buffers Ben Skeggs (85): drm/nvc0/fence: restore pre-suspend fence buffer context on resume drm/nouveau/gem: use bo.offset rather than mm_node.start drm/nouveau: restructure source tree, split core from drm implementation drm/nouveau/agp: move all agp stuff into its own source file drm/nouveau/core: pull in most of the new core infrastructure drm/nouveau: implement module init functions in nouveau_drm.c drm/nouveau: have non-core mmio accesses go through device object drm/nouveau/bios: pull in basic vbios subdev, more to come later drm/nouveau/oldbios: remove shadowing support, use bios subdev's image drm/nouveau/gpio: port gpio to subdev interfaces drm/nouveau/i2c: port to subdev interfaces drm/nouveau/clk: implement stub clock subdev drm/nouveau/clock: pull in the implementation from all over the place drm/nouveau: implement devinit subdev, and new init table parser drm/nouveau/mc: port to subdev interfaces drm/nouveau/timer: port to subdev interfaces drm/nouveau/core: add support for reverse mm allocations drm/nv50-/instmem: allocate vram for kernel objects from end of vram drm/nouveau/fb: merge fb/vram and port to subdev interfaces drm/nv04-nv40/instmem: duplicate nv04 code as nv40, remove alternate paths drm/nv04-nv40/instmem: remove use of nouveau_gpuobj_new_fake() drm/nv04-nv40/fifo: remove use of nouveau_gpuobj_new_fake() drm/nvc0/fifo: handle bar1 control regs much like fifo/nve0 drm/nouveau/gpuobj: create wrapper functions for mapping gpuobj into vm/bar drm/nouveau/gpuobj: remove flags for vm-mappings drm/nv50/instmem: remove use of nouveau_gpuobj_new_fake() drm/nouveau: remove last use of nouveau_gpuobj_new_fake() drm/nouveau/instmem: completely new implementation, as a subdev module drm/nv04/disp: kick all private state out to own header drm/nouveau: pull nouveau_bo definitions into their own header drm/nouveau: pull nouveau_gem definitions into their own header drm/nouveau/fence: un-port from nouveau_exec_engine interfaces drm/nvc0-nve0/graph: rename dev to priv, no code changes drm/nouveau: move some more code around to more appropriate places drm/nouveau/pageflip: kick flip handling out of engsw and into fence drm/nvc0-/gr: share headers between fermi and kepler graphics code drm/nvc0-/gr: generate grctx template at init time, not first context ctor drm/nouveau: port all engines to new engine module format drm/nouveau: start culling unused code drm/nouveau/mxm: split up into bios code and a subdev module drm/nouveau/acpi: move definitions out of nouveau_drv.h drm/nouveau: move compat ioctl out of nouveau_drv.h drm/nouveau: flatten nv{Read,Write}{MC,VIDEO,FB,EXTDEV} drm/nouveau/backlight: remove dependence on nouveau_drv.h drm/nouveau/device: include the official chipset names drm/nouveau: port remainder of drm code, and rip out compat layer drm/nouveau: add Kconfig options for debug control drm/nvc0-/gr: remove reset-after-grctx-construction hack drm/nouveau/core: remove some left-over pieces from the porting process drm/nouveau/device: return proper error codes if ioremap fails drm/nve0/fifo: support engine selection when creating fifo channels drm/nve0/copy: add initial support for the async copy engines drm/nve0: use async copy engine for ttm buffer moves if available drm/nv84/fifo: mask only the engine we're waiting on for channel unload drm/nouveau/core: protect engine context list with hardirq-safe spinlock drm/nouveau/fifo: add method to lookup fifo chid related to a given object drm/nouveau/core: have fifo store a unique context identifier at attach time drm/nouveau: restore fifo chid information in engine error messages drm/nouveau/fifo: separate object classes for dma channels drm/nouveau/fifo: version the dma channel class struct drm/nv84/fifo: add support for dma channel class drm/nv50/fifo: add support for dma channel class drm/nouveau: add defines for internal class names drm/nouveau/dmaobj: reject unsupported parent types instead of half-succeeding drm/nouveau/fifo: use defines instead of hardcoded class ids drm/nouveau/sw: trap and clear PMC_INTR_0_SOFTWARE drm/nve0/ibus: handle PIBUS interrupts to prevent storm drm/nve0/gr: initial fuc implementation, based on fermi's code drm/nve0/gr: remove 0x404160 bashing from hub fuc drm/nve0/gr: enable use of our fuc by default drm/nvc0/ltcg: read LTS count at startup drm/nvc0/gr: rebuild fuc with latest envyas drm/nvc0/gr: implement initial trap handler drm/nvc0/fifo: re-bash PBUS regs after vm-fault to BARs/PEEPHOLE drm/nouveau/core: have client-id be a string, rather than an integer drm/nouveau: have drm debugging macros build on top of core macros drm/nouveau: log channel debug/error messages from client object rather than drm client drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it drm/nvc0/ibus: initial implementation of subdev drm/nouveau: store supported dma mask in vmmgr drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie drm/nv44/vm: fix and enable use of "real" pciegart drm/nv41/vm: fix and enable use of "real" pciegart drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering drm/nv98/crypt: fix fuc build with latest envyas Ben Widawsky (24): drm/i915: add register read IOCTL drm/i915: Add contexts for HSW drm/i915: Macro to determine DPF support drm/i915: Expand DPF support to Haswell drm/i915: Add ERR_INT to gen7 error state drm/i915: Find unclaimed MMIO writes. drm/i915: Extract reading INSTDONE drm/i915: Add new INSTDONE registers drm/i915: Use new INSTDONE registers (Gen7+) drm/i915: Extract forcewake ack timeout drm/i915: use cpu_relax() in wait_for_atomic drm/i915: Change forcewake timeout to 2ms drm/i915: Never read FORCEWAKE drm/i915: Enable some sysfs stuff without CONFIG_PM drm/i915: placeholder getparam drm/i915: variable renames drm/i915: #define gpu freq multipler drm/i915: Add current/max/min GPU freq to sysfs drm/i915: POSTING_READ the new rps value drm/i915: Error checks in gen6_set_rps drm/i915: Add setters for min/max frequency drm/i915: Show render P state thresholds in sysfs drm/i915: Fix !CONFIG_PM sysfs for real this time drm/i915: s/cacheing/caching/ Chris Wilson (43): drm/i915: Cleanup context switching through do_switch() drm/i915: Return a mask of the active rings in the high word of busy_ioctl drm/i915: Allow late allocation of request for i915_add_request() drm/i915: Remove assertion over write domain after i915_gem_object_sync() drm/i915: Replace the pending_gpu_write flag with an explicit seqno drm/i915: Remove the defunct flushing list drm/i915: Remove the per-ring write list drm/i915: Remove explicit flush from i915_gem_object_flush_fence() drm/i915: Remove the explicit flush of the GPU write domain drm/i915: Clear the pending_gpu_fenced_access flag at the start of execbuffer drm/i915: Split i915_gem_flush_ring() into seperate invalidate/flush funcs drm/i915: Avoid concurrent access when marking the device as idle/busy drm/i915: Segregate memory domains in the GTT using coloring drm/i915: Export ability of changing cache levels to userspace drm/i915: Only apply the SNB pipe control w/a to gen6 drm/i915: Add I915_GEM_PARAM_HAS_SEMAPHORES drm/i915: Lazily apply the SNB+ seqno w/a drm/i915: Track unbound pages drm/i915: Add some sanity checks to unbound tracking drm/i915: Show (count, size) of purgeable objects in i915_gem_objects drm/i915: Show pin count in debugfs drm/i915: Try harder to allocate an mmap_offset drm/i915: Cantiga+ cannot handle a hsync front porch of 0 drm/i915: Only pwrite through the GTT if there is space in the aperture drm/i915: Protect private gem objects from truncate (such as imported dmabuf) drm/i915: Extract general object init routine drm/i915: Use cpu relocations if the object is in the GTT but not mappable drm/i915: Juggle code order to ease flow of the next patch drm/i915: Use a non-blocking wait for set-to-domain ioctl drm/i915: Avoid unbinding due to an interrupted pin_and_fence during execbuffer drm/i915: Convert remaining debugfs iterators over rings to for_each_ring() drm/i915: Introduce drm_i915_gem_object_ops drm/i915: Pin backing pages whilst exporting through a dmabuf vmap drm/i915: Pin backing pages for pwrite drm/i915: Pin backing pages for pread drm/i915: Replace the array of pages with a scatterlist drm/i915: Drop the misleading cast to the wrong user pointer type drm/i915: Limit the ioremap of the PCI bar to the registers agp/intel: Use a write-combining map for updating PTEs drm/i915: Convert the dmabuf object to use the new i915_gem_object_ops drm/i915: Assert that the exec object lookup table is a power-of-two drm/i915: Wrap external callers to IPS state with appropriate locks drm: Destroy the planes prior to destroying the associated CRTC Christian König (18): drm/radeon: cleanup VM id handling a bit drm/radeon: move VM funcs into asic structure drm/radeon: remove vm_unbind drm/radeon: add sync helper function drm/radeon: make VM flushs a ring operation drm/radeon: rework VMID handling drm/radeon: rework VM page table handling drm/radeon: Move looping over the PTEs into chip code drm/radeon: make page table updates async v2 drm/radeon: fix VM syncing with multiple rings drm/radeon: fix VA range check drm/radeon: fix VA overlap check drm/radeon: move IB pool to 1MB offset drm/radeon: move and rename radeon_bo_va function drm/radeon: let bo_reserve take no_intr instead of no_wait param drm/radeon: fix gem_close_object handling drm/radeon: rework the VM code a bit more (v2) drm/radeon: refactor set_page chipset interface v5 Damien Lespiau (1): drm/i915: Don't hardcode the number of pipes in the error state dump Dan Carpenter (1): drm/ast: drop duplicate initialization Daniel Vetter (113): drm/i915: group ADPA #defines together drm/i915: simplify possible_clones computation drm/i915: add port parameter to intel_hdmi_init drm/i915: Reserve ioctl numbers for set/get_caching drm/i915: create VLV_DSIPLAY_BASE #define drm/i915: add inte_crt->adpa_reg drm/i915: Replace the complex flushing logic with simple invalidate/flush all drm/i915: Only set the down rps limit when at the loweset frequency drm/i915: rip out sanitize_pm again drm/i915: fixup desired rps frequency computation drm/i915: dump the device info drm/i915: properly guard ilk ips state drm/i915: fixup up debugfs rps state handling drm/i915: use mutex_lock_interruptible for debugfs files drm/i915: move all rps state into dev_priv->rps drm/i915: kill dev_priv->mchdev_lock drm/i915: DE_PCU_EVENT irq is ilk-only drm/i915: fix up ilk drps/ips locking drm/i915: enable rc6 on ilk again drm/i915: don't grab dev->struct_mutex for userspace forcewak Merge tag 'v3.6-rc2' into drm-intel-next drm/i915: add missing gen2 pipe A quirk entries drm/i915/ns2501: kill pll A enabling hack drm/i915: rip out the overlay pipe A workaround drm/i915: prepare load-detect pipe code for dpms changes drm/i915: drop intel_encoder argument to load_detect_pipe functions drm/i915: simplify dvo dpms interface drm/i915: kill a few unused things in dev_priv drm/i915: extract ironlake_fdi_pll_disable drm/fb-helper: don't clobber output routing in setup_crtcs drm/i915: move functions around drm/i915: disable rc6 on ilk when vt-d is enabled drm/i915: move i915_get_extra_insdone out of CONFIG_DEBUG_FS block drm/ips: move drps/ips/ilk related variables into dev_priv->ips drm/i915: add a tracepoint for gpu frequency changes drm/i915: align vlv forcewake with common lore drm/i915: differ error message between forcwake timeouts drm/i915: add crtc->enable/disable vfuncs insted of dpms drm/i915: rip out crtc prepare/commit indirection drm/i915: add direct encoder disable/enable infrastructure drm/i915/hdmi: convert to encoder->disable/enable drm/i915/tv: convert to encoder enable/disable drm/i915/lvds: convert to encoder disable/enable drm/i915/dp: convert to encoder disable/enable drm/i915/crt: convert to encoder disable/enable drm/i915/sdvo: convert to encoder disable/enable drm/i915/dvo: convert to encoder disable/enable drm/i915: convert dpms functions of dvo/sdvo/crt drm/i915: rip out encoder->disable/enable checks drm/i915: clean up encoder_prepare/commit drm/i915: copy&paste drm_crtc_helper_set_config drm/i915: call set_base directly drm/i915: inline intel_best_encoder drm/i915: copy&paste drm_crtc_helper_set_mode drm/i915: simplify intel_crtc_prepare_encoders drm/i915: rip out encoder->prepare/commit drm/i915: call crtc functions directly drm/i915: WARN when trying to enabled an unused crtc drm/i915: Add interfaces to read out encoder/connector hw state drm/i915/dp: implement get_hw_state drm/i915/hdmi: implement get_hw_state drm/i915/tv: implement get_hw_state drm/i915/lvds: implement get_hw_state drm/i915/crt: implement get_hw_state drm/i915/sdvo: implement get_hw_state drm/i915/dvo: implement get_hw_state drm/i915: read out the modeset hw state at load and resume time drm/i915: check connector hw/sw state drm/i915: rip out intel_crtc->dpms_mode drm/i915: rip out intel_dp->dpms_mode drm/i915: ensure the force pipe A quirk is actually followed drm/i915: introduce struct intel_set_config drm/i915: extract modeset config save/restore code drm/i915: extract intel_set_config_compute_mode_changes drm/i915: extract intel_set_config_update_output_state drm/i915: implement crtc helper semantics relied upon by the fb helper drm/i915: don't update the fb base if there is no fb drm/i915: convert pointless error checks in set_config to BUGs drm/i915: don't save all the encoder/crtc state in set_config drm/i915: stage modeset output changes drm/i915: push crtc->fb update into pipe_set_base drm/i915: remove crtc disabling special case drm/i915: move output commit and crtc disabling into set_mode drm/i915: extract adjusted mode computation drm/i915: use staged outuput config in tv->mode_fixup drm/i915: use staged outuput config in lvds->mode_fixup drm/i915: compute masks of crtcs affected in set_mode drm/i915: implement new set_mode code flow drm/i915: push commit_output_state past crtc disabling drm/i915: s/intel_encoder_disable/intel_encoder_noop drm/i915: WARN if the pipe won't turn off drm/i915: switch the load detect code to the staged modeset config drm/i915: push commit_output_state past the crtc/encoder preparing drm/i915: disable all crtcs at suspend time drm/i915: no longer call drm_helper_resume_force_mode drm/i915: add tons of modeset state checks drm/i915: improve modeset state checking after dpms calls Merge the modeset-rework, basic conversion into drm-intel-next drm/fb helper: don't call drm_helper_connector_dpms directly drm/i915: correctly update crtc->x/y in set_base drm/i915: fix OOPS in lid_notify drm/i915: rip out early dp port write for gm45/ilk drm/i915: add encoder->pre_enable/post_disable drm/i915: clean up the cpu edp pll special case drm/i915: robustify edp_pll_on/off drm/i915: rip out dp port enabling cludges^Wchecks drm/i915: disable the cpu edp port after the cpu pipe drm/i915: rip out edp special case from dp_link_down drm/i915: rip out intel_disable_pch_ports drm/i915: don't disable fdi links harder in ilk_crtc_enable drm/i915: don't call dpms funcs after set_mode drm/i915: update dpms property in set_mode Merge tag 'v3.6-rc7' into drm-intel-next-queued Dave Airlie (14): drm/i915: implement dma buf begin_cpu_access (v2) drm/udl: call begin/end cpu access at more appropriate time Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-next Merge branch 'drm-doc' of git://linuxtv.org/pinchartl/fbdev into drm-next gma500: fix incorrect declaration. Merge branch 'master' of git://git.kernel.org/.../torvalds/linux into drm-next Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-next Merge branch 'drm-lcdc' of git://linuxtv.org/pinchartl/fbdev into drm-next drm: micro optimise cache flushing Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-next Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-next Merge branch 'drm-next-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-next Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next drm: Merge remote-tracking branch 'pfdo/drm-next' into linus David Herrmann (1): drm: make buffer management work without DRM_MASTER Dmitry Cherkasov (1): drm/radeon: add 2-level VM pagetables support v9 Dmitry Eremin-Solenikov (1): drm/nouveau: fix pm initialization order Emil Goode (1): gma500: Remove unused variable Eugeni Dodonov (1): drm/i915: prevent possible pin leak on error path Florian Zumbiehl (1): drm/savage: re-add busmaster enable, regression fix Forest Bond (2): gma500: Fix comment mispelling in cdv_intel_limits definition. gma500: psb_intel_crtc: Drop crtc_enable flag. Huacai Chen (2): drm: Handle io prot correctly for MIPS. drm: Define SAREA_MAX for Loongson (PageSize = 16KB). Jani Nikula (7): drm/i915: fix EDID memory leak in SDVO drm/ast: fix EDID memory leak drm: remove the raw_edid field from struct drm_display_info gma500: remove an unreachable return statement gma500: remove references to drm_display_info raw_edid field drm/i915: only enable sdvo hotplug irq if needed drm/i915: fix sdvo hotplug support check and activation Jerome Glisse (2): drm/edid: limit printk when facing bad edid drm/radeon: make sure ib bo is properly bound and up to date in vm space Keith Packard (1): drm/i915: Allow VGA on CRTC 2 Lars-Peter Clausen (1): DRM: Add DRM KMS/FB CMA helper Laurent Pinchart (4): Documentation: DocBook DRM framework documentation drm: gma500: Kill the GEM glue layer drm: Add NV24 and NV42 pixel formats drm: Renesas SH Mobile DRM driver Lauri Kasanen (2): drm/radeon: Mark all possible functions / structs as static drm/radeon: Remove unused functions Lekensteyn (1): i915: initialize CADL in opregion Luca Tettamanti (6): drm/radeon: refactor radeon_atif_call drm/radeon: implement radeon_atif_verify_interface drm/radeon: implement wrapper for GET_SYSTEM_PARAMS drm/radeon: implement handler for ACPI event ACPI video: allow events handlers to veto the keypress drm/radeon: block the keypress on ATIF events Maarten Lankhorst (3): drm/ast: remove unused validate_sequence drm/cirrus: Remove unused validate_sequence drm/mgag200: remove unused validate_sequence Marcin Slusarz (2): drm/nouveau: constify instances of nouveau_bitfield and nouveau_enum structs drm/nouveau: quiet some static-related sparse noise Marek Olšák (2): drm/radeon/kms: allow STRMOUT_BASE_UPDATE on RS780 and RS880 drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on Evergreen Mark Brown (1): drm/i2c/ch7006: Convert to dev_pm_ops Martin Peres (9): drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table drm/nouveau/therm: rework thermal table parsing drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices drm/nouveau/bios: parse the pwm divisor from the perf table drm/nouveau/therm: move thermal-related functions to the therm subdev drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster drm/nouveau/therm: calculate the pwm divisor on nv50+ drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules drm/nouveau/therm: add support for fan-control modes Michel Dänzer (1): drm/radeon: Fix scratch register leak in IB test. Paulo Zanoni (18): drm/i915: move common code to intel_dp_set_link_train drm/i915: add port field to struct intel_dp and use it drm/i915: fix pipe DDI mode select drm/i915: set the DDI sync polarity bits drm/i915: correctly set the DDI_FUNC_CTL bpc field drm/i915: completely reset the value of DDI_FUNC_CTL drm/i915: reindent Haswell register definitions drm/i915: add parentheses around PIXCLK_GATE definitions drm/i915: use the correct encoder type when comparing drm/i915: try harder to find WR PLL clock settings drm/i915: add gen7_render_ring_flush drm/i915: add workarounds directly to gen6_render_ring_flush drm/i915: add workarounds to gen7_render_ring_flush drm/i915: extract ironlake_set_pipeconf form ironlake_crtc_mode_set drm/i915: simplify setting DSPCNTR inside ironlake_crtc_mode_set drm/i915: extract compute_clocks from ironlake_crtc_mode_set drm/i915: BUG() on unexpected HDMI register drm/i915: make sure we write all the DIP data bytes Peter Senna Tschudin (1): drivers/gpu/drm/ttm/ttm_page_alloc_dma.c: Remove useless kfree Rob Clark (3): drm: refcnt drm_framebuffer (v4.1) drm: support for rotated scanout drm: change ioctl permissions Robert P. J. Day (1): drm: Remove unnecessary test for ARM. Russell King - ARM Linux (1): drm: consistently name interlaced modes Sachin Kamat (7): drm/usb: select USB_SUPPORT in Kconfig drm: Add missing static storage class specifier in drm_irq.c file drm: Add misssing static storage class specifier in drm_fb_helper.c file drm/udl: Use NULL instead of 0 for pointers drm/udl: Make udl_enc_destroy() static drm/udl: Make udl_crtc_init() static drm/udl: Add missing static storage class specifiers in udl_fb.c Sascha Hauer (1): DRM: Add DRM GEM CMA helper Sedat Dilek (2): drm/i915: Remove __GFP_NO_KSWAPD drm: udl: usb: Fix recursive Kconfig dependency Shirish S (1): drm: edid: add support for E-DDC Shobhit Kumar (1): drm/i915: Move DP structs to shared location Steven Fuerst (3): Rename i2f() to int2float(), and make it global so one copy can be removed. Replace int2float() with an optimized version. Annotate int2float() as being a pure function. Tejun Heo (1): i915: use alloc_ordered_workqueue() instead of explicit UNBOUND w/ max_active = 1 Thomas Richter (1): drm/i915: Support for ns2501-DVO Ville Syrjälä (3): drm: edid: Add some bounds checking drm: edid: Add bounds checking to HDMI VSDB parsing drm: edid: Refactor HDMI VSDB detection Wang Xingchao (5): drm/i915: HSW audio registers definition drm/i915: write eld info for HDMI audio drm/i915: ironlake_write_eld code cleanup drm/i915: Haswell HDMI audio initialization drm/i915: HDMI - Clear Audio Enable bit for Hot Plug unconditionally Wei Yongjun (1): vmwgfx: remove useless set memory to zero use memset() Xu, Anhua (2): drm/i915: fix wrong order of parameters in port checking functions drm/i915: fix reassignment of variable "intel_dp->DP" Zhao Yakui (4): gma500: Fix incorrect SR issue when disabling CRTC already in disabled state gma500: Program the DPLL lane based on the selected digitial port gma500/cdv: Add eDP support gma500: Disable the clock gating of display controller to make DP/eDP work well Documentation/DocBook/drm.tmpl | 2835 +++++++++--- drivers/acpi/video.c | 8 +- drivers/char/agp/intel-gtt.c | 62 +- drivers/gpu/drm/Kconfig | 19 +- drivers/gpu/drm/Makefile | 3 + drivers/gpu/drm/ast/ast_drv.h | 1 - drivers/gpu/drm/ast/ast_mode.c | 2 +- drivers/gpu/drm/cirrus/cirrus_drv.h | 1 - drivers/gpu/drm/drm_cache.c | 28 +- drivers/gpu/drm/drm_crtc.c | 139 +- drivers/gpu/drm/drm_drv.c | 22 +- drivers/gpu/drm/drm_edid.c | 208 +- drivers/gpu/drm/drm_edid_load.c | 29 +- drivers/gpu/drm/drm_edid_modes.h | 42 +- drivers/gpu/drm/drm_fb_cma_helper.c | 406 ++ drivers/gpu/drm/drm_fb_helper.c | 10 +- drivers/gpu/drm/drm_gem_cma_helper.c | 251 ++ drivers/gpu/drm/drm_irq.c | 2 +- drivers/gpu/drm/drm_vm.c | 11 +- drivers/gpu/drm/exynos/exynos_drm_connector.c | 4 +- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 4 +- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 13 - drivers/gpu/drm/gma500/Makefile | 5 +- drivers/gpu/drm/gma500/backlight.c | 45 + drivers/gpu/drm/gma500/cdv_device.c | 72 +- drivers/gpu/drm/gma500/cdv_intel_display.c | 236 +- drivers/gpu/drm/gma500/cdv_intel_dp.c | 1950 +++++++++ drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 6 +- drivers/gpu/drm/gma500/cdv_intel_lvds.c | 12 +- drivers/gpu/drm/gma500/framebuffer.c | 7 + drivers/gpu/drm/gma500/gem.c | 9 +- drivers/gpu/drm/gma500/gem_glue.c | 90 - drivers/gpu/drm/gma500/gem_glue.h | 2 - drivers/gpu/drm/gma500/intel_bios.c | 101 + drivers/gpu/drm/gma500/intel_bios.h | 46 + drivers/gpu/drm/gma500/mdfld_dsi_output.c | 13 +- drivers/gpu/drm/gma500/mid_bios.c | 8 +- drivers/gpu/drm/gma500/oaktrail_hdmi.c | 1 - drivers/gpu/drm/gma500/opregion.c | 3 +- drivers/gpu/drm/gma500/psb_device.c | 1 + drivers/gpu/drm/gma500/psb_drv.h | 20 +- drivers/gpu/drm/gma500/psb_intel_drv.h | 28 +- drivers/gpu/drm/gma500/psb_intel_lvds.c | 13 +- drivers/gpu/drm/gma500/psb_intel_reg.h | 197 +- drivers/gpu/drm/gma500/psb_intel_sdvo.c | 4 - drivers/gpu/drm/i2c/ch7006_drv.c | 16 +- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/dvo.h | 16 +- drivers/gpu/drm/i915/dvo_ch7017.c | 21 +- drivers/gpu/drm/i915/dvo_ch7xxx.c | 17 +- drivers/gpu/drm/i915/dvo_ivch.c | 23 +- drivers/gpu/drm/i915/dvo_ns2501.c | 588 +++ drivers/gpu/drm/i915/dvo_sil164.c | 20 +- drivers/gpu/drm/i915/dvo_tfp410.c | 18 +- drivers/gpu/drm/i915/i915_debugfs.c | 251 +- drivers/gpu/drm/i915/i915_dma.c | 73 +- drivers/gpu/drm/i915/i915_drv.c | 61 +- drivers/gpu/drm/i915/i915_drv.h | 239 +- drivers/gpu/drm/i915/i915_gem.c | 1548 ++++--- drivers/gpu/drm/i915/i915_gem_context.c | 65 +- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 174 +- drivers/gpu/drm/i915/i915_gem_evict.c | 44 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 391 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 144 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 16 +- drivers/gpu/drm/i915/i915_irq.c | 194 +- drivers/gpu/drm/i915/i915_reg.h | 328 +- drivers/gpu/drm/i915/i915_sysfs.c | 220 +- drivers/gpu/drm/i915/i915_trace.h | 25 +- drivers/gpu/drm/i915/intel_crt.c | 165 +- drivers/gpu/drm/i915/intel_ddi.c | 144 +- drivers/gpu/drm/i915/intel_display.c | 2173 ++++++--- drivers/gpu/drm/i915/intel_dp.c | 401 +- drivers/gpu/drm/i915/intel_drv.h | 147 +- drivers/gpu/drm/i915/intel_dvo.c | 115 +- drivers/gpu/drm/i915/intel_hdmi.c | 221 +- drivers/gpu/drm/i915/intel_lvds.c | 99 +- drivers/gpu/drm/i915/intel_modes.c | 1 - drivers/gpu/drm/i915/intel_opregion.c | 23 +- drivers/gpu/drm/i915/intel_overlay.c | 60 +- drivers/gpu/drm/i915/intel_pm.c | 420 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 152 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 20 +- drivers/gpu/drm/i915/intel_sdvo.c | 210 +- drivers/gpu/drm/i915/intel_tv.c | 70 +- drivers/gpu/drm/mgag200/mgag200_drv.h | 1 - drivers/gpu/drm/mgag200/mgag200_mode.c | 1 - drivers/gpu/drm/nouveau/Kconfig | 36 +- drivers/gpu/drm/nouveau/Makefile | 225 +- drivers/gpu/drm/nouveau/core/core/client.c | 103 + drivers/gpu/drm/nouveau/core/core/engctx.c | 236 + drivers/gpu/drm/nouveau/core/core/engine.c | 55 + .../nouveau/{nouveau_util.c => core/core/enum.c} | 47 +- drivers/gpu/drm/nouveau/core/core/gpuobj.c | 318 ++ drivers/gpu/drm/nouveau/core/core/handle.c | 223 + .../drm/nouveau/{nouveau_mm.c => core/core/mm.c} | 174 +- drivers/gpu/drm/nouveau/core/core/namedb.c | 203 + drivers/gpu/drm/nouveau/core/core/object.c | 468 ++ drivers/gpu/drm/nouveau/core/core/option.c | 131 + drivers/gpu/drm/nouveau/core/core/parent.c | 139 + drivers/gpu/drm/nouveau/core/core/printk.c | 74 + drivers/gpu/drm/nouveau/core/core/ramht.c | 109 + drivers/gpu/drm/nouveau/core/core/subdev.c | 115 + drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c | 175 + .../engine/copy/fuc/nva3.fuc} | 0 .../engine/copy/fuc/nva3.fuc.h} | 4 +- .../engine/copy/fuc/nvc0.fuc.h} | 4 +- drivers/gpu/drm/nouveau/core/engine/copy/nva3.c | 222 + drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c | 265 ++ drivers/gpu/drm/nouveau/core/engine/copy/nve0.c | 156 + .../engine/crypt/fuc/nv98.fuc} | 2 +- .../engine/crypt/fuc/nv98.fuc.h} | 4 +- drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c | 217 + drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c | 208 + drivers/gpu/drm/nouveau/core/engine/disp/nv04.c | 90 + drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | 125 + drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | 118 + drivers/gpu/drm/nouveau/core/engine/disp/vga.c | 215 + drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c | 87 + drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c | 185 + drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | 173 + drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c | 99 + drivers/gpu/drm/nouveau/core/engine/fifo/base.c | 181 + drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 630 +++ drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h | 178 + drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | 171 + drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | 208 + drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 349 ++ drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 502 +++ drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h | 36 + drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 420 ++ drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 647 +++ drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 628 +++ .../{nouveau_grctx.h => core/engine/graph/ctx.h} | 26 +- .../{nv40_grctx.c => core/engine/graph/ctxnv40.c} | 133 +- .../{nv50_grctx.c => core/engine/graph/ctxnv50.c} | 561 ++- .../gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | 3039 +++++++++++++ .../gpu/drm/nouveau/core/engine/graph/ctxnve0.c | 2788 ++++++++++++ .../engine/graph/fuc/gpcnvc0.fuc} | 8 +- .../engine/graph/fuc/gpcnvc0.fuc.h} | 66 + .../drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc | 451 ++ .../nouveau/core/engine/graph/fuc/gpcnve0.fuc.h | 530 +++ .../engine/graph/fuc/hubnvc0.fuc} | 8 +- .../engine/graph/fuc/hubnvc0.fuc.h} | 89 + .../drm/nouveau/core/engine/graph/fuc/hubnve0.fuc | 780 ++++ .../nouveau/core/engine/graph/fuc/hubnve0.fuc.h | 857 ++++ .../engine/graph/fuc/nvc0.fuc} | 0 .../gpu/drm/nouveau/core/engine/graph/fuc/nve0.fuc | 400 ++ drivers/gpu/drm/nouveau/core/engine/graph/nv04.c | 1387 ++++++ drivers/gpu/drm/nouveau/core/engine/graph/nv10.c | 1314 ++++++ drivers/gpu/drm/nouveau/core/engine/graph/nv20.c | 381 ++ drivers/gpu/drm/nouveau/core/engine/graph/nv20.h | 31 + drivers/gpu/drm/nouveau/core/engine/graph/nv25.c | 167 + drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c | 134 + drivers/gpu/drm/nouveau/core/engine/graph/nv30.c | 238 + drivers/gpu/drm/nouveau/core/engine/graph/nv34.c | 168 + drivers/gpu/drm/nouveau/core/engine/graph/nv35.c | 166 + drivers/gpu/drm/nouveau/core/engine/graph/nv40.c | 495 +++ drivers/gpu/drm/nouveau/core/engine/graph/nv40.h | 21 + drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 888 ++++ drivers/gpu/drm/nouveau/core/engine/graph/nv50.h | 7 + drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 955 ++++ drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | 171 + drivers/gpu/drm/nouveau/core/engine/graph/nve0.c | 576 +++ drivers/gpu/drm/nouveau/core/engine/graph/regs.h | 269 ++ drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c | 308 ++ drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c | 144 + drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c | 240 + drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c | 104 + drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c | 175 + .../gpu/drm/nouveau/core/engine/software/nv04.c | 147 + .../gpu/drm/nouveau/core/engine/software/nv10.c | 129 + .../gpu/drm/nouveau/core/engine/software/nv50.c | 199 + .../gpu/drm/nouveau/core/engine/software/nvc0.c | 181 + drivers/gpu/drm/nouveau/core/engine/vp/nv84.c | 175 + drivers/gpu/drm/nouveau/core/include/core/class.h | 118 + drivers/gpu/drm/nouveau/core/include/core/client.h | 42 + drivers/gpu/drm/nouveau/core/include/core/debug.h | 13 + drivers/gpu/drm/nouveau/core/include/core/device.h | 136 + drivers/gpu/drm/nouveau/core/include/core/engctx.h | 51 + drivers/gpu/drm/nouveau/core/include/core/engine.h | 57 + drivers/gpu/drm/nouveau/core/include/core/enum.h | 23 + drivers/gpu/drm/nouveau/core/include/core/gpuobj.h | 71 + drivers/gpu/drm/nouveau/core/include/core/handle.h | 31 + drivers/gpu/drm/nouveau/core/include/core/math.h | 16 + drivers/gpu/drm/nouveau/core/include/core/mm.h | 33 + drivers/gpu/drm/nouveau/core/include/core/namedb.h | 56 + drivers/gpu/drm/nouveau/core/include/core/object.h | 188 + drivers/gpu/drm/nouveau/core/include/core/option.h | 11 + drivers/gpu/drm/nouveau/core/include/core/parent.h | 64 + drivers/gpu/drm/nouveau/core/include/core/printk.h | 39 + drivers/gpu/drm/nouveau/core/include/core/ramht.h | 23 + drivers/gpu/drm/nouveau/core/include/core/subdev.h | 118 + drivers/gpu/drm/nouveau/core/include/engine/bsp.h | 45 + drivers/gpu/drm/nouveau/core/include/engine/copy.h | 49 + .../gpu/drm/nouveau/core/include/engine/crypt.h | 46 + drivers/gpu/drm/nouveau/core/include/engine/disp.h | 44 + .../gpu/drm/nouveau/core/include/engine/dmaobj.h | 57 + drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 111 + .../gpu/drm/nouveau/core/include/engine/graph.h | 72 + drivers/gpu/drm/nouveau/core/include/engine/mpeg.h | 61 + drivers/gpu/drm/nouveau/core/include/engine/ppp.h | 45 + .../gpu/drm/nouveau/core/include/engine/software.h | 60 + drivers/gpu/drm/nouveau/core/include/engine/vp.h | 45 + drivers/gpu/drm/nouveau/core/include/subdev/bar.h | 55 + drivers/gpu/drm/nouveau/core/include/subdev/bios.h | 34 + .../gpu/drm/nouveau/core/include/subdev/bios/bit.h | 13 + .../gpu/drm/nouveau/core/include/subdev/bios/bmp.h | 39 + .../drm/nouveau/core/include/subdev/bios/conn.h | 27 + .../gpu/drm/nouveau/core/include/subdev/bios/dcb.h | 90 + .../gpu/drm/nouveau/core/include/subdev/bios/dp.h | 8 + .../drm/nouveau/core/include/subdev/bios/extdev.h | 30 + .../drm/nouveau/core/include/subdev/bios/gpio.h | 33 + .../gpu/drm/nouveau/core/include/subdev/bios/i2c.h | 25 + .../drm/nouveau/core/include/subdev/bios/init.h | 21 + .../gpu/drm/nouveau/core/include/subdev/bios/mxm.h | 9 + .../drm/nouveau/core/include/subdev/bios/perf.h | 14 + .../gpu/drm/nouveau/core/include/subdev/bios/pll.h | 77 + .../drm/nouveau/core/include/subdev/bios/therm.h | 46 + .../gpu/drm/nouveau/core/include/subdev/clock.h | 59 + .../gpu/drm/nouveau/core/include/subdev/device.h | 24 + .../gpu/drm/nouveau/core/include/subdev/devinit.h | 40 + drivers/gpu/drm/nouveau/core/include/subdev/fb.h | 134 + drivers/gpu/drm/nouveau/core/include/subdev/gpio.h | 64 + drivers/gpu/drm/nouveau/core/include/subdev/i2c.h | 60 + drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 34 + .../gpu/drm/nouveau/core/include/subdev/instmem.h | 73 + drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h | 33 + drivers/gpu/drm/nouveau/core/include/subdev/mc.h | 49 + drivers/gpu/drm/nouveau/core/include/subdev/mxm.h | 37 + .../gpu/drm/nouveau/core/include/subdev/therm.h | 58 + .../gpu/drm/nouveau/core/include/subdev/timer.h | 53 + drivers/gpu/drm/nouveau/core/include/subdev/vga.h | 30 + .../{nouveau_vm.h => core/include/subdev/vm.h} | 87 +- drivers/gpu/drm/nouveau/core/os.h | 47 + drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 135 + drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c | 263 ++ drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 215 + drivers/gpu/drm/nouveau/core/subdev/bios/base.c | 479 ++ drivers/gpu/drm/nouveau/core/subdev/bios/bit.c | 52 + drivers/gpu/drm/nouveau/core/subdev/bios/conn.c | 56 + drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c | 135 + drivers/gpu/drm/nouveau/core/subdev/bios/dp.c | 76 + drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c | 100 + drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c | 121 + drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c | 129 + drivers/gpu/drm/nouveau/core/subdev/bios/init.c | 2120 +++++++++ drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c | 135 + drivers/gpu/drm/nouveau/core/subdev/bios/perf.c | 75 + drivers/gpu/drm/nouveau/core/subdev/bios/pll.c | 417 ++ drivers/gpu/drm/nouveau/core/subdev/bios/therm.c | 177 + drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c | 359 ++ .../{nouveau_ramht.h => core/subdev/clock/nv40.c} | 56 +- drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c | 105 + drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | 95 + drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c | 94 + drivers/gpu/drm/nouveau/core/subdev/clock/pll.h | 9 + .../gpu/drm/nouveau/core/subdev/clock/pllnv04.c | 242 + .../{nv50_calc.c => core/subdev/clock/pllnva3.c} | 69 +- drivers/gpu/drm/nouveau/core/subdev/device/base.c | 472 ++ drivers/gpu/drm/nouveau/core/subdev/device/nv04.c | 86 + drivers/gpu/drm/nouveau/core/subdev/device/nv10.c | 195 + drivers/gpu/drm/nouveau/core/subdev/device/nv20.c | 126 + drivers/gpu/drm/nouveau/core/subdev/device/nv30.c | 147 + drivers/gpu/drm/nouveau/core/subdev/device/nv40.c | 375 ++ drivers/gpu/drm/nouveau/core/subdev/device/nv50.c | 410 ++ drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c | 285 ++ drivers/gpu/drm/nouveau/core/subdev/device/nve0.c | 109 + .../{nv98_ppp.c => core/subdev/devinit/base.c} | 69 +- .../gpu/drm/nouveau/core/subdev/devinit/fbmem.h | 98 + drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c | 189 + drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c | 159 + drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c | 124 + .../{nouveau_i2c.h => core/subdev/devinit/nv1a.c} | 65 +- drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c | 96 + drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c | 87 + drivers/gpu/drm/nouveau/core/subdev/fb/base.c | 130 + drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c | 130 + drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c | 120 + drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c | 136 + drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c | 148 + drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c | 178 + drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c | 498 +++ drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 245 ++ drivers/gpu/drm/nouveau/core/subdev/gpio/base.c | 271 ++ drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c | 169 + drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c | 194 + drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c | 104 + drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c | 212 + drivers/gpu/drm/nouveau/core/subdev/i2c/base.c | 407 ++ drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c | 230 + drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c | 123 + drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c | 123 + drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | 135 + drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c | 198 + drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h | 39 + drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c | 138 + drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c | 172 + drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c | 93 + drivers/gpu/drm/nouveau/core/subdev/mc/base.c | 49 + drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c | 83 + drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c | 74 + drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c | 80 + drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c | 73 + drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | 75 + drivers/gpu/drm/nouveau/core/subdev/mxm/base.c | 290 ++ drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c | 193 + drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h | 22 + drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c | 233 + drivers/gpu/drm/nouveau/core/subdev/therm/base.c | 144 + drivers/gpu/drm/nouveau/core/subdev/therm/fan.c | 234 + drivers/gpu/drm/nouveau/core/subdev/therm/ic.c | 116 + drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c | 163 + drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c | 157 + drivers/gpu/drm/nouveau/core/subdev/therm/priv.h | 73 + drivers/gpu/drm/nouveau/core/subdev/therm/temp.c | 81 + drivers/gpu/drm/nouveau/core/subdev/timer/base.c | 87 + drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 249 ++ .../{nouveau_vm.c => core/subdev/vm/base.c} | 163 +- drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c | 151 + drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h | 19 + drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c | 158 + drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c | 248 ++ .../nouveau/{nv50_vm.c => core/subdev/vm/nv50.c} | 118 +- .../nouveau/{nvc0_vm.c => core/subdev/vm/nvc0.c} | 123 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 426 +- drivers/gpu/drm/nouveau/nouveau_abi16.h | 32 + drivers/gpu/drm/nouveau/nouveau_acpi.c | 26 +- drivers/gpu/drm/nouveau/nouveau_acpi.h | 22 + drivers/gpu/drm/nouveau/nouveau_agp.c | 152 + drivers/gpu/drm/nouveau/nouveau_agp.h | 10 + drivers/gpu/drm/nouveau/nouveau_backlight.c | 94 +- drivers/gpu/drm/nouveau/nouveau_bios.c | 4614 +------------------- drivers/gpu/drm/nouveau/nouveau_bios.h | 178 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 439 +- drivers/gpu/drm/nouveau/nouveau_bo.h | 99 + drivers/gpu/drm/nouveau/nouveau_calc.c | 234 +- drivers/gpu/drm/nouveau/nouveau_chan.c | 400 ++ drivers/gpu/drm/nouveau/nouveau_chan.h | 47 + drivers/gpu/drm/nouveau/nouveau_channel.c | 396 -- drivers/gpu/drm/nouveau/nouveau_connector.c | 219 +- drivers/gpu/drm/nouveau/nouveau_connector.h | 5 +- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 196 - drivers/gpu/drm/nouveau/nouveau_display.c | 259 +- drivers/gpu/drm/nouveau/nouveau_display.h | 94 + drivers/gpu/drm/nouveau/nouveau_dma.c | 55 +- drivers/gpu/drm/nouveau/nouveau_dma.h | 51 +- drivers/gpu/drm/nouveau/nouveau_dp.c | 280 +- drivers/gpu/drm/nouveau/nouveau_drm.c | 693 +++ drivers/gpu/drm/nouveau/nouveau_drm.h | 144 + drivers/gpu/drm/nouveau/nouveau_drv.c | 512 --- drivers/gpu/drm/nouveau/nouveau_drv.h | 1655 ------- drivers/gpu/drm/nouveau/nouveau_encoder.h | 21 +- drivers/gpu/drm/nouveau/nouveau_fb.h | 47 - drivers/gpu/drm/nouveau/nouveau_fbcon.c | 226 +- drivers/gpu/drm/nouveau/nouveau_fbcon.h | 3 +- drivers/gpu/drm/nouveau/nouveau_fence.c | 27 +- drivers/gpu/drm/nouveau/nouveau_fence.h | 41 +- drivers/gpu/drm/nouveau/nouveau_fifo.h | 32 - drivers/gpu/drm/nouveau/nouveau_gem.c | 178 +- drivers/gpu/drm/nouveau/nouveau_gem.h | 43 + drivers/gpu/drm/nouveau/nouveau_gpio.c | 400 -- drivers/gpu/drm/nouveau/nouveau_gpio.h | 71 - drivers/gpu/drm/nouveau/nouveau_gpuobj.c | 807 ---- drivers/gpu/drm/nouveau/nouveau_hdmi.c | 41 +- drivers/gpu/drm/nouveau/nouveau_hw.c | 435 +- drivers/gpu/drm/nouveau/nouveau_hw.h | 182 +- drivers/gpu/drm/nouveau/nouveau_i2c.c | 394 -- drivers/gpu/drm/nouveau/nouveau_ioc32.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ioctl.h | 6 + drivers/gpu/drm/nouveau/nouveau_irq.c | 132 +- drivers/gpu/drm/nouveau/nouveau_irq.h | 11 + drivers/gpu/drm/nouveau/nouveau_mem.c | 739 +--- drivers/gpu/drm/nouveau/nouveau_mm.h | 67 - drivers/gpu/drm/nouveau/nouveau_mxm.c | 723 --- drivers/gpu/drm/nouveau/nouveau_notifier.c | 162 - drivers/gpu/drm/nouveau/nouveau_perf.c | 65 +- drivers/gpu/drm/nouveau/nouveau_pm.c | 462 +- drivers/gpu/drm/nouveau/nouveau_pm.h | 186 +- drivers/gpu/drm/nouveau/nouveau_prime.c | 10 +- drivers/gpu/drm/nouveau/nouveau_ramht.c | 309 -- drivers/gpu/drm/nouveau/nouveau_sgdma.c | 377 +- drivers/gpu/drm/nouveau/nouveau_software.h | 56 - drivers/gpu/drm/nouveau/nouveau_state.c | 1304 ------ drivers/gpu/drm/nouveau/nouveau_temp.c | 331 -- drivers/gpu/drm/nouveau/nouveau_ttm.c | 354 +- drivers/gpu/drm/nouveau/nouveau_ttm.h | 25 + drivers/gpu/drm/nouveau/nouveau_util.h | 49 - drivers/gpu/drm/nouveau/nouveau_vga.c | 99 + drivers/gpu/drm/nouveau/nouveau_vga.h | 8 + drivers/gpu/drm/nouveau/nouveau_volt.c | 53 +- drivers/gpu/drm/nouveau/nv04_crtc.c | 142 +- drivers/gpu/drm/nouveau/nv04_cursor.c | 8 +- drivers/gpu/drm/nouveau/nv04_dac.c | 148 +- drivers/gpu/drm/nouveau/nv04_dfp.c | 132 +- drivers/gpu/drm/nouveau/nv04_display.c | 129 +- drivers/gpu/drm/nouveau/nv04_display.h | 184 + drivers/gpu/drm/nouveau/nv04_fb.c | 54 - drivers/gpu/drm/nouveau/nv04_fbcon.c | 70 +- drivers/gpu/drm/nouveau/nv04_fence.c | 67 +- drivers/gpu/drm/nouveau/nv04_fifo.c | 505 --- drivers/gpu/drm/nouveau/nv04_graph.c | 1325 ------ drivers/gpu/drm/nouveau/nv04_instmem.c | 192 - drivers/gpu/drm/nouveau/nv04_mc.c | 23 - drivers/gpu/drm/nouveau/nv04_pm.c | 37 +- drivers/gpu/drm/nouveau/nv04_software.c | 147 - drivers/gpu/drm/nouveau/nv04_timer.c | 83 - drivers/gpu/drm/nouveau/nv04_tv.c | 36 +- drivers/gpu/drm/nouveau/nv10_fb.c | 103 - drivers/gpu/drm/nouveau/nv10_fence.c | 103 +- drivers/gpu/drm/nouveau/nv10_fifo.c | 137 - drivers/gpu/drm/nouveau/nv10_gpio.c | 123 - drivers/gpu/drm/nouveau/nv10_graph.c | 1188 ----- drivers/gpu/drm/nouveau/nv17_fifo.c | 176 - drivers/gpu/drm/nouveau/nv17_tv.c | 98 +- drivers/gpu/drm/nouveau/nv17_tv.h | 6 +- drivers/gpu/drm/nouveau/nv17_tv_modes.c | 5 +- drivers/gpu/drm/nouveau/nv20_fb.c | 147 - drivers/gpu/drm/nouveau/nv20_graph.c | 835 ---- drivers/gpu/drm/nouveau/nv30_fb.c | 115 - drivers/gpu/drm/nouveau/nv31_mpeg.c | 346 -- drivers/gpu/drm/nouveau/nv40_fb.c | 162 - drivers/gpu/drm/nouveau/nv40_fifo.c | 209 - drivers/gpu/drm/nouveau/nv40_graph.c | 466 -- drivers/gpu/drm/nouveau/nv40_mc.c | 27 - drivers/gpu/drm/nouveau/nv40_pm.c | 182 +- drivers/gpu/drm/nouveau/nv50_crtc.c | 118 +- drivers/gpu/drm/nouveau/nv50_cursor.c | 32 +- drivers/gpu/drm/nouveau/nv50_dac.c | 89 +- drivers/gpu/drm/nouveau/nv50_display.c | 551 +-- drivers/gpu/drm/nouveau/nv50_display.h | 31 +- drivers/gpu/drm/nouveau/nv50_evo.c | 268 +- drivers/gpu/drm/nouveau/nv50_fb.c | 295 -- drivers/gpu/drm/nouveau/nv50_fbcon.c | 36 +- drivers/gpu/drm/nouveau/nv50_fence.c | 127 + drivers/gpu/drm/nouveau/nv50_fifo.c | 293 -- drivers/gpu/drm/nouveau/nv50_gpio.c | 155 - drivers/gpu/drm/nouveau/nv50_graph.c | 867 ---- drivers/gpu/drm/nouveau/nv50_instmem.c | 427 -- drivers/gpu/drm/nouveau/nv50_mc.c | 39 - drivers/gpu/drm/nouveau/nv50_mpeg.c | 241 - drivers/gpu/drm/nouveau/nv50_pm.c | 247 +- drivers/gpu/drm/nouveau/nv50_software.c | 203 - drivers/gpu/drm/nouveau/nv50_sor.c | 133 +- drivers/gpu/drm/nouveau/nv50_vram.c | 237 - drivers/gpu/drm/nouveau/nv84_bsp.c | 83 - drivers/gpu/drm/nouveau/nv84_crypt.c | 205 - drivers/gpu/drm/nouveau/nv84_fence.c | 127 +- drivers/gpu/drm/nouveau/nv84_fifo.c | 249 -- drivers/gpu/drm/nouveau/nv84_vp.c | 83 - drivers/gpu/drm/nouveau/nv98_crypt.c | 216 - drivers/gpu/drm/nouveau/nva3_copy.c | 203 - drivers/gpu/drm/nouveau/nva3_pm.c | 274 +- drivers/gpu/drm/nouveau/nvc0_copy.c | 243 -- drivers/gpu/drm/nouveau/nvc0_fb.c | 134 - drivers/gpu/drm/nouveau/nvc0_fbcon.c | 31 +- drivers/gpu/drm/nouveau/nvc0_fence.c | 150 +- drivers/gpu/drm/nouveau/nvc0_fifo.c | 477 -- drivers/gpu/drm/nouveau/nvc0_graph.c | 897 ---- drivers/gpu/drm/nouveau/nvc0_graph.h | 97 - drivers/gpu/drm/nouveau/nvc0_grctx.c | 2878 ------------ drivers/gpu/drm/nouveau/nvc0_instmem.c | 223 - drivers/gpu/drm/nouveau/nvc0_pm.c | 178 +- drivers/gpu/drm/nouveau/nvc0_software.c | 153 - drivers/gpu/drm/nouveau/nvc0_vram.c | 160 - drivers/gpu/drm/nouveau/nvd0_display.c | 504 ++- drivers/gpu/drm/nouveau/nve0_fifo.c | 453 -- drivers/gpu/drm/nouveau/nve0_graph.c | 831 ---- drivers/gpu/drm/nouveau/nve0_graph.h | 89 - drivers/gpu/drm/nouveau/nve0_grctx.c | 2777 ------------ drivers/gpu/drm/radeon/atombios_crtc.c | 663 ++- drivers/gpu/drm/radeon/atombios_dp.c | 4 +- drivers/gpu/drm/radeon/atombios_encoders.c | 367 +- drivers/gpu/drm/radeon/evergreen.c | 282 +- drivers/gpu/drm/radeon/evergreen_cs.c | 61 +- drivers/gpu/drm/radeon/evergreen_reg.h | 2 + drivers/gpu/drm/radeon/evergreend.h | 7 + drivers/gpu/drm/radeon/ni.c | 134 +- drivers/gpu/drm/radeon/nid.h | 1 + drivers/gpu/drm/radeon/r100.c | 96 +- drivers/gpu/drm/radeon/r300.c | 4 +- drivers/gpu/drm/radeon/r520.c | 4 +- drivers/gpu/drm/radeon/r600.c | 37 +- drivers/gpu/drm/radeon/r600_blit.c | 115 +- drivers/gpu/drm/radeon/r600_blit_kms.c | 52 +- drivers/gpu/drm/radeon/r600_blit_shaders.h | 1 + drivers/gpu/drm/radeon/r600_cs.c | 5 +- drivers/gpu/drm/radeon/r600_hdmi.c | 2 +- drivers/gpu/drm/radeon/radeon.h | 192 +- drivers/gpu/drm/radeon/radeon_acpi.c | 607 ++- drivers/gpu/drm/radeon/radeon_acpi.h | 445 ++ drivers/gpu/drm/radeon/radeon_asic.c | 93 +- drivers/gpu/drm/radeon/radeon_asic.h | 28 +- drivers/gpu/drm/radeon/radeon_atombios.c | 15 +- drivers/gpu/drm/radeon/radeon_atpx_handler.c | 411 +- drivers/gpu/drm/radeon/radeon_combios.c | 9 - drivers/gpu/drm/radeon/radeon_connectors.c | 43 +- drivers/gpu/drm/radeon/radeon_cs.c | 83 +- drivers/gpu/drm/radeon/radeon_device.c | 11 +- drivers/gpu/drm/radeon/radeon_drv.c | 4 +- drivers/gpu/drm/radeon/radeon_encoders.c | 19 +- drivers/gpu/drm/radeon/radeon_fb.c | 16 - drivers/gpu/drm/radeon/radeon_fence.c | 2 +- drivers/gpu/drm/radeon/radeon_gart.c | 602 ++- drivers/gpu/drm/radeon/radeon_gem.c | 54 +- drivers/gpu/drm/radeon/radeon_ioc32.c | 2 +- drivers/gpu/drm/radeon/radeon_irq_kms.c | 43 +- drivers/gpu/drm/radeon/radeon_kms.c | 17 +- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 7 +- drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 65 +- drivers/gpu/drm/radeon/radeon_mode.h | 49 +- drivers/gpu/drm/radeon/radeon_object.c | 22 +- drivers/gpu/drm/radeon/radeon_object.h | 4 +- drivers/gpu/drm/radeon/radeon_pm.c | 104 +- drivers/gpu/drm/radeon/radeon_ring.c | 30 +- drivers/gpu/drm/radeon/radeon_sa.c | 20 +- drivers/gpu/drm/radeon/radeon_test.c | 2 +- drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- drivers/gpu/drm/radeon/rs400.c | 6 +- drivers/gpu/drm/radeon/rs600.c | 49 +- drivers/gpu/drm/radeon/rs690.c | 6 +- drivers/gpu/drm/radeon/rv515.c | 18 +- drivers/gpu/drm/radeon/rv770.c | 10 +- drivers/gpu/drm/radeon/si.c | 113 +- drivers/gpu/drm/radeon/sid.h | 15 + drivers/gpu/drm/savage/savage_bci.c | 2 + drivers/gpu/drm/shmobile/Kconfig | 10 + drivers/gpu/drm/shmobile/Makefile | 7 + drivers/gpu/drm/shmobile/shmob_drm_backlight.c | 90 + drivers/gpu/drm/shmobile/shmob_drm_backlight.h | 23 + drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 763 ++++ drivers/gpu/drm/shmobile/shmob_drm_crtc.h | 60 + drivers/gpu/drm/shmobile/shmob_drm_drv.c | 361 ++ drivers/gpu/drm/shmobile/shmob_drm_drv.h | 47 + drivers/gpu/drm/shmobile/shmob_drm_kms.c | 160 + drivers/gpu/drm/shmobile/shmob_drm_kms.h | 34 + drivers/gpu/drm/shmobile/shmob_drm_plane.c | 268 ++ drivers/gpu/drm/shmobile/shmob_drm_plane.h | 22 + drivers/gpu/drm/shmobile/shmob_drm_regs.h | 311 ++ drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 5 +- drivers/gpu/drm/ttm/ttm_tt.c | 16 +- drivers/gpu/drm/udl/udl_connector.c | 3 - drivers/gpu/drm/udl/udl_encoder.c | 2 +- drivers/gpu/drm/udl/udl_fb.c | 26 +- drivers/gpu/drm/udl/udl_gem.c | 7 - drivers/gpu/drm/udl/udl_main.c | 7 +- drivers/gpu/drm/udl/udl_modeset.c | 2 +- drivers/gpu/drm/udl/udl_transfer.c | 8 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 1 - drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 1 - drivers/staging/omapdrm/omap_connector.c | 5 +- drivers/staging/omapdrm/omap_fbdev.c | 4 +- include/drm/drmP.h | 1 + include/drm/drm_crtc.h | 24 +- include/drm/drm_fb_cma_helper.h | 27 + include/drm/drm_fourcc.h | 2 + include/drm/drm_gem_cma_helper.h | 44 + include/drm/drm_sarea.h | 2 + include/drm/i915_drm.h | 36 +- include/drm/intel-gtt.h | 10 +- include/linux/platform_data/shmob_drm.h | 99 + 562 files changed, 71126 insertions(+), 43374 deletions(-) create mode 100644 drivers/gpu/drm/drm_fb_cma_helper.c create mode 100644 drivers/gpu/drm/drm_gem_cma_helper.c create mode 100644 drivers/gpu/drm/gma500/cdv_intel_dp.c delete mode 100644 drivers/gpu/drm/gma500/gem_glue.c delete mode 100644 drivers/gpu/drm/gma500/gem_glue.h create mode 100644 drivers/gpu/drm/i915/dvo_ns2501.c create mode 100644 drivers/gpu/drm/nouveau/core/core/client.c create mode 100644 drivers/gpu/drm/nouveau/core/core/engctx.c create mode 100644 drivers/gpu/drm/nouveau/core/core/engine.c rename drivers/gpu/drm/nouveau/{nouveau_util.c => core/core/enum.c} (86%) create mode 100644 drivers/gpu/drm/nouveau/core/core/gpuobj.c create mode 100644 drivers/gpu/drm/nouveau/core/core/handle.c rename drivers/gpu/drm/nouveau/{nouveau_mm.c => core/core/mm.c} (53%) create mode 100644 drivers/gpu/drm/nouveau/core/core/namedb.c create mode 100644 drivers/gpu/drm/nouveau/core/core/object.c create mode 100644 drivers/gpu/drm/nouveau/core/core/option.c create mode 100644 drivers/gpu/drm/nouveau/core/core/parent.c create mode 100644 drivers/gpu/drm/nouveau/core/core/printk.c create mode 100644 drivers/gpu/drm/nouveau/core/core/ramht.c create mode 100644 drivers/gpu/drm/nouveau/core/core/subdev.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c rename drivers/gpu/drm/nouveau/{nva3_copy.fuc => core/engine/copy/fuc/nva3.fuc} (100%) rename drivers/gpu/drm/nouveau/{nva3_copy.fuc.h => core/engine/copy/fuc/nva3.fuc.h} (99%) rename drivers/gpu/drm/nouveau/{nvc0_copy.fuc.h => core/engine/copy/fuc/nvc0.fuc.h} (99%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/copy/nva3.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/copy/nve0.c rename drivers/gpu/drm/nouveau/{nv98_crypt.fuc => core/engine/crypt/fuc/nv98.fuc} (99%) rename drivers/gpu/drm/nouveau/{nv98_crypt.fuc.h => core/engine/crypt/fuc/nv98.fuc.h} (99%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/vga.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/base.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c rename drivers/gpu/drm/nouveau/{nouveau_grctx.h => core/engine/graph/ctx.h} (84%) rename drivers/gpu/drm/nouveau/{nv40_grctx.c => core/engine/graph/ctxnv40.c} (85%) rename drivers/gpu/drm/nouveau/{nv50_grctx.c => core/engine/graph/ctxnv50.c} (91%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c rename drivers/gpu/drm/nouveau/{nvc0_grgpc.fuc => core/engine/graph/fuc/gpcnvc0.fuc} (98%) rename drivers/gpu/drm/nouveau/{nvc0_grgpc.fuc.h => core/engine/graph/fuc/gpcnvc0.fuc.h} (78%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h rename drivers/gpu/drm/nouveau/{nvc0_grhub.fuc => core/engine/graph/fuc/hubnvc0.fuc} (99%) rename drivers/gpu/drm/nouveau/{nvc0_grhub.fuc.h => core/engine/graph/fuc/hubnvc0.fuc.h} (81%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h rename drivers/gpu/drm/nouveau/{nvc0_graph.fuc => core/engine/graph/fuc/nvc0.fuc} (100%) create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/fuc/nve0.fuc create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv20.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv20.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv25.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv30.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv34.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv35.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv40.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nv50.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nve0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/regs.h create mode 100644 drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/software/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/software/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/software/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/software/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/engine/vp/nv84.c create mode 100644 drivers/gpu/drm/nouveau/core/include/core/class.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/client.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/debug.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/device.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/engctx.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/engine.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/enum.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/gpuobj.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/handle.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/math.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/mm.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/namedb.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/object.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/option.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/parent.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/printk.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/ramht.h create mode 100644 drivers/gpu/drm/nouveau/core/include/core/subdev.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/bsp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/copy.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/crypt.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/disp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/fifo.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/graph.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/mpeg.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/ppp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/software.h create mode 100644 drivers/gpu/drm/nouveau/core/include/engine/vp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bar.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/clock.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/device.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/devinit.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/fb.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/gpio.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/i2c.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/ibus.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/instmem.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/mc.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/mxm.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/therm.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/timer.h create mode 100644 drivers/gpu/drm/nouveau/core/include/subdev/vga.h rename drivers/gpu/drm/nouveau/{nouveau_vm.h => core/include/subdev/vm.h} (60%) create mode 100644 drivers/gpu/drm/nouveau/core/os.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bar/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/bit.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/conn.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/dp.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/init.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/perf.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/pll.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/bios/therm.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c rename drivers/gpu/drm/nouveau/{nouveau_ramht.h => core/subdev/clock/nv40.c} (55%) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/pll.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c rename drivers/gpu/drm/nouveau/{nv50_calc.c => core/subdev/clock/pllnva3.c} (52%) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv20.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv30.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/device/nve0.c rename drivers/gpu/drm/nouveau/{nv98_ppp.c => core/subdev/devinit/base.c} (52%) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c rename drivers/gpu/drm/nouveau/{nouveau_i2c.h => core/subdev/devinit/nv1a.c} (52%) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/gpio/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/i2c/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/instmem/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mxm/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/fan.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/ic.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/priv.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/therm/temp.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/timer/base.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c rename drivers/gpu/drm/nouveau/{nouveau_vm.c => core/subdev/vm/base.c} (72%) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h create mode 100644 drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c create mode 100644 drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c rename drivers/gpu/drm/nouveau/{nv50_vm.c => core/subdev/vm/nv50.c} (59%) rename drivers/gpu/drm/nouveau/{nvc0_vm.c => core/subdev/vm/nvc0.c} (53%) create mode 100644 drivers/gpu/drm/nouveau/nouveau_acpi.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_agp.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_agp.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_chan.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_chan.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_channel.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_debugfs.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_display.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_drm.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_drm.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_drv.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_drv.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_fb.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_fifo.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_gem.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_gpio.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_gpio.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_gpuobj.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_i2c.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_ioctl.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_irq.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_mm.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_mxm.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_notifier.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_ramht.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_software.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_state.c delete mode 100644 drivers/gpu/drm/nouveau/nouveau_temp.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_ttm.h delete mode 100644 drivers/gpu/drm/nouveau/nouveau_util.h create mode 100644 drivers/gpu/drm/nouveau/nouveau_vga.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_vga.h create mode 100644 drivers/gpu/drm/nouveau/nv04_display.h delete mode 100644 drivers/gpu/drm/nouveau/nv04_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_instmem.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_mc.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_software.c delete mode 100644 drivers/gpu/drm/nouveau/nv04_timer.c delete mode 100644 drivers/gpu/drm/nouveau/nv10_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nv10_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv10_gpio.c delete mode 100644 drivers/gpu/drm/nouveau/nv10_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nv17_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv20_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nv20_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nv30_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nv31_mpeg.c delete mode 100644 drivers/gpu/drm/nouveau/nv40_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nv40_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv40_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nv40_mc.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_fb.c create mode 100644 drivers/gpu/drm/nouveau/nv50_fence.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_gpio.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_instmem.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_mc.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_mpeg.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_software.c delete mode 100644 drivers/gpu/drm/nouveau/nv50_vram.c delete mode 100644 drivers/gpu/drm/nouveau/nv84_bsp.c delete mode 100644 drivers/gpu/drm/nouveau/nv84_crypt.c delete mode 100644 drivers/gpu/drm/nouveau/nv84_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nv84_vp.c delete mode 100644 drivers/gpu/drm/nouveau/nv98_crypt.c delete mode 100644 drivers/gpu/drm/nouveau/nva3_copy.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_copy.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_fb.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_graph.h delete mode 100644 drivers/gpu/drm/nouveau/nvc0_grctx.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_instmem.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_software.c delete mode 100644 drivers/gpu/drm/nouveau/nvc0_vram.c delete mode 100644 drivers/gpu/drm/nouveau/nve0_fifo.c delete mode 100644 drivers/gpu/drm/nouveau/nve0_graph.c delete mode 100644 drivers/gpu/drm/nouveau/nve0_graph.h delete mode 100644 drivers/gpu/drm/nouveau/nve0_grctx.c create mode 100644 drivers/gpu/drm/radeon/radeon_acpi.h create mode 100644 drivers/gpu/drm/shmobile/Kconfig create mode 100644 drivers/gpu/drm/shmobile/Makefile create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_backlight.c create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_backlight.h create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_crtc.c create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_crtc.h create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_drv.c create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_drv.h create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_kms.c create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_kms.h create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_plane.c create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_plane.h create mode 100644 drivers/gpu/drm/shmobile/shmob_drm_regs.h create mode 100644 include/drm/drm_fb_cma_helper.h create mode 100644 include/drm/drm_gem_cma_helper.h create mode 100644 include/linux/platform_data/shmob_drm.h

4 4

Re: linux-next: Tree for Oct 5 (nouveau)
by Randy Dunlap 05 Oct '12

05 Oct '12

On 10/04/2012 09:54 PM, Stephen Rothwell wrote: > Hi all, > > Do not add stuff destined for v3.8 to your linux-next included branches > until after v3.7-rc1 is released. > > Changes since 201201004: > on x86_64, when CONFIG_AGP is not enabled: CC [M] drivers/gpu/drm/nouveau/nouveau_bo.o drivers/gpu/drm/nouveau/nouveau_bo.c: In function 'nouveau_ttm_tt_create': drivers/gpu/drm/nouveau/nouveau_bo.c:463:3: error: implicit declaration of function 'ttm_agp_tt_create' drivers/gpu/drm/nouveau/nouveau_bo.c:463:3: warning: return makes pointer from integer without a cast make[5]: *** [drivers/gpu/drm/nouveau/nouveau_bo.o] Error 1 -- ~Randy

1 0

[Bug 45061] New: Power consumption higher after resume, probably vgaswitcheroo/radeon related
by bugzilla-daemon＠bugzilla.kernel.org 05 Oct '12

05 Oct '12

https://bugzilla.kernel.org/show_bug.cgi?id=45061 Summary: Power consumption higher after resume, probably vgaswitcheroo/radeon related Product: Drivers Version: 2.5 Kernel Version: 3.2, 3.4, 3.5 Platform: All OS/Version: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) AssignedTo: drivers_video-dri(a)kernel-bugs.osdl.org ReportedBy: alexpigna.dev(a)gmail.com Regression: No Created an attachment (id=75941) --> (https://bugzilla.kernel.org/attachment.cgi?id=75941) lspci -vvv I have an hybrid graphics Sony VAIO laptop, with the usual intel integrated+radeon discrete cards. On startup I disable the radeon card using vgaswitcheroo. I noticed that the power consumption, as reported in /proc/acpi/battery/BAT1/state gets higher when I resume my laptop from suspend to RAM. I strongly suspect that this is related to a bug in vgaswitcheroo or the radeon driver, since the power used after resume is consistent with the power used when the discrete video card is not off. My guess is that the card is powered by default when the system comes up from suspend, while the kernel believes it's still powered off. Before resume I made sure the discrete card was off by using sudo bash -c "echo OFF > /sys/kernel/debug/vgaswitcheroo/switch" At resume, with high power consumption, the state is reported as expected: sudo cat /sys/kernel/debug/vgaswitcheroo/switch 0:IGD:+:Pwr:0000:00:02.0 1:DIS: :Off:0000:01:00.0 Still, if I run: sudo bash -c "echo ON > /sys/kernel/debug/vgaswitcheroo/switch" It takes a few seconds, and from dmesg I can see errors from the radeon driver. [ 9450.115590] radeon: switched on [ 9450.115618] radeon 0000:01:00.0: enabling device (0000 -> 0003) [ 9450.115634] radeon 0000:01:00.0: setting latency timer to 64 [ 9450.115644] radeon 0000:01:00.0: GPU softreset [ 9450.115649] radeon 0000:01:00.0: GRBM_STATUS=0xFFFFFFFF [ 9450.115654] radeon 0000:01:00.0: GRBM_STATUS_SE0=0xFFFFFFFF [ 9450.115660] radeon 0000:01:00.0: GRBM_STATUS_SE1=0xFFFFFFFF [ 9450.115665] radeon 0000:01:00.0: SRBM_STATUS=0xFFFFFFFF [ 9450.343133] radeon 0000:01:00.0: Wait for MC idle timedout ! [ 9450.343137] radeon 0000:01:00.0: GRBM_SOFT_RESET=0x00007F6B [ 9450.343245] radeon 0000:01:00.0: GRBM_STATUS=0xFFFFFFFF [ 9450.343250] radeon 0000:01:00.0: GRBM_STATUS_SE0=0xFFFFFFFF [ 9450.343255] radeon 0000:01:00.0: GRBM_STATUS_SE1=0xFFFFFFFF [ 9450.343260] radeon 0000:01:00.0: SRBM_STATUS=0xFFFFFFFF [ 9455.340458] [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [ 9455.340473] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing CDDC (len 62, WS 0, PS 0) @ 0xCDF8 [ 9455.340481] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing BB16 (len 1036, WS 4, PS 0) @ 0xBC13 [ 9455.340489] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing BAAC (len 76, WS 0, PS 8) @ 0xBAB4 [ 9455.568120] radeon 0000:01:00.0: Wait for MC idle timedout ! [ 9455.795784] radeon 0000:01:00.0: Wait for MC idle timedout ! [ 9455.820793] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 9455.821119] radeon 0000:01:00.0: WB enabled [ 9456.065584] [drm:r600_ring_test] *ERROR* radeon: ring test failed (scratch(0x8504)=0xFFFFFFFF) [ 9456.065591] [drm:evergreen_resume] *ERROR* evergreen startup failed on resume [ 9461.061054] [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [ 9461.061074] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing CDDC (len 62, WS 0, PS 0) @ 0xCDF8 [ 9466.058587] [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [ 9466.058604] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing CDDC (len 62, WS 0, PS 0) @ 0xCDF8 [ 9471.056127] [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [ 9471.056143] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing CDDC (len 62, WS 0, PS 0) @ 0xCDF8 [ 9476.053651] [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [ 9476.053668] [drm:atom_execute_table_locked] *ERROR* atombios stuck executing CDDC (len 62, WS 0, PS 0) @ 0xCDF8 Anyway, eventually the command finishes and I can run: sudo bash -c "echo OFF > /sys/kernel/debug/vgaswitcheroo/switch" No error now, and the power consumption goes down to the expected level. Details that may be useful: Linux version 3.2.0-26-generic (buildd@batsu) (gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5) ) #41-Ubuntu SMP Thu Jun 14 17:49:24 UTC 2012 /proc/cpuinfo (repeated 4 times) processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 42 model name : Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz stepping : 7 microcode : 0x14 cpu MHz : 800.000 cache size : 3072 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 2 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm ida arat epb xsaveopt pln pts dts tpr_shadow vnmi flexpriority ept vpid bogomips : 4988.75 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: /proc/modules: kvm_intel 137721 0 - Live 0x0000000000000000 kvm 415549 1 kvm_intel, Live 0x0000000000000000 parport_pc 32866 0 - Live 0x0000000000000000 ppdev 17113 0 - Live 0x0000000000000000 rfcomm 47604 14 - Live 0x0000000000000000 bnep 18281 2 - Live 0x0000000000000000 binfmt_misc 17540 1 - Live 0x0000000000000000 snd_hda_codec_hdmi 32474 1 - Live 0x0000000000000000 snd_hda_codec_realtek 223867 1 - Live 0x0000000000000000 arc4 12529 2 - Live 0x0000000000000000 uvcvideo 72627 0 - Live 0x0000000000000000 videodev 98259 1 uvcvideo, Live 0x0000000000000000 v4l2_compat_ioctl32 17128 1 videodev, Live 0x0000000000000000 psmouse 87692 0 - Live 0x0000000000000000 serio_raw 13211 0 - Live 0x0000000000000000 sony_laptop 45393 0 - Live 0x0000000000000000 mac_hid 13253 0 - Live 0x0000000000000000 btusb 18288 2 - Live 0x0000000000000000 bluetooth 180104 23 rfcomm,bnep,btusb, Live 0x0000000000000000 snd_hda_intel 33773 5 - Live 0x0000000000000000 snd_hda_codec 127706 3 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel, Live 0x0000000000000000 snd_hwdep 13668 1 snd_hda_codec, Live 0x0000000000000000 snd_pcm 97188 4 snd_hda_codec_hdmi,snd_hda_intel,snd_hda_codec, Live 0x0000000000000000 snd_seq_midi 13324 0 - Live 0x0000000000000000 snd_rawmidi 30748 1 snd_seq_midi, Live 0x0000000000000000 snd_seq_midi_event 14899 1 snd_seq_midi, Live 0x0000000000000000 snd_seq 61896 2 snd_seq_midi,snd_seq_midi_event, Live 0x0000000000000000 snd_timer 29990 2 snd_pcm,snd_seq, Live 0x0000000000000000 snd_seq_device 14540 3 snd_seq_midi,snd_rawmidi,snd_seq, Live 0x0000000000000000 i915 468737 3 - Live 0x0000000000000000 iwlwifi 332672 0 - Live 0x0000000000000000 video 19596 1 i915, Live 0x0000000000000000 mac80211 506816 1 iwlwifi, Live 0x0000000000000000 mei 41616 0 - Live 0x0000000000000000 (C) radeon 804372 0 - Live 0x0000000000000000 cfg80211 205544 2 iwlwifi,mac80211, Live 0x0000000000000000 ttm 76949 1 radeon, Live 0x0000000000000000 rts_pstor 445196 0 - Live 0x0000000000000000 (C) drm_kms_helper 46978 2 i915,radeon, Live 0x0000000000000000 snd 78855 19 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel,snd_hda_codec,snd_hwdep,snd_pcm,snd_rawmidi,snd_seq,snd_timer,snd_seq_device, Live 0x0000000000000000 drm 242038 6 i915,radeon,ttm,drm_kms_helper, Live 0x0000000000000000 soundcore 15091 1 snd, Live 0x0000000000000000 snd_page_alloc 18529 2 snd_hda_intel,snd_pcm, Live 0x0000000000000000 i2c_algo_bit 13423 2 i915,radeon, Live 0x0000000000000000 lp 17799 0 - Live 0x0000000000000000 parport 46562 3 parport_pc,ppdev,lp, Live 0x0000000000000000 r8169 62099 0 - Live 0x0000000000000000 /proc/ioports: 0000-0cf7 : PCI Bus 0000:00 0000-001f : dma1 0020-0021 : pic1 0040-0043 : timer0 0050-0053 : timer1 0060-0060 : keyboard 0062-0062 : EC data 0064-0064 : keyboard 0066-0066 : EC cmd 0070-0077 : rtc0 0080-008f : dma page reg 00a0-00a1 : pic2 00c0-00df : dma2 00f0-00ff : fpu 0400-0453 : pnp 00:05 0400-0403 : ACPI PM1a_EVT_BLK 0404-0405 : ACPI PM1a_CNT_BLK 0408-040b : ACPI PM_TMR 0410-0415 : ACPI CPU throttle 0420-042f : ACPI GPE0_BLK 0450-0450 : ACPI PM2_CNT_BLK 0454-0457 : pnp 00:07 0458-047f : pnp 00:05 0500-057f : pnp 00:05 0680-069f : pnp 00:05 0cf8-0cff : PCI conf1 0d00-ffff : PCI Bus 0000:00 1000-100f : pnp 00:05 164e-164f : pnp 00:05 2000-2000 : pnp 00:05 2004-2004 : pnp 00:05 3000-3fff : PCI Bus 0000:05 3000-30ff : 0000:05:00.0 3000-30ff : r8169 4000-4fff : PCI Bus 0000:04 5000-5fff : PCI Bus 0000:03 6000-6fff : PCI Bus 0000:02 7000-7fff : PCI Bus 0000:01 7000-70ff : 0000:01:00.0 8000-803f : 0000:00:02.0 8040-805f : 0000:00:1f.3 8060-807f : 0000:00:1f.2 8060-807f : ahci 8090-8097 : 0000:00:1f.2 8090-8097 : ahci 8098-809f : 0000:00:1f.2 8098-809f : ahci 80b8-80bb : 0000:00:1f.2 80b8-80bb : ahci 80bc-80bf : 0000:00:1f.2 80bc-80bf : ahci ffff-ffff : pnp 00:05 ffff-ffff : pnp 00:05 /proc/iomem: 00000000-0000ffff : reserved 00010000-0009d7ff : System RAM 0009d800-0009ffff : reserved 000a0000-000bffff : PCI Bus 0000:00 000c0000-000cffff : Video ROM 000e0000-000fffff : reserved 000f0000-000fffff : System ROM 00100000-9ae3efff : System RAM 01000000-01666eeb : Kernel code 01666eec-01ce42ff : Kernel data 01dd3000-01f28fff : Kernel bss 9ae3f000-9aebefff : reserved 9aebf000-9afbefff : ACPI Non-volatile Storage 9afbf000-9affefff : ACPI Tables 9afff000-9affffff : System RAM 9b000000-9f9fffff : reserved 9fa00000-feafffff : PCI Bus 0000:00 9fa00000-9fa00fff : pnp 00:0a a0000000-afffffff : PCI Bus 0000:01 a0000000-afffffff : 0000:01:00.0 b0000000-bfffffff : 0000:00:02.0 c0000000-c03fffff : 0000:00:02.0 c0400000-c13fffff : PCI Bus 0000:02 c1400000-c23fffff : PCI Bus 0000:03 c2400000-c33fffff : PCI Bus 0000:04 c3400000-c43fffff : PCI Bus 0000:05 c3400000-c3403fff : 0000:05:00.0 c3400000-c3403fff : r8169 c3404000-c3404fff : 0000:05:00.0 c3404000-c3404fff : r8169 c4400000-c53fffff : PCI Bus 0000:05 c5400000-c63fffff : PCI Bus 0000:04 c5400000-c5401fff : 0000:04:00.0 c5400000-c5401fff : xhci_hcd c6400000-c73fffff : PCI Bus 0000:03 c6400000-c6400fff : 0000:03:00.0 c6400000-c6400fff : rts_pstor c7400000-c83fffff : PCI Bus 0000:02 c7400000-c7401fff : 0000:02:00.0 c7400000-c7401fff : iwlwifi c8400000-c93fffff : PCI Bus 0000:01 c8400000-c841ffff : 0000:01:00.0 c8420000-c843ffff : 0000:01:00.0 c9400000-c9403fff : 0000:00:1b.0 c9400000-c9403fff : ICH HD audio c9404000-c940400f : 0000:00:16.0 c9404000-c940400f : mei c9406000-c94060ff : 0000:00:1f.3 c9408000-c94087ff : 0000:00:1f.2 c9408000-c94087ff : ahci c9409000-c94093ff : 0000:00:1d.0 c9409000-c94093ff : ehci_hcd c940a000-c940a3ff : 0000:00:1a.0 c940a000-c940a3ff : ehci_hcd e0000000-efffffff : PCI MMCONFIG 0000 [bus 00-ff] e0000000-efffffff : reserved e0000000-efffffff : pnp 00:0a feb00000-feb03fff : reserved fec00000-fec00fff : reserved fec00000-fec003ff : IOAPIC 0 fed00000-fed003ff : HPET 0 fed10000-fed19fff : reserved fed10000-fed17fff : pnp 00:0a fed18000-fed18fff : pnp 00:0a fed19000-fed19fff : pnp 00:0a fed1c000-fed1ffff : reserved fed1c000-fed1ffff : pnp 00:0a fed20000-fed3ffff : pnp 00:0a fed90000-fed93fff : pnp 00:0a fee00000-fee00fff : Local APIC fee00000-fee00fff : reserved ffd80000-ffffffff : reserved 100000000-1dfdfffff : System RAM 1dfe00000-1dfffffff : RAM buffer -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are watching the assignee of the bug.

1 7

[PATCH] drm: nouveau: Fix build warning seen is HWMON is undefined
by Guenter Roeck 05 Oct '12

05 Oct '12

Fix: nouveau_pm.c: In function ‘nouveau_hwmon_init’: nouveau_pm.c:703:24: warning: unused variable ‘therm’ [-Wunused-variable] Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- This was seen in the latest upstream kernel. drivers/gpu/drm/nouveau/nouveau_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c index 0bf64c9..90dc63e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/drivers/gpu/drm/nouveau/nouveau_pm.c @@ -699,10 +699,10 @@ static int nouveau_hwmon_init(struct drm_device *dev) { struct nouveau_pm *pm = nouveau_pm(dev); - struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_therm *therm = nouveau_therm(drm->device); #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) + struct nouveau_drm *drm = nouveau_drm(dev); + struct nouveau_therm *therm = nouveau_therm(drm->device); struct device *hwmon_dev; int ret = 0; -- 1.7.9.7

1 0

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dri-devel October 2012