dri-devel August 2013

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[PATCHv2 0/4] drm/msm: A DRM/KMS driver for snapdragon SoCs
by Rob Clark 07 Aug '13

07 Aug '13

This patchset can also be found here, for easier browsing: http://cgit.freedesktop.org/~robclark/linux/log/?h=drm-next git://people.freedesktop.org/~robclark/linux drm-next Compared to the previous patchset, there are a number of fixes (leaks, etc), fixed handling of some clocks (ie. don't disable PLL that feeds a clk before disabling the clk, etc), cleaned up the handling for device specific config (with placeholders for DT bindings), etc. At this point, I have gnome-shell, wayland (weston drm compositor), etc working pretty well. In userspace, I've a libdrm branch with libdrm_freedreno updated to work on top of either this driver or the downstream android kgsl+fbdev drivers: https://github.com/freedreno/libdrm/commits/msm-drm And the DDX has been updated to either use kms with this driver, or the downstream android drivers. Note that page flipping requires kms: https://github.com/freedreno/xf86-video-freedreno/commits/msm-drm And finally mesa/gallium with a few minor tweaks, mostly updates to the loader to load on either "msm" or legacy/downstream "kgsl": https://github.com/freedreno/mesa/commits/msm-drm History: v1: original v2: only changed patch is a3xx gpu (fix timespec vs ioctl issue, drop setparam ioctl for now). I've left out the two debugfs patches, until I have a chance to attempt to make drm core move minor creation (or at least debugfs) until after load. I've also added a small note about why cmdstream validation is not required in the commit-msg of the a3xx gpu patch. NOTES from the previous RFCs: In the current snapdragon SoC's, we have (at least) 3 different display controller blocks at play: + MDP3 - ?? seems to be what is on geeksphone peak device + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410) + MDSS - snapdragon 800 (I don't have a completely clear picture on which display controller maps to which part #) Plus a handful of blocks around them for HDMI/DSI/etc output. And on gpu side of things: + zero, one, or two 2d cores (z180) + and either a2xx or a3xx 3d core. But, HDMI/DSI/etc blocks seem like they can be shared across multiple display controller blocks. And I for sure don't want to have to deal with N different kms devices from xf86-video-freedreno. Plus, it seems like we can do some clever tricks like use GPU to trigger pageflip after rendering completes (ie. have the kms/crtc code build up gpu cmdstream to update scanout and write FLUSH register after). So, the approach is one drm driver, with some modularity. Different 'struct msm_kms' implementations, depending on display controller. And one or more 'struct msm_gpu' for the various different gpu sub- modules. The kms module provides the plane, crtc, and encoder objects, and loads whatever connectors are appropriate. For MDP4, the mapping is: plane -> PIPE{RGBn,VGn} \ crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device" encoder -> DTV/LCDC/DSI (within MDP4) / connector -> HDMI/DSI/etc --> other device(s) Since the irq's that drm core mostly cares about are vblank/framedone, we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions and treat the MDP4 block's irq as "the" irq. Even though the connectors may have their own irqs which they install themselves. For this reason the display controller is the "master" device. Each connector probably ends up being a separate device, just for the logistics of finding/mapping io region, irq, etc. Idealy we would have a better way than just stashing the platform device in a global (ie. like DT super-node.. but I don't have any snapdragon hw yet that is using DT). Note that so far I've not been able to get any docs on the hw, and it seems that access to such docs would prevent me from working on the freedreno gallium driver. So there may be some mistakes in register names (I had to invent a few, since no sufficient hint was given in the downstream android fbdev driver), bitfield sizes, etc. My current state of understanding the registers is given in the envytools rnndb files at: https://github.com/freedreno/envytools/tree/master/rnndb These files are used both for a parser tool (in the same tree) to parse logged register reads/writes (both from downstream android fbdev driver, and this driver with register logging enabled), as well as to generate the register level headers. Rob Clark (4): drm/msm: add register definitions drm/msm: basic KMS driver for snapdragon drm/msm: add register definitions for gpu drm/msm: add a3xx gpu support drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/msm/Kconfig | 34 + drivers/gpu/drm/msm/Makefile | 30 + drivers/gpu/drm/msm/NOTES | 69 + drivers/gpu/drm/msm/adreno/a2xx.xml.h | 1438 ++++++++++++++++ drivers/gpu/drm/msm/adreno/a3xx.xml.h | 2193 ++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 501 ++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.h | 30 + drivers/gpu/drm/msm/adreno/adreno_common.xml.h | 432 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 350 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 142 ++ drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 254 +++ drivers/gpu/drm/msm/dsi/dsi.xml.h | 262 +++ drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 156 ++ drivers/gpu/drm/msm/dsi/sfpb.xml.h | 46 + drivers/gpu/drm/msm/hdmi/hdmi.c | 246 +++ drivers/gpu/drm/msm/hdmi/hdmi.h | 112 ++ drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 508 ++++++ drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 461 +++++ drivers/gpu/drm/msm/hdmi/hdmi_i2c.c | 281 +++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 141 ++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 214 +++ drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 50 + drivers/gpu/drm/msm/mdp4/mdp4.xml.h | 1053 ++++++++++++ drivers/gpu/drm/msm/mdp4/mdp4_crtc.c | 638 +++++++ drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c | 312 ++++ drivers/gpu/drm/msm/mdp4/mdp4_format.c | 56 + drivers/gpu/drm/msm/mdp4/mdp4_irq.c | 203 +++ drivers/gpu/drm/msm/mdp4/mdp4_kms.c | 374 ++++ drivers/gpu/drm/msm/mdp4/mdp4_kms.h | 193 +++ drivers/gpu/drm/msm/mdp4/mdp4_plane.c | 243 +++ drivers/gpu/drm/msm/msm_connector.c | 34 + drivers/gpu/drm/msm/msm_connector.h | 68 + drivers/gpu/drm/msm/msm_drv.c | 755 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 211 +++ drivers/gpu/drm/msm/msm_fb.c | 202 +++ drivers/gpu/drm/msm/msm_fbdev.c | 258 +++ drivers/gpu/drm/msm/msm_gem.c | 597 +++++++ drivers/gpu/drm/msm/msm_gem.h | 99 ++ drivers/gpu/drm/msm/msm_gem_submit.c | 412 +++++ drivers/gpu/drm/msm/msm_gpu.c | 419 +++++ drivers/gpu/drm/msm/msm_gpu.h | 114 ++ drivers/gpu/drm/msm/msm_ringbuffer.c | 61 + drivers/gpu/drm/msm/msm_ringbuffer.h | 43 + include/uapi/drm/Kbuild | 1 + include/uapi/drm/msm_drm.h | 207 +++ 47 files changed, 14506 insertions(+) create mode 100644 drivers/gpu/drm/msm/Kconfig create mode 100644 drivers/gpu/drm/msm/Makefile create mode 100644 drivers/gpu/drm/msm/NOTES create mode 100644 drivers/gpu/drm/msm/adreno/a2xx.xml.h create mode 100644 drivers/gpu/drm/msm/adreno/a3xx.xml.h create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_gpu.c create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_gpu.h create mode 100644 drivers/gpu/drm/msm/adreno/adreno_common.xml.h create mode 100644 drivers/gpu/drm/msm/adreno/adreno_gpu.c create mode 100644 drivers/gpu/drm/msm/adreno/adreno_gpu.h create mode 100644 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h create mode 100644 drivers/gpu/drm/msm/dsi/dsi.xml.h create mode 100644 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h create mode 100644 drivers/gpu/drm/msm/dsi/sfpb.xml.h create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi.h create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi.xml.h create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_connector.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c create mode 100644 drivers/gpu/drm/msm/hdmi/qfprom.xml.h create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4.xml.h create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_crtc.c create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_format.c create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_irq.c create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.c create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.h create mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_plane.c create mode 100644 drivers/gpu/drm/msm/msm_connector.c create mode 100644 drivers/gpu/drm/msm/msm_connector.h create mode 100644 drivers/gpu/drm/msm/msm_drv.c create mode 100644 drivers/gpu/drm/msm/msm_drv.h create mode 100644 drivers/gpu/drm/msm/msm_fb.c create mode 100644 drivers/gpu/drm/msm/msm_fbdev.c create mode 100644 drivers/gpu/drm/msm/msm_gem.c create mode 100644 drivers/gpu/drm/msm/msm_gem.h create mode 100644 drivers/gpu/drm/msm/msm_gem_submit.c create mode 100644 drivers/gpu/drm/msm/msm_gpu.c create mode 100644 drivers/gpu/drm/msm/msm_gpu.h create mode 100644 drivers/gpu/drm/msm/msm_ringbuffer.c create mode 100644 drivers/gpu/drm/msm/msm_ringbuffer.h create mode 100644 include/uapi/drm/msm_drm.h -- 1.8.3.1

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Re: [RFC 0/1] drm/pl111: Initial drm/kms driver for pl111
by Rob Clark 07 Aug '13

07 Aug '13

On Tue, Aug 6, 2013 at 1:38 PM, Tom Cooksey <tom.cooksey(a)arm.com> wrote: > >> >> ... This is the purpose of the attach step, >> >> so you know all the devices involved in sharing up front before >> >> allocating the backing pages. (Or in the worst case, if you have a >> >> "late attacher" you at least know when no device is doing dma access >> >> to a buffer and can reallocate and move the buffer.) A long time >> >> back, I had a patch that added a field or two to 'struct >> >> device_dma_parameters' so that it could be known if a device >> >> required contiguous buffers.. looks like that never got merged, so >> >> I'd need to dig that back up and resend it. But the idea was to >> >> have the 'struct device' encapsulate all the information that would >> >> be needed to do-the-right-thing when it comes to placement. >> > >> > As I understand it, it's up to the exporting device to allocate the >> > memory backing the dma_buf buffer. I guess the latest possible point >> > you can allocate the backing pages is when map_dma_buf is first >> > called? At that point the exporter can iterate over the current set >> > of attachments, programmatically determine the all the constraints of >> > all the attached drivers and attempt to allocate the backing pages >> > in such a way as to satisfy all those constraints? >> >> yes, this is the idea.. possibly some room for some helpers to help >> out with this, but that is all under the hood from userspace >> perspective >> >> > Didn't you say that programmatically describing device placement >> > constraints was an unbounded problem? I guess we would have to >> > accept that it's not possible to describe all possible constraints >> > and instead find a way to describe the common ones? >> >> well, the point I'm trying to make, is by dividing your constraints >> into two groups, one that impacts and is handled by userspace, and one >> that is in the kernel (ie. where the pages go), you cut down the >> number of permutations that the kernel has to care about considerably. >> And kernel already cares about, for example, what range of addresses >> that a device can dma to/from. I think really the only thing missing >> is the max # of sglist entries (contiguous or not) > > I think it's more than physically contiguous or not. > > For example, it can be more efficient to use large page sizes on > devices with IOMMUs to reduce TLB traffic. I think the size and even > the availability of large pages varies between different IOMMUs. sure.. but I suppose if we can spiff out dma_params to express "I need contiguous", perhaps we can add some way to express "I prefer as-contiguous-as-possible".. either way, this is about where the pages are placed, and not about the layout of pixels within the page, so should be in kernel. It's something that is missing, but I believe that it belongs in dma_params and hidden behind dma_alloc_*() for simple drivers. > There's also the issue of buffer stride alignment. As I say, if the > buffer is to be written by a tile-based GPU like Mali, it's more > efficient if the buffer's stride is aligned to the max AXI bus burst > length. Though I guess a buffer stride only makes sense as a concept > when interpreting the data as a linear-layout 2D image, so perhaps > belongs in user-space along with format negotiation? > Yeah.. this isn't about where the pages go, but about the arrangement within a page. And, well, except for hw that supports the same tiling (or compressed-fb) in display+gpu, you probably aren't sharing tiled buffers. > >> > One problem with this is it duplicates a lot of logic in each >> > driver which can export a dma_buf buffer. Each exporter will need to >> > do pretty much the same thing: iterate over all the attachments, >> > determine of all the constraints (assuming that can be done) and >> > allocate pages such that the lowest-common-denominator is satisfied. >> > >> > Perhaps rather than duplicating that logic in every driver, we could >> > Instead move allocation of the backing pages into dma_buf itself? >> > >> >> I tend to think it is better to add helpers as we see common patterns >> emerge, which drivers can opt-in to using. I don't think that we >> should move allocation into dma_buf itself, but it would perhaps be >> useful to have dma_alloc_*() variants that could allocate for multiple >> devices. > > A helper could work I guess, though I quite like the idea of having > dma_alloc_*() variants which take a list of devices to allocate memory > for. > > >> That would help for simple stuff, although I'd suspect >> eventually a GPU driver will move away from that. (Since you probably >> want to play tricks w/ pools of pages that are pre-zero'd and in the >> correct cache state, use spare cycles on the gpu or dma engine to >> pre-zero uncached pages, and games like that.) > > So presumably you're talking about a GPU driver being the exporter > here? If so, how could the GPU driver do these kind of tricks on > memory shared with another device? > Yes, that is gpu-as-exporter. If someone else is allocating buffers, it is up to them to do these tricks or not. Probably there is a pretty good chance that if you aren't a GPU you don't need those sort of tricks for fast allocation of transient upload buffers, staging textures, temporary pixmaps, etc. Ie. I don't really think a v4l camera or video decoder would benefit from that sort of optimization. > >> >> > Anyway, assuming user-space can figure out how a buffer should be >> >> > stored in memory, how does it indicate this to a kernel driver and >> >> > actually allocate it? Which ioctl on which device does user-space >> >> > call, with what parameters? Are you suggesting using something >> >> > like ION which exposes the low-level details of how buffers are >> > >> laid out in physical memory to userspace? If not, what? >> >> > >> >> >> >> no, userspace should not need to know this. And having a central >> >> driver that knows this for all the other drivers in the system >> >> doesn't really solve anything and isn't really scalable. At best >> >> you might want, in some cases, a flag you can pass when allocating. >> >> For example, some of the drivers have a 'SCANOUT' flag that can be >> >> passed when allocating a GEM buffer, as a hint to the kernel that >> >> 'if this hw requires contig memory for scanout, allocate this >> >> buffer contig'. But really, when it comes to sharing buffers >> >> between devices, we want this sort of information in dev->dma_params >> >> of the importing device(s). >> > >> > If you had a single driver which knew the constraints of all devices >> > on that particular SoC and the interface allowed user-space to >> > specify which devices a buffer is intended to be used with, I guess >> > it could pretty trivially allocate pages which satisfy those > constraints? >> >> keep in mind, even a number of SoC's come with pcie these days. You >> already have things like >> >> https://developer.nvidia.com/content/kayla-platform >> >> You probably want to get out of the SoC mindset, otherwise you are >> going to make bad assumptions that come back to bite you later on. > > Sure - there are always going to be PC-like devices where the > hardware configuration isn't fixed like it is on a traditional SoC. > But I'd rather have a simple solution which works on traditional SoCs > than no solution at all. Today our solution is to over-load the dumb > buffer alloc functions of the display's DRM driver - For now I'm just > looking for the next step up from that! ;-) > True.. the original intention, which is perhaps a bit desktop-centric, really was for there to be a userspace component talking to the drm driver for allocation, ie. xf86-video-foo and/or src/gallium/drivers/foo (for example) ;-) Which means for x11 having a SoC vendor specific xf86-video-foo for x11.. or vendor specific gbm implementation for wayland. (Although at least in the latter case it is a pretty small piece of code.) But that is probably what you are trying to avoid. At any rate, for both xorg and wayland/gbm, you know when a buffer is going to be a scanout buffer. What I'd recommend is define a small userspace API that your customers (the SoC vendors) implement to allocate a scanout buffer and hand you back a dmabuf fd. That could be used both for x11 and for gbm. Inputs should be requested width/height and format. And outputs pitch plus dmabuf fd. (Actually you might even just want to use gbm as your starting point. You could probably just use gbm from xf86-video-armsoc for allocation, to have one thing that works for both wayland and x11. Scanout and cursor buffers should go to vendor/SoC specific fxn, rest can be allocated from mali kernel driver.) > >> > wouldn't need a way to programmatically describe the constraints >> > either: As you say, if userspace sets the "SCANOUT" flag, it would >> > just "know" that on this SoC, that buffer needs to be physically >> > contiguous for example. >> >> not really.. it just knows it wants to scanout the buffer, and tells >> this as a hint to the kernel. >> >> For example, on omapdrm, the SCANOUT flag does nothing on omap4+ >> (where phys contig is not required for scanout), but causes CMA >> (dma_alloc_*()) to be used on omap3. Userspace doesn't care. It just >> knows that it wants to be able to scanout that particular buffer. > > I think that's the idea? The omap3's allocator driver would use > contiguous memory when it detects the SCANOUT flag whereas the omap4 > allocator driver wouldn't have to. No complex negotiation of > constraints - it just "knows". > well, it is same allocating driver in both cases (although maybe that is unimportant). The "it" that just knows it wants to scanout is userspace. The "it" that just knows that scanout translates to contiguous (or not) is the kernel. Perhaps we are saying the same thing ;-) BR, -R > > Cheers, > > Tom > > > >

2 1

[Bug 60710] New: Radeon RV530 I2C failure with DVI monitor.
by bugzilla-daemon＠bugzilla.kernel.org 07 Aug '13

07 Aug '13

https://bugzilla.kernel.org/show_bug.cgi?id=60710 Bug ID: 60710 Summary: Radeon RV530 I2C failure with DVI monitor. Product: Drivers Version: 2.5 Kernel Version: 3.10.5 Hardware: i386 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: rankincj(a)yahoo.com Regression: No Experimenting with my T60p laptop with built-in M66GL chip (~RV530?); 1680x1050 LVDS panel + 1920x1200 LCD monitor. Also attached to a docking station with HD4650 card, and 1920x1080 HDTV connected to that. This combination seems to start up fine. However, when I was trying to switch my primary display to be the HDTV, the latop "beeped" at me and then shut down all displays. Studying my logs later revealed the following: Aug 6 15:21:39 lantern kernel: [TTM] Illegal buffer object size Aug 6 15:21:39 lantern kernel: [TTM] Illegal buffer object size Aug 6 15:21:39 lantern kernel: [drm:radeon_gem_object_create] *ERROR* Failed to allocate GEM object (0, 6, 4096, -22) Aug 6 15:21:39 lantern kernel: [drm:r500_hw_i2c_xfer] *ERROR* failed to get i2c bus Aug 6 15:21:39 lantern kernel: [drm:r500_hw_i2c_xfer] *ERROR* failed to get i2c bus Aug 6 15:21:39 lantern kernel: [drm:r500_hw_i2c_xfer] *ERROR* failed to get i2c bus Aug 6 15:21:39 lantern kernel: [drm:r500_hw_i2c_xfer] *ERROR* failed to get i2c bus Aug 6 15:21:39 lantern kernel: [drm:r500_hw_i2c_xfer] *ERROR* failed to get i2c bus After this point, only the LVDS panel would work. Worse, I had to boot with "radeon.hw_i2c=0" before I was able to turn the 1920x1200 monitor back on with: $ xrandr --output DVI-0 --auto Now that everything is (finally!) working again as it used to, XRandR is reporting this: $ xrandr -q Screen 0: minimum 320 x 200, current 1920 x 1200, maximum 8192 x 8192 VGA-0 disconnected (normal left inverted right x axis y axis) LVDS connected (normal left inverted right x axis y axis) 1680x1050 60.1 + 50.1 1400x1050 60.0 1280x1024 59.9 1440x900 59.9 1280x960 59.9 1280x854 59.9 1280x800 59.8 1280x720 59.9 1152x768 59.8 1024x768 59.9 800x600 59.9 848x480 59.7 720x480 59.7 640x480 59.4 DVI-0 connected primary 1920x1200+0+0 (normal left inverted right x axis y axis) 546mm x 352mm 1680x1050 59.9 + 1920x1200 60.0*+ 1600x1200 60.0 1600x1000 60.0 1280x1024 75.0 1280x960 60.0 1152x864 75.0 1024x768 75.1 60.0 832x624 74.6 800x600 75.0 60.3 640x480 75.0 60.0 720x400 70.1 DVI-1-1 connected (normal left inverted right x axis y axis) 1920x1080 50.0 + 60.0 DIN-1-0 disconnected (normal left inverted right x axis y axis) DVI-1-2 disconnected (normal left inverted right x axis y axis) I don't know what happened - all I know is that HW I2C broke suddenly and had to be disabled completely before I could restore everything. However, I have since turned HW I2C back on - and it's fine again! Did I push something over the edge of a cliff? -- You are receiving this mail because: You are watching the assignee of the bug.

1 6

[PATCH] drm/nouveau: require contiguous bo for framebuffer
by Maarten Lankhorst 07 Aug '13

07 Aug '13

This was already required before, but no check in the kernel was done to enforce it. Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)canonical.com> --- diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 73cf240..ddb065c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -107,6 +107,11 @@ nouveau_framebuffer_init(struct drm_device *dev, return -EINVAL; } + if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { + NV_ERROR(drm, "framebuffer requires contiguous bo\n"); + return -EINVAL; + } + if (nv_device(drm->device)->chipset == 0x50) nv_fb->r_format |= (tile_flags << 8);

1 0

Some edid-decode patches
by Damien Lespiau 07 Aug '13

07 Aug '13

A bit more context than the previous patch that was a bit alone. This series parses yet a bit more of the EDID: - The HDMI VICs in the HDMI vendor specific block (HDMI 1.4, 4k modes) - The CEA Video Capability Data Block It also includes 2 EDIDs of TVs that have those bits. -- Damien

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Re: [RFC 0/1] drm/pl111: Initial drm/kms driver for pl111
by Rob Clark 07 Aug '13

07 Aug '13

On Tue, Aug 6, 2013 at 7:31 AM, Tom Cooksey <tom.cooksey(a)arm.com> wrote: > >> > So in some respects, there is a constraint on how buffers which will >> > be drawn to using the GPU are allocated. I don't really like the idea >> > of teaching the display controller DRM driver about the GPU buffer >> > constraints, even if they are fairly trivial like this. If the same >> > display HW IP is being used on several SoCs, it seems wrong somehow >> > to enforce those GPU constraints if some of those SoCs don't have a >> > GPU. >> >> Well, I suppose you could get min_pitch_alignment from devicetree, or >> something like this.. >> >> In the end, the easy solution is just to make the display allocate to >> the worst-case pitch alignment. In the early days of dma-buf >> discussions, we kicked around the idea of negotiating or >> programatically describing the constraints, but that didn't really >> seem like a bounded problem. > > Yeah - I was around for some of those discussions and agree it's not > really an easy problem to solve. > > > >> > We may also then have additional constraints when sharing buffers >> > between the display HW and video decode or even camera ISP HW. >> > Programmatically describing buffer allocation constraints is very >> > difficult and I'm not sure you can actually do it - there's some >> > pretty complex constraints out there! E.g. I believe there's a >> > platform where Y and UV planes of the reference frame need to be in >> > separate DRAM banks for real-time 1080p decode, or something like >> > that? >> >> yes, this was discussed. This is different from pitch/format/size >> constraints.. it is really just a placement constraint (ie. where do >> the physical pages go). IIRC the conclusion was to use a dummy >> devices with it's own CMA pool for attaching the Y vs UV buffers. >> >> > Anyway, I guess my point is that even if we solve how to allocate >> > buffers which will be shared between the GPU and display HW such that >> > both sets of constraints are satisfied, that may not be the end of >> > the story. >> > >> >> that was part of the reason to punt this problem to userspace ;-) >> >> In practice, the kernel drivers doesn't usually know too much about >> the dimensions/format/etc.. that is really userspace level knowledge. >> There are a few exceptions when the kernel needs to know how to setup >> GTT/etc for tiled buffers, but normally this sort of information is up >> at the next level up (userspace, and drm_framebuffer in case of >> scanout). Userspace media frameworks like GStreamer already have a >> concept of format/caps negotiation. For non-display<->gpu sharing, I >> think this is probably where this sort of constraint negotiation >> should be handled. > > I agree that user-space will know which devices will access the buffer > and thus can figure out at least a common pixel format. Though I'm not > so sure userspace can figure out more low-level details like alignment > and placement in physical memory, etc. well, let's divide things up into two categories: 1) the arrangement and format of pixels.. ie. what userspace would need to know if it mmap's a buffer. This includes pixel format, stride, etc. This should be negotiated in userspace, it would be crazy to try to do this in the kernel. 2) the physical placement of the pages. Ie. whether it is contiguous or not. Which bank the pages in the buffer are placed in, etc. This is not visible to userspace. This is the purpose of the attach step, so you know all the devices involved in sharing up front before allocating the backing pages. (Or in the worst case, if you have a "late attacher" you at least know when no device is doing dma access to a buffer and can reallocate and move the buffer.) A long time back, I had a patch that added a field or two to 'struct device_dma_parameters' so that it could be known if a device required contiguous buffers.. looks like that never got merged, so I'd need to dig that back up and resend it. But the idea was to have the 'struct device' encapsulate all the information that would be needed to do-the-right-thing when it comes to placement. > Anyway, assuming user-space can figure out how a buffer should be > stored in memory, how does it indicate this to a kernel driver and > actually allocate it? Which ioctl on which device does user-space > call, with what parameters? Are you suggesting using something like > ION which exposes the low-level details of how buffers are laid out in > physical memory to userspace? If not, what? no, userspace should not need to know this. And having a central driver that knows this for all the other drivers in the system doesn't really solve anything and isn't really scalable. At best you might want, in some cases, a flag you can pass when allocating. For example, some of the drivers have a 'SCANOUT' flag that can be passed when allocating a GEM buffer, as a hint to the kernel that 'if this hw requires contig memory for scanout, allocate this buffer contig'. But really, when it comes to sharing buffers between devices, we want this sort of information in dev->dma_params of the importing device(s). BR, -R

3 3

[PATCH] drm: Fix undefined reference to drm_agp_clear() on non-AGP platforms
by Laurent Pinchart 07 Aug '13

07 Aug '13

The drm_agp_clear() function is only defined on platforms with AGP support. Move the drm_core_has_AGP() check from drm_agp_clear() to the caller to let the compiler optimize the drm_agp_clear() call away. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas(a)ideasonboard.com> --- drivers/gpu/drm/drm_agpsupport.c | 2 +- drivers/gpu/drm/drm_drv.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) This fixes a link-time build error in drm-next. An alternative approach would be to guard the drm_agp_clear() call in drm_drv.c with an #if __OS_HAS_AGP. I can resubmit the patch to do so if preferred. diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c index e301d65..084a674 100644 --- a/drivers/gpu/drm/drm_agpsupport.c +++ b/drivers/gpu/drm/drm_agpsupport.c @@ -439,7 +439,7 @@ void drm_agp_clear(struct drm_device *dev) { struct drm_agp_mem *entry, *tempe; - if (!drm_core_has_AGP(dev) || !dev->agp) + if (!dev->agp) return; if (drm_core_check_feature(dev, DRIVER_MODESET)) return; diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index dddd799..1e2ad35 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -195,7 +195,8 @@ int drm_lastclose(struct drm_device * dev) mutex_lock(&dev->struct_mutex); - drm_agp_clear(dev); + if (drm_core_has_AGP(dev)) + drm_agp_clear(dev); if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg && !drm_core_check_feature(dev, DRIVER_MODESET)) { -- Regards, Laurent Pinchart

4 3

[3.11-rc4] Possible problem with nouveau drm driver and interrupts on Dell Latitude E6510
by Mikael Pettersson 07 Aug '13

07 Aug '13

My Latitude E6510 has the following graphics HW: 01:00.0 VGA compatible controller: nVidia Corporation GT218 [NVS 3100M] (rev a2) (prog-if 00 [VGA controller]) Subsystem: Dell Latitude E6510 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at e2000000 (32-bit, non-prefetchable) [size=16M] Memory at d0000000 (64-bit, prefetchable) [size=256M] Memory at e0000000 (64-bit, prefetchable) [size=32M] I/O ports at 7000 [size=128] Expansion ROM at e3000000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: nouveau User-space is Fedora 17. No proprietary drivers of any kind. Up to the 3.11-rc2 kernel I never had any problems with it. With 3.11-rc4 I've twice so far had the following problem: 0. X has been running for a while with fvwm, a couple of xterms, emacs, firefox, and xclock. 1. Suddenly text scrolling in xterm or emacs becomes extremely slow and grinds to a halt. Moving the mouse (which generates interrupts) resumes the scrolling, but then it stops again unless I keep moving the mouse. 2. At this time there are no kernel messages indicating problems. 3. If I exit X then the console behaves normally. 4. If I try to start X again it paints the background of my desktop and shows the mouse cursor, but nothing else comes up and it's unresponsive to mouse or keyboard input. I have to press C-A-D or the power button at this point. 5. After 1. above occurs, even a warm reboot isn't enough to make X work again. A full power-cycled reboot is needed to bring the machine back to normal. /Mikael

1 0

Re: [drm-intel:drm-intel-nightly 243/249] undefined reference to `drm_agp_clear'
by David Herrmann 07 Aug '13

07 Aug '13

Hi On Wed, Aug 7, 2013 at 10:19 AM, kbuild test robot <fengguang.wu(a)intel.com> wrote: > tree: git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-nightly > head: 3224cf6c3ee5ab9c280052c9fbed4f660310c411 > commit: 28ec711cd427f8b61f73712a43b8100ba8ca933b [243/249] drm/agp: move AGP cleanup paths to drm_agpsupport.c > config: x86_64-randconfig-a02-0807 (attached as .config) > > All error/warnings: > > drivers/built-in.o: In function `drm_lastclose': >>> (.text+0x904a0): undefined reference to `drm_agp_clear' We called drm_agp_release() in the same code-path before. How did that work without CONFIG_AGP? Ugh, *confused*

2 1

[PATCH 0/3] Fix backlight issues on some Windows 8 systems
by Matthew Garrett 07 Aug '13

07 Aug '13

Windows 8 introduced new policy for backlight control by pushing it out to graphics drivers. This appears to have coincided with a range of vendors adding Windows 8 checks to their backlight control code which trigger either awkward behaviour (Lenovo) or complete brokenness (some Dells). The simplest thing to do would be to just disable ACPI backlight control entirely if the firmware indicates Windows 8 support, but it's entirely possible that individual graphics drivers might still make use of the ACPI functionality in preference to native control. The first two patches in this series are picked from other patchesets aimed at solving similar problems. The last simply unregisters ACPI backlight control on Windows 8 systems when using an Intel GPU. Similar code could be added to other drivers, but I'm reluctant to do so without further investigation as to the behaviour of the vendor drivers under Windows. -- Matthew Garrett | mjg59(a)srcf.ucam.org

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dri-devel August 2013