dri-devel September 2013

dri-devel@lists.freedesktop.org

153 participants
824 discussions

[PATCH] drm/nv84-: write fence value on exit, and restore value on init.
by Maarten Lankhorst 09 Sep '13

09 Sep '13

This increases the chance slightly that recovery from lockup can happen succesfully. Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)canonical.com> --- drivers/gpu/drm/nouveau/nv84_fence.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index 2cf0ade..daf4b18 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -122,8 +122,11 @@ nv84_fence_context_del(struct nouveau_channel *chan) struct drm_device *dev = chan->drm->dev; struct nv84_fence_priv *priv = chan->drm->fence; struct nv84_fence_chan *fctx = chan->fence; + struct nouveau_fifo_chan *fifo = (void *)chan->object; int i; + nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, fctx->base.sequence); + for (i = 0; i < dev->mode_config.num_crtc; i++) { struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); @@ -168,7 +171,7 @@ nv84_fence_context_new(struct nouveau_channel *chan) ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]); } - nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000); + fctx->base.sequence = nouveau_bo_rd32(priv->bo, fifo->chid * 16/4); if (ret) nv84_fence_context_del(chan); -- 1.8.3.4

2 3

[PATCH] drm/nv10/plane: add plane support for nv10-nv40
by Ilia Mirkin 09 Sep '13

09 Sep '13

Signed-off-by: Ilia Mirkin <imirkin(a)alum.mit.edu> --- This has received light testing on NV18 and NV34 cards, using the modetest tool. Userspace support to use this for xv is not yet ready. I decided against creating a new "pvideo" engine -- that just seems way too heavy-handed compared to the ~10 lines of code in disp/nv04.c to deal with the PVIDEO interrupts. Even though there are two possible planes, they are sufficiently linked together that I decided to just expose them as one, and do a double-buffering-style thing, similar to what xf86-video-nouveau did pre-KMS. drivers/gpu/drm/nouveau/core/engine/disp/nv04.c | 9 + drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c | 1 + drivers/gpu/drm/nouveau/dispnv04/Makefile | 1 + drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 + drivers/gpu/drm/nouveau/dispnv04/disp.h | 3 + drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 +- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 320 ++++++++++++++++++++++++ 7 files changed, 342 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/dispnv04/overlay.c diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c index 05e903f..a0bc8a8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c @@ -59,6 +59,7 @@ nv04_disp_intr(struct nouveau_subdev *subdev) struct nv04_disp_priv *priv = (void *)subdev; u32 crtc0 = nv_rd32(priv, 0x600100); u32 crtc1 = nv_rd32(priv, 0x602100); + u32 pvideo; if (crtc0 & 0x00000001) { nouveau_event_trigger(priv->base.vblank, 0); @@ -69,6 +70,14 @@ nv04_disp_intr(struct nouveau_subdev *subdev) nouveau_event_trigger(priv->base.vblank, 1); nv_wr32(priv, 0x602100, 0x00000001); } + + if (nv_device(priv)->chipset >= 0x10 && + nv_device(priv)->chipset <= 0x40) { + pvideo = nv_rd32(priv, 0x8100); + if (pvideo & ~0x11) + nv_info(priv, "PVIDEO intr: %08x\n", pvideo); + nv_wr32(priv, 0x8100, pvideo); + } } static int diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c index 64aa4ed..062c048 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c @@ -33,6 +33,7 @@ nv04_mc_intr[] = { { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, + { 0x00010000, NVDEV_ENGINE_DISP }, { 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */ { 0x00100000, NVDEV_SUBDEV_TIMER }, { 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */ diff --git a/drivers/gpu/drm/nouveau/dispnv04/Makefile b/drivers/gpu/drm/nouveau/dispnv04/Makefile index ea3f5b8..424a489 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/Makefile +++ b/drivers/gpu/drm/nouveau/dispnv04/Makefile @@ -5,6 +5,7 @@ nouveau-y += dispnv04/dac.o nouveau-y += dispnv04/dfp.o nouveau-y += dispnv04/disp.o nouveau-y += dispnv04/hw.o +nouveau-y += dispnv04/overlay.o nouveau-y += dispnv04/tvmodesnv17.o nouveau-y += dispnv04/tvnv04.o nouveau-y += dispnv04/tvnv17.o diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 4908d3f..b13ff0f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -140,6 +140,8 @@ nv04_display_create(struct drm_device *dev) func->save(encoder); } + nouveau_overlay_init(dev); + return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index 9928187..bb5c1bd 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h @@ -123,6 +123,9 @@ int nv04_tv_create(struct drm_connector *, struct dcb_output *); /* nv17_tv.c */ int nv17_tv_create(struct drm_connector *, struct dcb_output *); +/* overlay.c */ +void nouveau_overlay_init(struct drm_device *dev); + static inline bool nv_two_heads(struct drm_device *dev) { diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index ffd2641..b1c5cd6 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -27,6 +27,7 @@ #include "hw.h" #include <subdev/bios/pll.h> +#include <subdev/fb.h> #include <subdev/clock.h> #include <subdev/timer.h> @@ -664,6 +665,7 @@ nv_load_state_ext(struct drm_device *dev, int head, struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_device *device = nv_device(drm->device); struct nouveau_timer *ptimer = nouveau_timer(device); + struct nouveau_fb *pfb = nouveau_fb(device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t reg900; int i; @@ -680,10 +682,10 @@ nv_load_state_ext(struct drm_device *dev, int head, nv_wr32(device, NV_PVIDEO_INTR_EN, 0); nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); - nv_wr32(device, NV_PVIDEO_LIMIT(0), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_LIMIT(1), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //drm->fb_available_size - 1); + nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1); nv_wr32(device, NV_PBUS_POWERCTRL_2, 0); NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c new file mode 100644 index 0000000..7caf26f --- /dev/null +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -0,0 +1,320 @@ +/* + * Copyright 2013 Ilia Mirkin + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Implementation based on the pre-KMS implementation in xf86-video-nouveau, + * written by Arthur Huillet. + */ + +#include <drm/drmP.h> +#include <drm/drm_crtc.h> +#include <drm/drm_fourcc.h> + +#include "nouveau_drm.h" + +#include "nouveau_bo.h" +#include "nouveau_connector.h" +#include "nouveau_display.h" +#include "nvreg.h" + + +struct nouveau_plane { + struct drm_plane base; + bool flip; + struct nouveau_bo *cur; + + struct { + struct drm_property *colorkey; + struct drm_property *contrast; + struct drm_property *brightness; + struct drm_property *hue; + struct drm_property *saturation; + struct drm_property *iturbt_709; + } props; + + int colorkey; + int contrast; + int brightness; + int hue; + int saturation; + int iturbt_709; +}; + +static uint32_t formats[] = { + DRM_FORMAT_NV12, + DRM_FORMAT_UYVY, +}; + +/* Sine can be approximated with + * http://en.wikipedia.org/wiki/Bhaskara_I's_sine_approximation_formula + * sin(x degrees) ~= 4 x (180 - x) / (40500 - x (180 - x) ) + * Note that this only works for the range [0, 180]. + * Also note that sin(x) == -sin(x - 180) + */ +static inline int +sin_mul(int degrees, int factor) +{ + if (degrees > 180) { + degrees -= 180; + factor *= -1; + } + return factor * 4 * degrees * (180 - degrees) / + (40500 - degrees * (180 - degrees)); +} + +/* cos(x) = sin(x + 90) */ +static inline int +cos_mul(int degrees, int factor) +{ + return sin_mul((degrees + 90) % 360, factor); +} + +static int +nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) +{ + struct nouveau_device *dev = nouveau_dev(plane->dev); + struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; + struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); + struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); + struct nouveau_bo *cur = nv_plane->cur; + bool flip = nv_plane->flip; + int format = ALIGN(src_w * 4, 0x100); + int soff = NV_PCRTC0_SIZE * nv_crtc->index; + int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; + int ret; + + if (format > 0xffff) + return -EINVAL; + + ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM); + if (ret) + return ret; + + nv_plane->cur = nv_fb->nvbo; + + /* Source parameters given in 16.16 fixed point, ignore fractional. */ + src_x = src_x >> 16; + src_y = src_y >> 16; + src_w = src_w >> 16; + src_h = src_h >> 16; + + nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); + nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); + + nv_wr32(dev, NV_PVIDEO_BASE(flip), 0); + nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset); + nv_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); + nv_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); + nv_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); + nv_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); + nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); + nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); + + if (fb->pixel_format == DRM_FORMAT_NV12) { + format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; + format |= NV_PVIDEO_FORMAT_PLANAR; + } + if (nv_plane->iturbt_709) + format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; + if (nv_plane->colorkey & (1 << 24)) + format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; + + if (fb->pixel_format == DRM_FORMAT_NV12) { + nv_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); + nv_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), + nv_fb->nvbo->bo.offset + fb->offsets[1]); + } + nv_wr32(dev, NV_PVIDEO_FORMAT(flip), format); + nv_wr32(dev, NV_PVIDEO_STOP, 0); + /* TODO: wait for vblank? */ + nv_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); + nv_plane->flip = !flip; + + if (cur) + nouveau_bo_unpin(cur); + + return 0; +} + +static int +nv10_disable_plane(struct drm_plane *plane) +{ + struct nouveau_device *dev = nouveau_dev(plane->dev); + struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; + + nv_wr32(dev, NV_PVIDEO_STOP, 1); + if (nv_plane->cur) { + nouveau_bo_unpin(nv_plane->cur); + nv_plane->cur = NULL; + } + + return 0; +} + +static void +nv10_destroy_plane(struct drm_plane *plane) +{ + nv10_disable_plane(plane); + drm_plane_cleanup(plane); + kfree(plane); +} + +static void +nv10_set_params(struct nouveau_plane *plane) +{ + struct nouveau_device *dev = nouveau_dev(plane->base.dev); + u32 luma = (plane->brightness - 512) << 16 | plane->contrast; + u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | + (cos_mul(plane->hue, plane->saturation) & 0xffff); + u32 format = 0; + + nv_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma); + nv_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma); + nv_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma); + nv_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma); + nv_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff); + + if (plane->cur) { + if (plane->iturbt_709) + format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; + if (plane->colorkey & (1 << 24)) + format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; + nv_mask(dev, NV_PVIDEO_FORMAT(plane->flip), + NV_PVIDEO_FORMAT_MATRIX_ITURBT709 | + NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY, + format); + } +} + +static int +nv10_set_property(struct drm_plane *plane, + struct drm_property *property, + uint64_t value) +{ + struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; + + if (property == nv_plane->props.colorkey) + nv_plane->colorkey = value; + else if (property == nv_plane->props.contrast) + nv_plane->colorkey = value; + else if (property == nv_plane->props.brightness) + nv_plane->brightness = value; + else if (property == nv_plane->props.hue) + nv_plane->hue = value; + else if (property == nv_plane->props.saturation) + nv_plane->saturation = value; + else if (property == nv_plane->props.iturbt_709) + nv_plane->iturbt_709 = value; + else + return -EINVAL; + + nv10_set_params(nv_plane); + return 0; +} + +static const struct drm_plane_funcs nv10_plane_funcs = { + .update_plane = nv10_update_plane, + .disable_plane = nv10_disable_plane, + .set_property = nv10_set_property, + .destroy = nv10_destroy_plane, +}; + +static void +nv10_overlay_init(struct drm_device *device) +{ + struct nouveau_device *dev = nouveau_dev(device); + struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL); + int ret; + + if (!plane) + return; + + ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */, + &nv10_plane_funcs, + formats, ARRAY_SIZE(formats), false); + if (ret) + goto err; + + /* Set up the plane properties */ + plane->props.colorkey = drm_property_create_range( + device, 0, "colorkey", 0, 0x01ffffff); + plane->props.contrast = drm_property_create_range( + device, 0, "contrast", 0, 8192 - 1); + plane->props.brightness = drm_property_create_range( + device, 0, "brightness", 0, 1024); + plane->props.hue = drm_property_create_range( + device, 0, "hue", 0, 359); + plane->props.saturation = drm_property_create_range( + device, 0, "saturation", 0, 8192 - 1); + plane->props.iturbt_709 = drm_property_create_range( + device, 0, "iturbt_709", 0, 1); + if (!plane->props.colorkey || + !plane->props.contrast || + !plane->props.brightness || + !plane->props.hue || + !plane->props.saturation || + !plane->props.iturbt_709) + goto cleanup; + + plane->colorkey = 0; + drm_object_attach_property(&plane->base.base, + plane->props.colorkey, plane->colorkey); + + plane->contrast = 0x1000; + drm_object_attach_property(&plane->base.base, + plane->props.contrast, plane->contrast); + + plane->brightness = 512; + drm_object_attach_property(&plane->base.base, + plane->props.brightness, plane->brightness); + + plane->hue = 0; + drm_object_attach_property(&plane->base.base, + plane->props.hue, plane->hue); + + plane->saturation = 0x1000; + drm_object_attach_property(&plane->base.base, + plane->props.saturation, plane->saturation); + + plane->iturbt_709 = 0; + drm_object_attach_property(&plane->base.base, + plane->props.iturbt_709, plane->iturbt_709); + + nv10_set_params(plane); + nv_wr32(dev, NV_PVIDEO_STOP, 1); + return; +cleanup: + drm_plane_cleanup(&plane->base); +err: + kfree(plane); + nv_error(dev, "Failed to create plane\n"); +} + +void +nouveau_overlay_init(struct drm_device *device) +{ + struct nouveau_device *dev = nouveau_dev(device); + if (dev->chipset >= 0x10 && dev->chipset <= 0x40) + nv10_overlay_init(device); +} -- 1.8.1.5

2 1

[Bug 61011] New: Radeon Screen Corruption since merged patch of Bug 60639
by bugzilla-daemon＠bugzilla.kernel.org 09 Sep '13

09 Sep '13

https://bugzilla.kernel.org/show_bug.cgi?id=61011 Bug ID: 61011 Summary: Radeon Screen Corruption since merged patch of Bug 60639 Product: Drivers Version: 2.5 Kernel Version: 3.10.5 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: Hamsi2k(a)freenet.de Regression: No Created attachment 107641 --> https://bugzilla.kernel.org/attachment.cgi?id=107641&action=edit This is the result I own a board: 880GMH/U3S3 with radeon chipset HD 4250. Since I upgraded to kernel 3.10.5 I get some screen corruption (shown in attached picture). Then I used git bisect to track down the commit between the last working kernel 3.10.2 and 3.10.5. The commit in question is 6f8bbaf568c7f2c497558bfd04654c0b9841ad57 which points to https://bugzilla.kernel.org/show_bug.cgi?id=60639. Without this commit I was able to build and run the 3.11.0 kernel release. This is also the version, which attached log files refers to. As reference: I created an thread https://bbs.archlinux.org/viewtopic.php?id=169361 where I first described my problem. -- You are receiving this mail because: You are watching the assignee of the bug.

1 7

[PATCH] nouveau reclocking on nv40 not working since 77145f1cbdf8d28b46ff8070ca749bad821e0774
by Pali Rohár 09 Sep '13

09 Sep '13

Hello, in commit 77145f1cbdf8d28b46ff8070ca749bad821e0774 was introduced error which cause that on my Nvidia 6600GT card reclocking not working anymore. There is missing assigment of return value from pll_calc to ret. After this patch reclocking on my card working fine again. Above broken commit was introduced in kernel 3.7, so consider backporting this patch to older kernels too. Signed-off-by: Pali Rohár <pali.rohar(a)gmail.com> diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c index 3af5bcd..625f80d 100644 --- a/drivers/gpu/drm/nouveau/nv40_pm.c +++ b/drivers/gpu/drm/nouveau/nv40_pm.c @@ -131,7 +131,7 @@ nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll, if (clk < pll->vco1.max_freq) pll->vco2.max_freq = 0; - pclk->pll_calc(pclk, pll, clk, &coef); + ret = pclk->pll_calc(pclk, pll, clk, &coef); if (ret == 0) return -ERANGE; -- Pali Rohár pali.rohar(a)gmail.com

3 9

[Bug 42490] NUTMEG DP to VGA bridge not working
by bugzilla-daemon＠freedesktop.org 07 Sep '13

07 Sep '13

https://bugs.freedesktop.org/show_bug.cgi?id=42490 --- Comment #46 from rmccorkell(a)karoshi.org.uk --- I can confirm that this bug is still present in Linux 3.8.0, using X Server 7.7 and driver 7.1.0. As graphics are initialized screen just goes black. -- You are receiving this mail because: You are the assignee for the bug.

1 0

Patch for i915 module load parameter to igore edp bpp value
by Jyrki Kuoppala 07 Sep '13

07 Sep '13

Patch against Linus' latest git, fixing bug 59841 reported at https://bugzilla.kernel.org/show_bug.cgi?id=59841 for the cases where a quirk has not been added to the kernel for specific hardware. At least one Intel HD Graphics 4000 PCI display controller hardware with PCI id 0x0166 appears to return an incorrect edp bpp value 18 instead of the correct 24. This patch allows user to set a flag at module load time to ignore the incorrect edp bpp value. Correction to previous patch notes: the edp bpp value returned is 18, not 16 as erroneusly claimed in previous patch (quirking the feature). Date: Sat, 7 Sep 2013 13:17:59 +0300 Subject: [PATCH] i915: add module load parameter to ignore incorrect edp_bpp value Signed-off-by: Jyrki Kuoppala <jkp(a)iki.fi> --- drivers/gpu/drm/i915/i915_drv.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 1 + 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ccb28ea..debb785 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -136,6 +136,10 @@ int i915_enable_ips __read_mostly = 1; module_param_named(enable_ips, i915_enable_ips, int, 0600); MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); +bool i915_ignore_edp_bpp __read_mostly; +module_param_named(i915_ignore_edp_bpp, i915_ignore_edp_bpp, bool, 0600); +MODULE_PARM_DESC(i915_ignore_edp_bpp, "Ignore BDB edp BPP value (default: false)"); + bool i915_fastboot __read_mostly = 0; module_param_named(fastboot, i915_fastboot, bool, 0600); MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3784be1..95b1abe 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1707,6 +1707,7 @@ extern int i915_enable_psr __read_mostly; extern unsigned int i915_preliminary_hw_support __read_mostly; extern int i915_disable_power_well __read_mostly; extern int i915_enable_ips __read_mostly; +extern bool i915_ignore_edp_bpp __read_mostly; extern bool i915_fastboot __read_mostly; extern int i915_enable_pc8 __read_mostly; extern int i915_pc8_timeout __read_mostly; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0e0fc37..a3442cd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -732,6 +732,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, * bpc in between. */ bpp = pipe_config->pipe_bpp; if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp + && !i915_ignore_edp_bpp && !(dev_priv->quirks & QUIRK_IGNORE_EDP_BPP)) { DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", dev_priv->vbt.edp_bpp); -- 1.8.1.2

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Patch for quirking Asus tx300 and others incorrect edp bpp value
by Jyrki Kuoppala 07 Sep '13

07 Sep '13

Patch against Linus' latest git, fixing bug 59841 reported at https://bugzilla.kernel.org/show_bug.cgi?id=59841 The Intel HD Graphics 4000 PCI display controller id 0x0166 appears to return an incorrect edp bpp value 16 instead of the correct 24. This patch adds a quirk for the controller. Date: Sat, 7 Sep 2013 12:18:31 +0300 Subject: [PATCH] i915: add quirk to ignore incorrect edp_bpp value on Asus TX300 and others Signed-off-by: Jyrki Kuoppala <jkp(a)iki.fi> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 3 ++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 52a3785..3784be1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -651,6 +651,7 @@ enum intel_sbi_destination { #define QUIRK_LVDS_SSC_DISABLE (1<<1) #define QUIRK_INVERT_BRIGHTNESS (1<<2) #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) +#define QUIRK_IGNORE_EDP_BPP (1<<4) struct intel_fbdev; struct intel_fbc_work; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 38452d8..2a8cec3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9907,6 +9907,17 @@ static void quirk_no_pcm_pwm_enable(struct drm_device *dev) DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); } +/* + * Some machines (e.g. Asus TX300) incorrectly return 18bpp in UEFI mode + * from vbe edp data + */ +static void quirk_no_edp_bpp_enable(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + dev_priv->quirks |= QUIRK_IGNORE_EDP_BPP; + DRM_INFO("applying IGNORE_EDP_BPP quirk\n"); +} + struct intel_quirk { int device; int subsystem_vendor; @@ -9981,6 +9992,11 @@ static struct intel_quirk intel_quirks[] = { { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, + + /* at least Asus TX300 (0x1042 0x15b7), + UX32VD (0x1042 0x1507), Dell XPS13 and Toshiba Kirabook, + see https://bugzilla.kernel.org/show_bug.cgi?id=59841 */ + { 0x0166, PCI_ANY_ID, PCI_ANY_ID, quirk_no_edp_bpp_enable }, }; static void intel_init_quirks(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2151d13..0e0fc37 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -731,7 +731,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, /* Walk through all bpp values. Luckily they're all nicely spaced with 2 * bpc in between. */ bpp = pipe_config->pipe_bpp; - if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) { + if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp + && !(dev_priv->quirks & QUIRK_IGNORE_EDP_BPP)) { DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", dev_priv->vbt.edp_bpp); bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp); -- 1.8.1.2

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Re: [PULL] drm-intel-fixes
by Daniel Vetter 06 Sep '13

06 Sep '13

Blergh, forgotten to cc: mailing lists ... -Daniel On Fri, Sep 6, 2013 at 9:48 AM, Daniel Vetter <daniel(a)ffwll.ch> wrote: > Hi Dave, > > Already a decent pile of fixes and a few stragglers for the merge window. > Nothing in here though to appease Linus :( > - Early stolen mem reservation from Jesse in x86 boot code. Acked by Ingo > and hpa. This was ready much earlier but somehow I've thought it'd go > in through x86 trees, hence why this is late. Avoids the pci resource > code to plant mmiobars in the middle of stolen mem and other ugliness. > - vgaarb improvements from Alex Williamson plus the fix from Ville for the > vgacon->fbcon smooth transition "feature". > - Render pageflips on ivb/hsw to avoid stalls due to the ring switching > when only flipping on the blitter (Chris). > - Deadlock fixes around our flush_workqueue which crept back in - lockdep > isn't clever enough :( > - Shrinker recursion fix from Chris - this is the thing that blew the vma > patches from Ben I've taken out of 3.12. > - Fixup for the relocation refactoring. Also an igt testcase to make sure > we don't break this again. > - Pile of smaller fixups all over, shortlog has full details. > > Cheers, Daniel > > > The following changes since commit f33bcab9e816c5bf56b74c3007790f2a256910eb: > > drm/radeon: support render nodes (2013-09-02 10:51:53 +1000) > > are available in the git repository at: > > git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-fixes-2013-09-06 > > for you to fetch changes up to cac6a5ae0118832936eb162ec4cedb30f2422bcc: > > drm/i915: try not to lose backlight CBLV precision (2013-09-06 09:41:20 +0200) > > ---------------------------------------------------------------- > Alex Williamson (3): > vgaarb: Don't disable resources that are not owned > vgaarb: Fix VGA decodes changes > i915: Update VGA arbiter support for newer devices > > Chris Wilson (9): > drm/i915: Adjust available RPS information through sysfs for vlv > drm/i915: Apply the force-detect VGA w/a to Valleyview > drm/i915: Report requested frequency alongside current frequency in debugfs > drm/i915: Embed the ring->private within the struct intel_ring_buffer > drm/i915: Use RCS flips on Ivybridge+ > drm/i915: Pin pages whilst mapping the dma-buf > drm/i915: Hold an object reference whilst we shrink it > drm/i915: Skip stolen region initialisation if none is reserved > drm/i915: Confine page flips to BCS on Valleyview > > Damien Lespiau (1): > drm/i915: Don't call sg_free_table() if sg_alloc_table() fails > > Daniel Vetter (6): > drm/i915: tune down hangcheck noise > drm/i915: fix up the relocate_entry refactoring > drm/i915: fix hpd work vs. flush_work in the pageflip code deadlock > drm/i915: handle sdvo input pixel multiplier correctly again > drm/i915: fix i9xx_crtc_clock_get for multiplied pixels > drm/i915: fix gpu hang vs. flip stall deadlocks > > Imre Deak (1): > drm/i915: fix lvds/dp panel fitter setting > > Jani Nikula (1): > drm/i915: try not to lose backlight CBLV precision > > Jesse Barnes (2): > drm/i915: split PCI IDs out into i915_drm.h v4 > x86: add early quirk for reserving Intel graphics stolen memory v5 > > Joe Perches (1): > i915_gem: Convert kmem_cache_alloc(...GFP_ZERO) to kmem_cache_zalloc > > Mika Kuoppala (2): > drm/i915: Don't mask EI UP interrupt on IVB|SNB > drm/i915: sanitize forcewake registers on reset > > Paulo Zanoni (1): > drm/i915: enable trickle feed on Haswell > > Ville Syrjälä (1): > drm/i915: Fix pipe config warnings when dealing with LVDS fixed mode > > arch/x86/kernel/early-quirks.c | 154 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_debugfs.c | 11 +- > drivers/gpu/drm/i915/i915_dma.c | 9 +- > drivers/gpu/drm/i915/i915_drv.c | 164 +++++----------------- > drivers/gpu/drm/i915/i915_drv.h | 7 + > drivers/gpu/drm/i915/i915_gem.c | 48 +++++-- > drivers/gpu/drm/i915/i915_gem_dmabuf.c | 41 +++--- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 + > drivers/gpu/drm/i915/i915_gem_stolen.c | 3 + > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_irq.c | 23 +++- > drivers/gpu/drm/i915/i915_reg.h | 34 +++-- > drivers/gpu/drm/i915/i915_sysfs.c | 36 ++++- > drivers/gpu/drm/i915/intel_crt.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 78 +++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 2 +- > drivers/gpu/drm/i915/intel_lvds.c | 8 +- > drivers/gpu/drm/i915/intel_opregion.c | 2 +- > drivers/gpu/drm/i915/intel_panel.c | 14 +- > drivers/gpu/drm/i915/intel_pm.c | 14 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 99 ++++---------- > drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +- > drivers/gpu/drm/i915/intel_sdvo.c | 17 +-- > drivers/gpu/drm/i915/intel_sprite.c | 7 +- > drivers/gpu/drm/i915/intel_uncore.c | 9 +- > drivers/gpu/vga/vgaarb.c | 51 +++---- > include/drm/i915_drm.h | 34 +++++ > include/drm/i915_pciids.h | 211 +++++++++++++++++++++++++++++ > include/linux/vgaarb.h | 7 + > 29 files changed, 762 insertions(+), 334 deletions(-) > create mode 100644 include/drm/i915_pciids.h > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch

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[PATCH] radeon: pad CS to 8 DW
by Alex Deucher 06 Sep '13

06 Sep '13

Aligns the IB to 8 DWs. The aligns the IB to the CP fetch size. r6xx also require at least 4 DW alignment to avoid a hw bug. Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- radeon/radeon_cs_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index b963140..b87c6b1 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs) unsigned i; int r; + while (cs->cdw & 7) + radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000); + #if CS_BOF_DUMP cs_gem_dump_bof(cs); #endif -- 1.8.3.1

1 0

[libdrm] Stereo 3D
by Damien Lespiau 06 Sep '13

06 Sep '13

libdrm's support for: http://lists.freedesktop.org/archives/dri-devel/2013-September/044885.html -- Damien

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dri-devel September 2013