dri-devel December 2014

dri-devel@lists.freedesktop.org

156 participants
1053 discussions

[PATCH 0/4] drm/msm: YUV suppport addition for MDP4 & MDP5
by Stephane Viau 08 Dec '14

08 Dec '14

Hi, So this set of patches adds YUV support for MDP4 and MDP5. This only concerns the public planes (using ViG pipes). The fun part was to rebase things on top of atomic but things worked out fine. I was able to test this for MDP5 on a 8084 target. I cannot say the same for MDP4 for which I don't have a build based on atomic yet. The change is pretty similar to MDP5 though. Rgds, Stephane. Beeresh Gopal (1): drm/msm/mdp4: add YUV format support Stephane Viau (3): drm/msm/mdp: add … [View More]

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[Bug 89331] Radeon 8670M in DRI_PRIME shows garbage in scene
by bugzilla-daemon＠bugzilla.kernel.org 08 Dec '14

08 Dec '14

https://bugzilla.kernel.org/show_bug.cgi?id=89331 Alex Deucher <alexdeucher(a)gmail.com> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |alexdeucher(a)gmail.com --- Comment #1 from Alex Deucher <alexdeucher(a)gmail.com> --- This is a limitation of prime at the moment. There is no cross device synchronization support yet. See also https://… [View More]

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[Bug 89331] Radeon 8670M in DRI_PRIME shows garbage in scene
by bugzilla-daemon＠bugzilla.kernel.org 08 Dec '14

08 Dec '14

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[PATCH] gpu: drm: i915: intel_dp.c: Remove unused function
by Rickard Strandqvist 08 Dec '14

08 Dec '14

Remove the function intel_dp_set_drrs_state() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist(a)spectrumdigital.se> --- drivers/gpu/drm/i915/intel_dp.c | 89 -------------------------------------- drivers/gpu/drm/i915/intel_drv.h | 1 - 2 files changed, 90 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5ad45bf..… [View More]6df948b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4810,95 +4810,6 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, I915_READ(pp_div_reg)); } -void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_encoder *encoder; - struct intel_dp *intel_dp = NULL; - struct intel_crtc_config *config = NULL; - struct intel_crtc *intel_crtc = NULL; - struct intel_connector *intel_connector = dev_priv->drrs.connector; - u32 reg, val; - enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; - - if (refresh_rate <= 0) { - DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); - return; - } - - if (intel_connector == NULL) { - DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); - return; - } - - /* - * FIXME: This needs proper synchronization with psr state. But really - * hard to tell without seeing the user of this function of this code. - * Check locking and ordering once that lands. - */ - if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { - DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); - return; - } - - encoder = intel_attached_encoder(&intel_connector->base); - intel_dp = enc_to_intel_dp(&encoder->base); - intel_crtc = encoder->new_crtc; - - if (!intel_crtc) { - DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); - return; - } - - config = &intel_crtc->config; - - if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { - DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); - return; - } - - if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) - index = DRRS_LOW_RR; - - if (index == intel_dp->drrs_state.refresh_rate_type) { - DRM_DEBUG_KMS( - "DRRS requested for previously set RR...ignoring\n"); - return; - } - - if (!intel_crtc->active) { - DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); - return; - } - - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { - reg = PIPECONF(intel_crtc->config.cpu_transcoder); - val = I915_READ(reg); - if (index > DRRS_HIGH_RR) { - val |= PIPECONF_EDP_RR_MODE_SWITCH; - intel_dp_set_m_n(intel_crtc); - } else { - val &= ~PIPECONF_EDP_RR_MODE_SWITCH; - } - I915_WRITE(reg, val); - } - - /* - * mutex taken to ensure that there is no race between differnt - * drrs calls trying to update refresh rate. This scenario may occur - * in future when idleness detection based DRRS in kernel and - * possible calls from user space to set differnt RR are made. - */ - - mutex_lock(&intel_dp->drrs_state.mutex); - - intel_dp->drrs_state.refresh_rate_type = index; - - mutex_unlock(&intel_dp->drrs_state.mutex); - - DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); -} - static struct drm_display_mode * intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ba71522..6ad239d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -941,7 +941,6 @@ void intel_edp_panel_on(struct intel_dp *intel_dp); void intel_edp_panel_off(struct intel_dp *intel_dp); void intel_edp_psr_enable(struct intel_dp *intel_dp); void intel_edp_psr_disable(struct intel_dp *intel_dp); -void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); void intel_edp_psr_invalidate(struct drm_device *dev, unsigned frontbuffer_bits); void intel_edp_psr_flush(struct drm_device *dev, -- 1.7.10.4 [View Less]

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[PATCH] gpu: drm: i915: intel_dsi_pll.c: Remove unused function
by Rickard Strandqvist 08 Dec '14

08 Dec '14

Remove the function dsi_rr_formula() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist(a)spectrumdigital.se> --- drivers/gpu/drm/i915/intel_dsi_pll.c | 83 +--------------------------------- 1 file changed, 1 insertion(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index fa7a6ca..20086e8 100644 --- a/drivers/… [View More]gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -50,88 +50,7 @@ static const u32 lfsr_converts[] = { 71, 35 /* 91 - 92 */ }; -#ifdef DSI_CLK_FROM_RR - -static u32 dsi_rr_formula(const struct drm_display_mode *mode, - int pixel_format, int video_mode_format, - int lane_count, bool eotp) -{ - u32 bpp; - u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; - u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; - u32 bytes_per_line, bytes_per_frame; - u32 num_frames; - u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; - u32 dsi_bit_clock_hz; - u32 dsi_clk; - - switch (pixel_format) { - default: - case VID_MODE_FORMAT_RGB888: - case VID_MODE_FORMAT_RGB666_LOOSE: - bpp = 24; - break; - case VID_MODE_FORMAT_RGB666: - bpp = 18; - break; - case VID_MODE_FORMAT_RGB565: - bpp = 16; - break; - } - - hactive = mode->hdisplay; - vactive = mode->vdisplay; - hfp = mode->hsync_start - mode->hdisplay; - hsync = mode->hsync_end - mode->hsync_start; - hbp = mode->htotal - mode->hsync_end; - - vfp = mode->vsync_start - mode->vdisplay; - vsync = mode->vsync_end - mode->vsync_start; - vbp = mode->vtotal - mode->vsync_end; - - hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); - hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); - hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); - hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); - - bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + - DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + - hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + - hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + - hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; - - /* - * XXX: Need to accurately calculate LP to HS transition timeout and add - * it to bytes_per_line/bytes_per_frame. - */ - - if (eotp && video_mode_format == VIDEO_MODE_BURST) - bytes_per_line += DSI_EOTP_PACKET_SIZE; - - bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + - vactive * bytes_per_line + vfp * bytes_per_line; - - if (eotp && - (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || - video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) - bytes_per_frame += DSI_EOTP_PACKET_SIZE; - - num_frames = drm_mode_vrefresh(mode); - bytes_per_x_frames = num_frames * bytes_per_frame; - - bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; - - /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ - dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; - dsi_clk = dsi_bit_clock_hz / 1000; - - if (eotp && video_mode_format == VIDEO_MODE_BURST) - dsi_clk *= 2; - - return dsi_clk; -} - -#else +#ifndef DSI_CLK_FROM_RR /* Get DSI clock from pixel clock */ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) -- 1.7.10.4 [View Less]

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[PATCH] gpu: drm: i915: intel_dsi_cmd.c: Remove unused function
by Rickard Strandqvist 08 Dec '14

08 Dec '14

Remove the function dsi_hs_mode_enable() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist(a)spectrumdigital.se> --- drivers/gpu/drm/i915/intel_dsi_cmd.c | 21 --------------------- drivers/gpu/drm/i915/intel_dsi_cmd.h | 2 -- 2 files changed, 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index f4767fd..… [View More]

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[PATCH] gpu: drm: i915: intel_sideband.c: Remove some unused functions
by Rickard Strandqvist 08 Dec '14

08 Dec '14

Removes some functions that are not used anywhere: vlv_flisdsi_read() vlv_gps_core_write() vlv_gps_core_read() vlv_ccu_write() vlv_ccu_read() vlv_gpio_nc_read() This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist(a)spectrumdigital.se> --- drivers/gpu/drm/i915/i915_drv.h | 6 ----- drivers/gpu/drm/i915/intel_sideband.c | 44 --------------------------------- 2 files changed, 50 deletions(-) … [View More]diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 16a6f6d..d248957 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2849,23 +2849,17 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); -u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); -void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, enum intel_sbi_destination destination); void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, enum intel_sbi_destination destination); -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 01d841e..5939171 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -129,14 +129,6 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) return val; } -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) -{ - u32 val = 0; - vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, - SB_CRRDDA_NP, reg, &val); - return val; -} - void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) { vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, @@ -157,34 +149,6 @@ void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) SB_CRWRDA_NP, reg, &val); } -u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) -{ - u32 val = 0; - vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, - SB_CRRDDA_NP, reg, &val); - return val; -} - -void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) -{ - vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, - SB_CRWRDA_NP, reg, &val); -} - -u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) -{ - u32 val = 0; - vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, - SB_CRRDDA_NP, reg, &val); - return val; -} - -void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) -{ - vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, - SB_CRWRDA_NP, reg, &val); -} - u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) { u32 val = 0; @@ -267,14 +231,6 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, } } -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) -{ - u32 val = 0; - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, - reg, &val); - return val; -} - void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) { vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, -- 1.7.10.4 [View Less]

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[PATCH] add support for AM572x in the DDX
by Robert Nelson 08 Dec '14

08 Dec '14

Signed-off-by: Robert Nelson <robertcnelson(a)gmail.com> --- README | 1 + src/omap_driver.c | 3 +++ src/omap_driver.h | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/README b/README index 059f258..d4afd89 100644 --- a/README +++ b/README @@ -9,6 +9,7 @@ the following chipsets: + OMAP4460 + OMAP5430 + OMAP5432 + + AM572x NOTE: this driver is work in progress.. you probably don't want to try diff --git a/src/omap_driver.c b/src/omap_driver.… [View More]

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[PATCH] drm/fb_helper: move deferred fb checking into restore mode (v2)
by Dave Airlie 08 Dec '14

08 Dec '14

From: Dave Airlie <airlied(a)redhat.com> On MST systems the monitors don't appear when we set the fb up, but plymouth opens the drm device and holds it open while they come up, when plymouth finishes and lastclose gets called we don't do the delayed fb probe, so the monitor never appears on the console. Fix this by moving the delayed checking into the mode restore. v2: Daniel suggested that ->delayed_hotplug is set under the mode_config mutex, so we should check it under that as … [View More]

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[Bug 86832] [dota2][si] freezes up to 3 seconds when many/big display effects happen
by bugzilla-daemon＠freedesktop.org 08 Dec '14

08 Dec '14

https://bugs.freedesktop.org/show_bug.cgi?id=86832 Bug ID: 86832 Summary: [dota2][si] freezes up to 3 seconds when many/big display effects happen Product: DRI Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: critical Priority: medium Component: DRM/Radeon Assignee: dri-devel(a)lists.freedesktop.org Reporter: … [View More]

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dri-devel December 2014