dri-devel June 2014

dri-devel@lists.freedesktop.org

183 participants
944 discussions

[PATCH v2 0/8] drm & drivers: kill drm_get_connector_name() and drm_get_encoder_name()
by Jani Nikula 04 Jun '14

04 Jun '14

Hi all, this is v2 of [1] to remove drm_get_connector_name() and drm_get_encoder_name(), adding patch 1 for imx in staging and making some dereferences less of an eye sore. This is based on Dave's drm-next branch. BR, Jani. [1] http://mid.gmane.org/cover.1401110921.git.jani.nikula@intel.com Jani Nikula (8): staging: imx-drm-core: replace drm_get_connector_name() with direct name field use drm/i915: replace drm_get_connector_name() with direct name field use drm/nouveau: replace drm_get_connector_name() with direct name field use drm/radeon: replace drm_get_connector_name() with direct name field use drm: replace drm_get_connector_name() with direct name field use drm/i915: replace drm_get_encoder_name() with direct name field use drm: replace drm_get_encoder_name() with direct name field use drm: drop drm_get_connector_name() and drm_get_encoder_name() drivers/gpu/drm/drm_crtc.c | 26 +++-------------------- drivers/gpu/drm/drm_crtc_helper.c | 8 ++++---- drivers/gpu/drm/drm_edid.c | 6 +++--- drivers/gpu/drm/drm_edid_load.c | 2 +- drivers/gpu/drm/drm_fb_helper.c | 6 +++--- drivers/gpu/drm/drm_probe_helper.c | 10 ++++----- drivers/gpu/drm/drm_sysfs.c | 6 +++--- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++--------------- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_fbdev.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++---- drivers/gpu/drm/i915/intel_tv.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/dac.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 3 ++- drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 3 +-- drivers/gpu/drm/nouveau/nouveau_connector.c | 8 ++++---- drivers/gpu/drm/nouveau/nv50_display.c | 2 +- drivers/gpu/drm/radeon/radeon_connectors.c | 19 ++++++++++------- drivers/gpu/drm/radeon/radeon_display.c | 2 +- drivers/staging/imx-drm/imx-drm-core.c | 2 +- include/drm/drm_crtc.h | 2 -- 30 files changed, 83 insertions(+), 100 deletions(-) -- 1.9.1

2 9

[pull] radeon drm-next-3.16
by Alex Deucher 04 Jun '14

04 Jun '14

Hi Dave, This is the first pull request for radeon for 3.16. Christian has a few other patches that depend on some fixes from 3.15 so I'll wait to send those out until you sort out the 3.15 merge. Highlights: - GPUVM opimtizations - HDMI audio cleanups - Deep color HDMI support - more bug fixes, cleanups The following changes since commit 182407a6ed5333fc37dd980a8de91a8f826a94f6: drm: add DP MST encoder type (2014-05-30 11:59:51 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-3.16 for you to fetch changes up to bc5b96414cf8fe1cf73f778144ed6e10cbd849b4: drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. (2014-06-02 18:37:35 -0400) ---------------------------------------------------------------- Alex Deucher (9): drm/radeon: add a i2c bus mutex vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled drm/radeon: fix typo in radeon_connector_is_dp12_capable() drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices drm/radeon/atom: fix dithering on certain panels drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi drm/radeon: use hw cts/n values for deep color drm/radeon: fix pll setup for hdmi deep color (v7) drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2) Christian König (10): drm/radeon: add large PTE support for NI, SI and CIK v5 drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2 drm/radeon: remove (pre|post)_page_flip callbacks drm/radeon: remove drm_vblank_get|put from pflip handling drm/radeon: split page flip and pending callback drm/radeon: separate vblank and pflip crtc handling drm/radeon: rework page flip handling v3 drm/radeon: add define for flags used in R600+ GTT drm/radeon: optimize SI VM handling drm/radeon: optimize CIK VM handling v2 Mario Kleiner (3): drm/radeon: Limit hdmi deep color bit depth to 12 bpc. drm/edid: Parse and handle HDMI deep color modes. drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. Michele CURTI (2): drm/radeon: use NULL instead of zero in object functions drm/radeon: use NULL instead of zero in clearstate headers Rafał Miłecki (4): drm/radeon/hdmi: use separated file for DCE 3.1/3.2 code drm/radeon/hdmi: DCE3: clean ACR control drm/radeon/hdmi: DCE2: update setmode drm/radeon/hdmi: DCE2: simplify audio workaround Émeric MASCHINO (1): radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770 drivers/gpu/drm/drm_edid.c | 118 +++++++++- drivers/gpu/drm/radeon/Makefile | 2 +- drivers/gpu/drm/radeon/atombios_crtc.c | 89 +++++--- drivers/gpu/drm/radeon/atombios_dp.c | 35 ++- drivers/gpu/drm/radeon/atombios_encoders.c | 5 +- drivers/gpu/drm/radeon/atombios_i2c.c | 17 +- drivers/gpu/drm/radeon/cik.c | 17 +- drivers/gpu/drm/radeon/cik_sdma.c | 21 +- drivers/gpu/drm/radeon/cikd.h | 1 + drivers/gpu/drm/radeon/clearstate_cayman.h | 8 +- drivers/gpu/drm/radeon/clearstate_ci.h | 4 +- drivers/gpu/drm/radeon/clearstate_si.h | 4 +- drivers/gpu/drm/radeon/dce3_1_afmt.c | 244 +++++++++++++++++++++ drivers/gpu/drm/radeon/evergreen.c | 60 ++--- drivers/gpu/drm/radeon/evergreen_hdmi.c | 48 +++- drivers/gpu/drm/radeon/evergreend.h | 3 +- drivers/gpu/drm/radeon/ni.c | 3 + drivers/gpu/drm/radeon/nid.h | 1 + drivers/gpu/drm/radeon/r100.c | 55 ++--- drivers/gpu/drm/radeon/r600.c | 4 +- drivers/gpu/drm/radeon/r600_hdmi.c | 341 +++++++++-------------------- drivers/gpu/drm/radeon/r600d.h | 17 ++ drivers/gpu/drm/radeon/radeon.h | 33 ++- drivers/gpu/drm/radeon/radeon_agp.c | 3 - drivers/gpu/drm/radeon/radeon_asic.c | 68 ++---- drivers/gpu/drm/radeon/radeon_asic.h | 28 ++- drivers/gpu/drm/radeon/radeon_connectors.c | 27 ++- drivers/gpu/drm/radeon/radeon_display.c | 280 +++++++++++++---------- drivers/gpu/drm/radeon/radeon_i2c.c | 9 + drivers/gpu/drm/radeon/radeon_mode.h | 6 +- drivers/gpu/drm/radeon/radeon_object.c | 2 +- drivers/gpu/drm/radeon/radeon_object.h | 2 +- drivers/gpu/drm/radeon/radeon_vm.c | 95 +++++++- drivers/gpu/drm/radeon/rs600.c | 35 +-- drivers/gpu/drm/radeon/rv770.c | 10 +- drivers/gpu/drm/radeon/si.c | 18 +- drivers/gpu/drm/radeon/si_dma.c | 20 +- drivers/gpu/drm/radeon/sid.h | 1 + drivers/gpu/vga/vga_switcheroo.c | 3 +- include/drm/drm_edid.h | 5 + 40 files changed, 1135 insertions(+), 607 deletions(-) create mode 100644 drivers/gpu/drm/radeon/dce3_1_afmt.c

4 5

[PATCH v2 0/5] Move IPUv3 core out of staging, add CSI support
by Philipp Zabel 04 Jun '14

04 Jun '14

Hi, This is a rebased version of the earlier RFC series. It is mostly about the first patch, which moves the IPUv3 core code (drivers/staging/imx-drm/ipu-v3) to drivers/gpu. host1x, which serves a similar purpose, already sits there. I'd like to move the IPUv3 core code out of staging so that we can start submitting V4L2 code for video capture and scaling / colorspace conversion. The other four patches add necessary preparations for CSI and SMFC handling. These are used by the V4L2 CSI & capture drivers. This series is based on the current staging-next tree, it is otherwise nearly unchanged. I hope we can get this move in before the approaching merge window so that we have a base for submitting the CSI V4L2 patches in the following round. regards Philipp --- Changes since RFC: - Rebased onto current staging-next - Streamlined destaging patch a bit --- Philipp Zabel (5): gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging gpu: ipu-v3: Add SMFC code gpu: ipu-v3: Add ipu_idmac_get_current_buffer function gpu: ipu-v3: Add CSI and SMFC module enable wrappers gpu: ipu-v3: Register the CSI modules drivers/gpu/Makefile | 1 + drivers/gpu/ipu-v3/Kconfig | 7 ++ drivers/{staging/imx-drm => gpu}/ipu-v3/Makefile | 4 +- .../{staging/imx-drm => gpu}/ipu-v3/ipu-common.c | 82 ++++++++++++++++-- drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dc.c | 3 +- drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-di.c | 2 +- drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dmfc.c | 2 +- drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dp.c | 2 +- drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-prv.h | 8 +- drivers/gpu/ipu-v3/ipu-smfc.c | 97 ++++++++++++++++++++++ drivers/staging/imx-drm/Kconfig | 11 +-- drivers/staging/imx-drm/Makefile | 1 - drivers/staging/imx-drm/imx-hdmi.c | 2 +- drivers/staging/imx-drm/imx-tve.c | 2 +- drivers/staging/imx-drm/ipuv3-crtc.c | 2 +- drivers/staging/imx-drm/ipuv3-plane.c | 2 +- drivers/video/Kconfig | 1 + .../imx-drm/ipu-v3 => include/video}/imx-ipu-v3.h | 16 ++++ 18 files changed, 216 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/ipu-v3/Kconfig rename drivers/{staging/imx-drm => gpu}/ipu-v3/Makefile (51%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-common.c (94%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dc.c (99%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-di.c (99%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dmfc.c (99%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-dp.c (99%) rename drivers/{staging/imx-drm => gpu}/ipu-v3/ipu-prv.h (96%) create mode 100644 drivers/gpu/ipu-v3/ipu-smfc.c rename {drivers/staging/imx-drm/ipu-v3 => include/video}/imx-ipu-v3.h (95%) -- 2.0.0.rc2

4 10

[PATCH qxl.ko] Use surface_id 0 for primary surface on all monitors
by David Mansfield 04 Jun '14

04 Jun '14

spice-server and downstream code expect that the primary surface will always have surface_id = 0, while in reality, once allocated, the surface_id in qxl.ko is NEVER 0. In a dual head environment, all monitors render portions of the primary surface. However, when the monitor config events are generated and sent, the primary surface is only mapped to the correct identifier (i.e. 0) for the primary head (where crtc index is 0). The fix is to look at the "primary" flag in the bo and always use id 0, irrespective of which head is being configured. -- Thanks, David Mansfield Cobite, INC.

2 1

[Bug 76861] New: radeon: flickering horizontal stripes/lines
by bugzilla-daemon＠bugzilla.kernel.org 03 Jun '14

03 Jun '14

https://bugzilla.kernel.org/show_bug.cgi?id=76861 Bug ID: 76861 Summary: radeon: flickering horizontal stripes/lines Product: Drivers Version: 2.5 Kernel Version: 3.15-rc6 Hardware: i386 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: sven.dziadek(a)gmx.de CC: bugspam(a)moreofthesa.me.uk, deathsimple(a)vodafone.de Regression: No Created attachment 137301 --> https://bugzilla.kernel.org/attachment.cgi?id=137301&action=edit Video of my monitor Maybe duplicate of https://bugzilla.kernel.org/show_bug.cgi?id=75921 Recent DRI updates trigger a strange bug with my Radeon graphics card. Horizontal lines flicker. These stripes/ lines start from the right edge of the screen and have different lengths. All colors are visible. The amount of lines depends on the speed of diplay changes. In games/ console scrolling, there is a lot of them. If the pc is idle, I don't see any. Occurs also in tty1 on the text console. I appended a bad-quality video showing this issue. Sorry for the quality, but screencast programs don't record the problem, only the picture as it should be. With 3.15-rc1 it still works fine. In later Kernels, it is black without output. >From somewhere between 3.15-rc3 and 3.15-rc4 (when the black-screen-issue is fixed), theses stripes are visible. They are still there in latest commit: 1ee1ceafb572f1a925809168267a7962a4289de8 Graphics card is onboard: 01:05.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] RS880 [Radeon HD 4200] (prog-if 00 [VGA controller]) Monitor is attached over DVI. I haven't found any errors in syslog. Tell me if you need some more info. -- You are receiving this mail because: You are watching the assignee of the bug.

1 15

[PATCH] drm/radeon: rework page flip handling v4
by Alex Deucher 03 Jun '14

03 Jun '14

From: Christian König <christian.koenig(a)amd.com> Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by: Christian König <christian.koenig(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/radeon/radeon.h | 16 ++- drivers/gpu/drm/radeon/radeon_display.c | 239 ++++++++++++++++++-------------- drivers/gpu/drm/radeon/radeon_mode.h | 4 +- 3 files changed, 147 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 2eaa330..dd4da88 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -676,14 +676,16 @@ void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); * IRQS. */ -struct radeon_unpin_work { - struct work_struct work; - struct radeon_device *rdev; - int crtc_id; - struct radeon_fence *fence; +struct radeon_flip_work { + struct work_struct flip_work; + struct work_struct unpin_work; + struct radeon_device *rdev; + int crtc_id; + struct drm_framebuffer *fb; struct drm_pending_vblank_event *event; - struct radeon_bo *old_rbo; - u64 new_crtc_base; + struct radeon_bo *old_rbo; + struct radeon_bo *new_rbo; + struct radeon_fence *fence; }; struct r500_irq_stat_regs { diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 88e3cbe..d96d1ca 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -249,16 +249,21 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); drm_crtc_cleanup(crtc); + destroy_workqueue(radeon_crtc->flip_queue); kfree(radeon_crtc); } -/* - * Handle unpin events outside the interrupt handler proper. +/** + * radeon_unpin_work_func - unpin old buffer object + * + * @__work - kernel work item + * + * Unpin the old frame buffer object outside of the interrupt handler */ static void radeon_unpin_work_func(struct work_struct *__work) { - struct radeon_unpin_work *work = - container_of(__work, struct radeon_unpin_work, work); + struct radeon_flip_work *work = + container_of(__work, struct radeon_flip_work, unpin_work); int r; /* unpin of the old buffer */ @@ -279,30 +284,19 @@ static void radeon_unpin_work_func(struct work_struct *__work) void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) { struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; - struct radeon_unpin_work *work; + struct radeon_flip_work *work; unsigned long flags; u32 update_pending; int vpos, hpos; spin_lock_irqsave(&rdev->ddev->event_lock, flags); - work = radeon_crtc->unpin_work; - if (work == NULL || - (work->fence && !radeon_fence_signaled(work->fence))) { + work = radeon_crtc->flip_work; + if (work == NULL) { spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); return; } - /* New pageflip, or just completion of a previous one? */ - if (!radeon_crtc->deferred_flip_completion) { - /* do the flip (mmio) */ - radeon_page_flip(rdev, crtc_id, work->new_crtc_base); - update_pending = radeon_page_flip_pending(rdev, crtc_id); - } else { - /* This is just a completion of a flip queued in crtc - * at last invocation. Make sure we go directly to - * completion routine. - */ - update_pending = 0; - } + + update_pending = radeon_page_flip_pending(rdev, crtc_id); /* Has the pageflip already completed in crtc, or is it certain * to complete in this vblank? @@ -320,19 +314,9 @@ void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) */ update_pending = 0; } - if (update_pending) { - /* crtc didn't flip in this target vblank interval, - * but flip is pending in crtc. It will complete it - * in next vblank interval, so complete the flip at - * next vblank irq. - */ - radeon_crtc->deferred_flip_completion = 1; - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); - return; - } else { - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + if (!update_pending) radeon_crtc_handle_flip(rdev, crtc_id); - } } /** @@ -346,7 +330,7 @@ void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) { struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; - struct radeon_unpin_work *work; + struct radeon_flip_work *work; unsigned long flags; /* this can happen at init */ @@ -354,15 +338,14 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) return; spin_lock_irqsave(&rdev->ddev->event_lock, flags); - work = radeon_crtc->unpin_work; + work = radeon_crtc->flip_work; if (work == NULL) { spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); return; } - /* Pageflip (will be) certainly completed in this vblank. Clean up. */ - radeon_crtc->unpin_work = NULL; - radeon_crtc->deferred_flip_completion = 0; + /* Pageflip completed. Clean up. */ + radeon_crtc->flip_work = NULL; /* wakeup userspace */ if (work->event) @@ -372,83 +355,69 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) radeon_fence_unref(&work->fence); radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id); - schedule_work(&work->work); + queue_work(radeon_crtc->flip_queue, &work->unpin_work); } -static int radeon_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) +/** + * radeon_flip_work_func - page flip framebuffer + * + * @work - kernel work item + * + * Wait for the buffer object to become idle and do the actual page flip + */ +static void radeon_flip_work_func(struct work_struct *__work) { - struct drm_device *dev = crtc->dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - struct radeon_framebuffer *old_radeon_fb; - struct radeon_framebuffer *new_radeon_fb; - struct drm_gem_object *obj; - struct radeon_bo *rbo; - struct radeon_unpin_work *work; - unsigned long flags; - u32 tiling_flags, pitch_pixels; - u64 base; - int r; + struct radeon_flip_work *work = + container_of(__work, struct radeon_flip_work, flip_work); + struct radeon_device *rdev = work->rdev; + struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; - work = kzalloc(sizeof *work, GFP_KERNEL); - if (work == NULL) - return -ENOMEM; + struct drm_crtc *crtc = &radeon_crtc->base; + struct drm_framebuffer *fb = work->fb; - work->event = event; - work->rdev = rdev; - work->crtc_id = radeon_crtc->crtc_id; - old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); - new_radeon_fb = to_radeon_framebuffer(fb); - /* schedule unpin of the old buffer */ - obj = old_radeon_fb->obj; - /* take a reference to the old object */ - drm_gem_object_reference(obj); - rbo = gem_to_radeon_bo(obj); - work->old_rbo = rbo; - obj = new_radeon_fb->obj; - rbo = gem_to_radeon_bo(obj); + uint32_t tiling_flags, pitch_pixels; + uint64_t base; - spin_lock(&rbo->tbo.bdev->fence_lock); - if (rbo->tbo.sync_obj) - work->fence = radeon_fence_ref(rbo->tbo.sync_obj); - spin_unlock(&rbo->tbo.bdev->fence_lock); + unsigned long flags; + int r; - INIT_WORK(&work->work, radeon_unpin_work_func); + down_read(&rdev->exclusive_lock); + while (work->fence) { + r = radeon_fence_wait(work->fence, false); + if (r == -EDEADLK) { + up_read(&rdev->exclusive_lock); + r = radeon_gpu_reset(rdev); + down_read(&rdev->exclusive_lock); + } - /* We borrow the event spin lock for protecting unpin_work */ - spin_lock_irqsave(&dev->event_lock, flags); - if (radeon_crtc->unpin_work) { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - r = -EBUSY; - goto unlock_free; + if (r) { + DRM_ERROR("failed to wait on page flip fence (%d)!\n", + r); + goto cleanup; + } else + radeon_fence_unref(&work->fence); } - radeon_crtc->unpin_work = work; - radeon_crtc->deferred_flip_completion = 0; - spin_unlock_irqrestore(&dev->event_lock, flags); /* pin the new buffer */ DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", - work->old_rbo, rbo); + work->old_rbo, work->new_rbo); - r = radeon_bo_reserve(rbo, false); + r = radeon_bo_reserve(work->new_rbo, false); if (unlikely(r != 0)) { DRM_ERROR("failed to reserve new rbo buffer before flip\n"); - goto pflip_cleanup; + goto cleanup; } /* Only 27 bit offset for legacy CRTC */ - r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, + r = radeon_bo_pin_restricted(work->new_rbo, RADEON_GEM_DOMAIN_VRAM, ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); if (unlikely(r != 0)) { - radeon_bo_unreserve(rbo); + radeon_bo_unreserve(work->new_rbo); r = -EINVAL; DRM_ERROR("failed to pin new rbo buffer before flip\n"); - goto pflip_cleanup; + goto cleanup; } - radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); - radeon_bo_unreserve(rbo); + radeon_bo_get_tiling_flags(work->new_rbo, &tiling_flags, NULL); + radeon_bo_unreserve(work->new_rbo); if (!ASIC_IS_AVIVO(rdev)) { /* crtc offset is from display base addr not FB location */ @@ -486,9 +455,8 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, base &= ~7; } - spin_lock_irqsave(&dev->event_lock, flags); - work->new_crtc_base = base; - spin_unlock_irqrestore(&dev->event_lock, flags); + /* We borrow the event spin lock for protecting flip_work */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); /* update crtc fb */ crtc->primary->fb = fb; @@ -496,18 +464,82 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, /* set the proper interrupt */ radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); - return 0; + /* do the flip (mmio) */ + radeon_page_flip(rdev, radeon_crtc->crtc_id, base); + + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + up_read(&rdev->exclusive_lock); + + return; -pflip_cleanup: - spin_lock_irqsave(&dev->event_lock, flags); - radeon_crtc->unpin_work = NULL; -unlock_free: - spin_unlock_irqrestore(&dev->event_lock, flags); - drm_gem_object_unreference_unlocked(old_radeon_fb->obj); +cleanup: + drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); radeon_fence_unref(&work->fence); kfree(work); + up_read(&rdev->exclusive_lock); +} + +static int radeon_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct radeon_framebuffer *old_radeon_fb; + struct radeon_framebuffer *new_radeon_fb; + struct drm_gem_object *obj; + struct radeon_flip_work *work; + unsigned long flags; + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (work == NULL) + return -ENOMEM; + + INIT_WORK(&work->flip_work, radeon_flip_work_func); + INIT_WORK(&work->unpin_work, radeon_unpin_work_func); + + work->rdev = rdev; + work->crtc_id = radeon_crtc->crtc_id; + work->fb = fb; + work->event = event; + + /* schedule unpin of the old buffer */ + old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); + obj = old_radeon_fb->obj; + + /* take a reference to the old object */ + drm_gem_object_reference(obj); + work->old_rbo = gem_to_radeon_bo(obj); + + new_radeon_fb = to_radeon_framebuffer(fb); + obj = new_radeon_fb->obj; + work->new_rbo = gem_to_radeon_bo(obj); + + spin_lock(&work->new_rbo->tbo.bdev->fence_lock); + if (work->new_rbo->tbo.sync_obj) + work->fence = radeon_fence_ref(work->new_rbo->tbo.sync_obj); + spin_unlock(&work->new_rbo->tbo.bdev->fence_lock); + + /* We borrow the event spin lock for protecting flip_work */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); - return r; + if (radeon_crtc->flip_work) { + DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); + radeon_fence_unref(&work->fence); + kfree(work); + return -EBUSY; + } + radeon_crtc->flip_work = work; + + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + + queue_work(radeon_crtc->flip_queue, &work->flip_work); + + return 0; } static int @@ -577,6 +609,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index) drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); radeon_crtc->crtc_id = index; + radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); rdev->mode_info.crtcs[index] = radeon_crtc; if (rdev->family >= CHIP_BONAIRE) { diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 718be1a..ea72ad8 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -325,8 +325,8 @@ struct radeon_crtc { struct drm_display_mode native_mode; int pll_id; /* page flipping */ - struct radeon_unpin_work *unpin_work; - int deferred_flip_completion; + struct workqueue_struct *flip_queue; + struct radeon_flip_work *flip_work; /* pll sharing */ struct radeon_atom_ss ss; bool ss_enabled; -- 1.8.3.1

1 0

[PATCH] drm/radeon: use lower_32_bits where appropriated
by Christian König 03 Jun '14

03 Jun '14

From: Christian König <christian.koenig(a)amd.com> Replace occurrences of "v & 0xffffffff" with lower_32_bits(v) when it's next to an upper_32_bits(v). Also remove unnecessary "upper_32_bits(v) & 0xffffffff" code snippets. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/radeon/cik.c | 4 ++-- drivers/gpu/drm/radeon/cik_sdma.c | 26 +++++++++++++------------- drivers/gpu/drm/radeon/ni.c | 2 +- drivers/gpu/drm/radeon/r600.c | 8 ++++---- drivers/gpu/drm/radeon/si.c | 4 ++-- drivers/gpu/drm/radeon/si_dma.c | 8 ++++---- drivers/gpu/drm/radeon/uvd_v2_2.c | 2 +- 7 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index a518140..d1639ea 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3631,7 +3631,7 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); return true; @@ -3750,7 +3750,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write(ring, next_rptr); } diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index 3c2407b..377e9ee 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c @@ -141,7 +141,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, next_rptr += 4; radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write(ring, 1); /* number of DWs to follow */ radeon_ring_write(ring, next_rptr); } @@ -151,7 +151,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ - radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); radeon_ring_write(ring, ib->length_dw); } @@ -203,8 +203,8 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, /* write the fence */ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); - radeon_ring_write(ring, addr & 0xffffffff); - radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); + radeon_ring_write(ring, upper_32_bits(addr)); radeon_ring_write(ring, fence->seq); /* generate an interrupt */ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); @@ -233,7 +233,7 @@ bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); radeon_ring_write(ring, addr & 0xfffffff8); - radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(addr)); return true; } @@ -551,10 +551,10 @@ int cik_copy_dma(struct radeon_device *rdev, radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); radeon_ring_write(ring, cur_size_in_bytes); radeon_ring_write(ring, 0); /* src/dst endian swap */ - radeon_ring_write(ring, src_offset & 0xffffffff); - radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff); - radeon_ring_write(ring, dst_offset & 0xffffffff); - radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(src_offset)); + radeon_ring_write(ring, upper_32_bits(src_offset)); + radeon_ring_write(ring, lower_32_bits(dst_offset)); + radeon_ring_write(ring, upper_32_bits(dst_offset)); src_offset += cur_size_in_bytes; dst_offset += cur_size_in_bytes; } @@ -604,7 +604,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev, } radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); - radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); radeon_ring_write(ring, 1); /* number of DWs to follow */ radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_unlock_commit(rdev, ring); @@ -659,7 +659,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; - ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff; + ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr); ib.ptr[3] = 1; ib.ptr[4] = 0xDEADBEEF; ib.length_dw = 5; @@ -751,9 +751,9 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); ib->ptr[ib->length_dw++] = bytes; ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ - ib->ptr[ib->length_dw++] = src & 0xffffffff; + ib->ptr[ib->length_dw++] = lower_32_bits(src); ib->ptr[ib->length_dw++] = upper_32_bits(src); - ib->ptr[ib->length_dw++] = pe & 0xffffffff; + ib->ptr[ib->length_dw++] = lower_32_bits(pe); ib->ptr[ib->length_dw++] = upper_32_bits(pe); pe += bytes; diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 1d3209f..8c3fbb1 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -1346,7 +1346,7 @@ void cayman_fence_ring_emit(struct radeon_device *rdev, /* EVENT_WRITE_EOP - flush caches, send int */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write(ring, fence->seq); radeon_ring_write(ring, 0); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 436e550..2a130b7 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2724,7 +2724,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev, /* EVENT_WRITE_EOP - flush caches, send int */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write(ring, fence->seq); radeon_ring_write(ring, 0); @@ -2763,7 +2763,7 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev, sel |= PACKET3_SEM_WAIT_ON_SIGNAL; radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); return true; @@ -2824,9 +2824,9 @@ int r600_copy_cpdma(struct radeon_device *rdev, if (size_in_bytes == 0) tmp |= PACKET3_CP_DMA_CP_SYNC; radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); - radeon_ring_write(ring, src_offset & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write(ring, tmp); - radeon_ring_write(ring, dst_offset & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(dst_offset)); radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write(ring, cur_size_in_bytes); src_offset += cur_size_in_bytes; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 5c1c0c7..58711d9 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -3186,7 +3186,7 @@ void si_fence_ring_emit(struct radeon_device *rdev, /* EVENT_WRITE_EOP - flush caches, send int */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write(ring, fence->seq); radeon_ring_write(ring, 0); @@ -3219,7 +3219,7 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write(ring, (1 << 8)); radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); - radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write(ring, next_rptr); } diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c index 9521669..4b83f69 100644 --- a/drivers/gpu/drm/radeon/si_dma.c +++ b/drivers/gpu/drm/radeon/si_dma.c @@ -88,8 +88,8 @@ void si_dma_vm_set_page(struct radeon_device *rdev, ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, bytes); - ib->ptr[ib->length_dw++] = pe & 0xffffffff; - ib->ptr[ib->length_dw++] = src & 0xffffffff; + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = lower_32_bits(src); ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; @@ -220,8 +220,8 @@ int si_copy_dma(struct radeon_device *rdev, cur_size_in_bytes = 0xFFFFF; size_in_bytes -= cur_size_in_bytes; radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); - radeon_ring_write(ring, dst_offset & 0xffffffff); - radeon_ring_write(ring, src_offset & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(dst_offset)); + radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); src_offset += cur_size_in_bytes; diff --git a/drivers/gpu/drm/radeon/uvd_v2_2.c b/drivers/gpu/drm/radeon/uvd_v2_2.c index d177100..8bfdadd 100644 --- a/drivers/gpu/drm/radeon/uvd_v2_2.c +++ b/drivers/gpu/drm/radeon/uvd_v2_2.c @@ -45,7 +45,7 @@ void uvd_v2_2_fence_emit(struct radeon_device *rdev, radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); radeon_ring_write(ring, fence->seq); radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); - radeon_ring_write(ring, addr & 0xffffffff); + radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); radeon_ring_write(ring, upper_32_bits(addr) & 0xff); radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); -- 1.9.1

2 1

[Bug 74551] Unable to enable ACPI
by bugzilla-daemon＠bugzilla.kernel.org 03 Jun '14

03 Jun '14

https://bugzilla.kernel.org/show_bug.cgi?id=74551 --- Comment #9 from maxis11 <ya.maxis11(a)yandex.ru> --- (In reply to maxis11 from comment #8) > (In reply to Alex Deucher from comment #7) > > Can you bisect? > > All kernels 3.13.X ,3.14.X, 3.15-rc(1-8) are broken. 3.12 kernel started > work from commit b2b8225e61d9176a5d08218842ce03c7be035176 (drm/radeon: > 0x9649 is SUMO2 not SUMO) 3.12.7 - 3.12.20 working -- You are receiving this mail because: You are watching the assignee of the bug.

1 0

[Bug 74551] Unable to enable ACPI
by bugzilla-daemon＠bugzilla.kernel.org 03 Jun '14

03 Jun '14

https://bugzilla.kernel.org/show_bug.cgi?id=74551 --- Comment #8 from maxis11 <ya.maxis11(a)yandex.ru> --- (In reply to Alex Deucher from comment #7) > Can you bisect? All kernels 3.13.X ,3.14.X, 3.15-rc(1-8) are broken. 3.12 kernel started work from commit b2b8225e61d9176a5d08218842ce03c7be035176 (drm/radeon: 0x9649 is SUMO2 not SUMO) -- You are receiving this mail because: You are watching the assignee of the bug.

1 0

[PATCH] drm/nouveau/vm: fix mapping of SG pages list
by Alexandre Courbot 03 Jun '14

03 Jun '14

SG pages lists (not to be confused with scatterlists) are a list of 4KB memory pages used to define a nouveau_mem. Mapping them to a VM that does not use 4KB apertures resulted in each subsequent 4KB physical page being mapped into a larger VM aperture, thus creating an incorrect, overlapping mapping. This patch fixes this issue by detecting when such mappings occur and by skipping the required number of pages in the list to ensure a correct linear mapping. Signed-off-by: Alexandre Courbot <acourbot(a)nvidia.com> --- Ben, how does this look? This issue has been highlighted by the GK20A RAM driver which makes use of nouveau_mem::pages to provide system memory. The mapping overlap resulted in rendering issues for buffers that were bigger than 1 big VM page. I believe this is the correct way to fix this, and this way of building nouveau_mem instances is not much used in the driver anyway, but you know better. :) drivers/gpu/drm/nouveau/core/subdev/vm/base.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c index 7dd680f..db35e8d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c @@ -152,13 +152,18 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, end = (pte + num); if (unlikely(end >= max)) end = max; - len = end - pte; + + /* + * Map pages >4KB one by one so we can fix the list pointer + * as to not map intermediate pages to the next PTE + */ + len = bits ? 1 : end - pte; vmm->map_sg(vma, pgt, mem, pte, len, list); num -= len; pte += len; - list += len; + list += len << bits; if (unlikely(end >= max)) { pde++; pte = 0; -- 2.0.0

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dri-devel June 2014