dri-devel August 2014

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[PATCH 2/6] drm/i915: Make intel_plane_restore() return an error
by sonika.jindal＠intel.com 05 Aug '14

05 Aug '14

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Propagate the error from intel_update_plane() up through intel_plane_restore() to the caller. This will be used for rollback purposes when setting properties fails. Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Reviewed-by: Imre Deak <imre.deak(a)intel.com> --- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index bd915f4..a2c369f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1084,7 +1084,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); void intel_flush_primary_plane(struct drm_i915_private *dev_priv, enum plane plane); -void intel_plane_restore(struct drm_plane *plane); +int intel_plane_restore(struct drm_plane *plane); void intel_plane_disable(struct drm_plane *plane); int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f4d10c4..6118262 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1218,18 +1218,18 @@ out_unlock: return ret; } -void intel_plane_restore(struct drm_plane *plane) +int intel_plane_restore(struct drm_plane *plane) { struct intel_plane *intel_plane = to_intel_plane(plane); if (!plane->crtc || !plane->fb) - return; + return 0; - intel_update_plane(plane, plane->crtc, plane->fb, - intel_plane->crtc_x, intel_plane->crtc_y, - intel_plane->crtc_w, intel_plane->crtc_h, - intel_plane->src_x, intel_plane->src_y, - intel_plane->src_w, intel_plane->src_h); + return intel_update_plane(plane, plane->crtc, plane->fb, + intel_plane->crtc_x, intel_plane->crtc_y, + intel_plane->crtc_w, intel_plane->crtc_h, + intel_plane->src_x, intel_plane->src_y, + intel_plane->src_w, intel_plane->src_h); } void intel_plane_disable(struct drm_plane *plane) -- 1.7.10.4

1 0

[PATCH 1/6] drm/i915: Add 180 degree sprite rotation support
by sonika.jindal＠intel.com 05 Aug '14

05 Aug '14

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> The sprite planes (in fact all display planes starting from gen4) support 180 degree rotation. Add the relevant low level bits to the sprite code to make use of that feature. The upper layers are not yet plugged in. v2: HSW handles the rotated buffer offset automagically v3: BDW also handles the rotated buffer offset automagically Testcase: igt/kms_rotation_crc Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Sagar Kamble <sagar.a.kamble(a)intel.com> Reviewed-by: Imre Deak <imre.deak(a)intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_sprite.c | 38 +++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dc13961..1ece0c3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4218,6 +4218,7 @@ enum punit_power_well { #define DVS_YUV_ORDER_UYVY (1<<16) #define DVS_YUV_ORDER_YVYU (2<<16) #define DVS_YUV_ORDER_VYUY (3<<16) +#define DVS_ROTATE_180 (1<<15) #define DVS_DEST_KEY (1<<2) #define DVS_TRICKLE_FEED_DISABLE (1<<14) #define DVS_TILED (1<<10) @@ -4288,6 +4289,7 @@ enum punit_power_well { #define SPRITE_YUV_ORDER_UYVY (1<<16) #define SPRITE_YUV_ORDER_YVYU (2<<16) #define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_ROTATE_180 (1<<15) #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) #define SPRITE_INT_GAMMA_ENABLE (1<<13) #define SPRITE_TILED (1<<10) @@ -4361,6 +4363,7 @@ enum punit_power_well { #define SP_YUV_ORDER_UYVY (1<<16) #define SP_YUV_ORDER_YVYU (2<<16) #define SP_YUV_ORDER_VYUY (3<<16) +#define SP_ROTATE_180 (1<<15) #define SP_TILED (1<<10) #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 28d185d..bd915f4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -447,6 +447,7 @@ struct intel_plane { unsigned int crtc_w, crtc_h; uint32_t src_x, src_y; uint32_t src_w, src_h; + unsigned int rotation; /* Since we need to change the watermarks before/after * enabling/disabling the planes, we need to store the parameters here diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index d34a569..f4d10c4 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -164,6 +164,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, sprctl &= ~SP_PIXFORMAT_MASK; sprctl &= ~SP_YUV_BYTE_ORDER_MASK; sprctl &= ~SP_TILED; + sprctl &= ~SP_ROTATE_180; switch (fb->pixel_format) { case DRM_FORMAT_YUYV: @@ -236,6 +237,14 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, fb->pitches[0]); linear_offset -= sprsurf_offset; + if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { + sprctl |= SP_ROTATE_180; + + x += src_w; + y += src_h; + linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; + } + atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); intel_update_primary_plane(intel_crtc); @@ -365,6 +374,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, sprctl &= ~SPRITE_RGB_ORDER_RGBX; sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; sprctl &= ~SPRITE_TILED; + sprctl &= ~SPRITE_ROTATE_180; switch (fb->pixel_format) { case DRM_FORMAT_XBGR8888: @@ -427,6 +437,18 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, pixel_size, fb->pitches[0]); linear_offset -= sprsurf_offset; + if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { + sprctl |= SPRITE_ROTATE_180; + + /* HSW and BDW does this automagically in hardware */ + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { + x += src_w; + y += src_h; + linear_offset += src_h * fb->pitches[0] + + src_w * pixel_size; + } + } + atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); intel_update_primary_plane(intel_crtc); @@ -572,6 +594,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, dvscntr &= ~DVS_RGB_ORDER_XBGR; dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; dvscntr &= ~DVS_TILED; + dvscntr &= ~DVS_ROTATE_180; switch (fb->pixel_format) { case DRM_FORMAT_XBGR8888: @@ -629,6 +652,14 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, pixel_size, fb->pitches[0]); linear_offset -= dvssurf_offset; + if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { + dvscntr |= DVS_ROTATE_180; + + x += src_w; + y += src_h; + linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; + } + atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); intel_update_primary_plane(intel_crtc); @@ -896,6 +927,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, max_scale = intel_plane->max_downscale << 16; min_scale = intel_plane->can_scale ? 1 : (1 << 16); + drm_rect_rotate(&src, fb->width << 16, fb->height << 16, + intel_plane->rotation); + hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); BUG_ON(hscale < 0); @@ -934,6 +968,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, drm_rect_width(&dst) * hscale - drm_rect_width(&src), drm_rect_height(&dst) * vscale - drm_rect_height(&src)); + drm_rect_rotate_inv(&src, fb->width << 16, fb->height << 16, + intel_plane->rotation); + /* sanity check to make sure the src viewport wasn't enlarged */ WARN_ON(src.x1 < (int) src_x || src.y1 < (int) src_y || @@ -1311,6 +1348,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) intel_plane->pipe = pipe; intel_plane->plane = plane; + intel_plane->rotation = BIT(DRM_ROTATE_0); possible_crtcs = (1 << pipe); ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, &intel_plane_funcs, -- 1.7.10.4

1 0

[PATCH v5] drm/nouveau: map pages using DMA API
by Alexandre Courbot 04 Aug '14

04 Aug '14

The DMA API is the recommended way to map pages no matter what the underlying bus is. Use the DMA functions for page mapping and remove currently existing wrappers. Signed-off-by: Alexandre Courbot <acourbot(a)nvidia.com> Cc: Daniel Vetter <daniel(a)ffwll.ch> --- Changes since v4: - Patch against the Nouveau tree instead of the kernel - Separated this patch from the rest of the series since it can be merged alone - Replaced all pci_map invokations with dma_map. As Daniel pointed out, using the PCI API is deprecated: Documentation/DMA-API-HOWTO.txt: "Note that the DMA API works with any bus independent of the underlying microprocessor architecture. You should use the DMA API rather than the bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the pci_map_*() interfaces." - As a result, removed the page mapping wrappers which have become unneeded. drm/nouveau_bo.c | 22 ++++++++++++++++------ lib/core/os.h | 8 ++++---- nvkm/engine/device/base.c | 25 ------------------------- nvkm/include/core/device.h | 6 ------ nvkm/subdev/fb/nv50.c | 7 +++++-- nvkm/subdev/fb/nvc0.c | 7 +++++-- 6 files changed, 30 insertions(+), 45 deletions(-) diff --git a/drm/nouveau_bo.c b/drm/nouveau_bo.c index 4db886f9f793..e4f2071c46c3 100644 --- a/drm/nouveau_bo.c +++ b/drm/nouveau_bo.c @@ -1340,6 +1340,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) struct nouveau_drm *drm; struct nouveau_device *device; struct drm_device *dev; + struct device *pdev; unsigned i; int r; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); @@ -1358,6 +1359,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) drm = nouveau_bdev(ttm->bdev); device = nv_device(drm->device); dev = drm->dev; + pdev = nv_device_base(device); #if __OS_HAS_AGP if (drm->agp.stat == ENABLED) { @@ -1377,17 +1379,22 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) } for (i = 0; i < ttm->num_pages; i++) { - ttm_dma->dma_address[i] = nv_device_map_page(device, - ttm->pages[i]); - if (!ttm_dma->dma_address[i]) { + dma_addr_t addr; + + addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + + if (dma_mapping_error(pdev, addr)) { while (--i) { - nv_device_unmap_page(device, - ttm_dma->dma_address[i]); + dma_unmap_page(pdev, ttm_dma->dma_address[i], + PAGE_SIZE, DMA_BIDIRECTIONAL); ttm_dma->dma_address[i] = 0; } ttm_pool_unpopulate(ttm); return -EFAULT; } + + ttm_dma->dma_address[i] = addr; } return 0; } @@ -1399,6 +1406,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) struct nouveau_drm *drm; struct nouveau_device *device; struct drm_device *dev; + struct device *pdev; unsigned i; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); @@ -1408,6 +1416,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) drm = nouveau_bdev(ttm->bdev); device = nv_device(drm->device); dev = drm->dev; + pdev = nv_device_base(device); #if __OS_HAS_AGP if (drm->agp.stat == ENABLED) { @@ -1425,7 +1434,8 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) for (i = 0; i < ttm->num_pages; i++) { if (ttm_dma->dma_address[i]) { - nv_device_unmap_page(device, ttm_dma->dma_address[i]); + dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, + DMA_BIDIRECTIONAL); } } diff --git a/lib/core/os.h b/lib/core/os.h index 5f4f04fbff3d..596e083ffb36 100644 --- a/lib/core/os.h +++ b/lib/core/os.h @@ -644,7 +644,7 @@ dma_free_coherent(struct device *dev, size_t sz, void *vaddr, dma_addr_t bus) *****************************************************************************/ #include <pciaccess.h> -#define PCI_DMA_BIDIRECTIONAL 1 +#define DMA_BIDIRECTIONAL 1 #define PCI_CAP_ID_AGP 0x02 @@ -688,7 +688,7 @@ pci_resource_len(struct pci_dev *pdev, int bar) } static inline dma_addr_t -pci_map_page(struct pci_dev *pdev, struct page *page, int offset, +dma_map_page(struct device *pdev, struct page *page, int offset, int length, unsigned flags) { return 0; @@ -696,13 +696,13 @@ pci_map_page(struct pci_dev *pdev, struct page *page, int offset, static inline bool -pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t addr) +dma_mapping_error(struct device *pdev, dma_addr_t addr) { return true; } static inline void -pci_unmap_page(struct pci_dev *pdev, dma_addr_t addr, int size, unsigned flags) +dma_unmap_page(struct device *pdev, dma_addr_t addr, int size, unsigned flags) { } diff --git a/nvkm/engine/device/base.c b/nvkm/engine/device/base.c index 466dda2f7a3a..6c16dabe13b3 100644 --- a/nvkm/engine/device/base.c +++ b/nvkm/engine/device/base.c @@ -487,31 +487,6 @@ nv_device_resource_len(struct nouveau_device *device, unsigned int bar) } } -dma_addr_t -nv_device_map_page(struct nouveau_device *device, struct page *page) -{ - dma_addr_t ret; - - if (nv_device_is_pci(device)) { - ret = pci_map_page(device->pdev, page, 0, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(device->pdev, ret)) - ret = 0; - } else { - ret = page_to_phys(page); - } - - return ret; -} - -void -nv_device_unmap_page(struct nouveau_device *device, dma_addr_t addr) -{ - if (nv_device_is_pci(device)) - pci_unmap_page(device->pdev, addr, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); -} - int nv_device_get_irq(struct nouveau_device *device, bool stall) { diff --git a/nvkm/include/core/device.h b/nvkm/include/core/device.h index 9ce2ee9aa32e..03c039dcc61f 100644 --- a/nvkm/include/core/device.h +++ b/nvkm/include/core/device.h @@ -174,12 +174,6 @@ nv_device_resource_start(struct nouveau_device *device, unsigned int bar); resource_size_t nv_device_resource_len(struct nouveau_device *device, unsigned int bar); -dma_addr_t -nv_device_map_page(struct nouveau_device *device, struct page *page); - -void -nv_device_unmap_page(struct nouveau_device *device, dma_addr_t addr); - int nv_device_get_irq(struct nouveau_device *device, bool stall); diff --git a/nvkm/subdev/fb/nv50.c b/nvkm/subdev/fb/nv50.c index 1fc55c1e91a1..7d88e17fa927 100644 --- a/nvkm/subdev/fb/nv50.c +++ b/nvkm/subdev/fb/nv50.c @@ -250,7 +250,9 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (priv->r100c08_page) { - priv->r100c08 = nv_device_map_page(device, priv->r100c08_page); + priv->r100c08 = dma_map_page(nv_device_base(device), + priv->r100c08_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); if (!priv->r100c08) nv_warn(priv, "failed 0x100c08 page map\n"); } else { @@ -268,7 +270,8 @@ nv50_fb_dtor(struct nouveau_object *object) struct nv50_fb_priv *priv = (void *)object; if (priv->r100c08_page) { - nv_device_unmap_page(device, priv->r100c08); + dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(priv->r100c08_page); } diff --git a/nvkm/subdev/fb/nvc0.c b/nvkm/subdev/fb/nvc0.c index 0670ae33ee45..9f5f3ac8d4c6 100644 --- a/nvkm/subdev/fb/nvc0.c +++ b/nvkm/subdev/fb/nvc0.c @@ -70,7 +70,8 @@ nvc0_fb_dtor(struct nouveau_object *object) struct nvc0_fb_priv *priv = (void *)object; if (priv->r100c10_page) { - nv_device_unmap_page(device, priv->r100c10); + dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(priv->r100c10_page); } @@ -93,7 +94,9 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (priv->r100c10_page) { - priv->r100c10 = nv_device_map_page(device, priv->r100c10_page); + priv->r100c10 = dma_map_page(nv_device_base(device), + priv->r100c10_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); if (!priv->r100c10) return -EFAULT; } -- 2.0.3

3 2

[PATCH v2] drm/ttm: expose CPU address of DMA-allocated pages
by Alexandre Courbot 04 Aug '14

04 Aug '14

Pages allocated using the DMA API have a coherent memory mapping. Make this mapping visible to drivers so they can decide to use it instead of creating their own redundant one. Signed-off-by: Alexandre Courbot <acourbot(a)nvidia.com> Acked-by: David Airlie <airlied(a)linux.ie> --- Changes since v1: - Perform only one allocation for pages, CPU and DMA addresses - Added David's ack drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 2 ++ drivers/gpu/drm/ttm/ttm_tt.c | 13 ++++++++----- include/drm/ttm/ttm_bo_driver.h | 2 ++ 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c index fb8259f69839..0301fac5badd 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c @@ -847,6 +847,7 @@ static int ttm_dma_pool_get_pages(struct dma_pool *pool, if (count) { d_page = list_first_entry(&pool->free_list, struct dma_page, page_list); ttm->pages[index] = d_page->p; + ttm_dma->cpu_address[index] = d_page->vaddr; ttm_dma->dma_address[index] = d_page->dma; list_move_tail(&d_page->page_list, &ttm_dma->pages_list); r = 0; @@ -978,6 +979,7 @@ void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev) INIT_LIST_HEAD(&ttm_dma->pages_list); for (i = 0; i < ttm->num_pages; i++) { ttm->pages[i] = NULL; + ttm_dma->cpu_address[i] = 0; ttm_dma->dma_address[i] = 0; } diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 75f319090043..bf080abc86d1 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -55,9 +55,12 @@ static void ttm_tt_alloc_page_directory(struct ttm_tt *ttm) static void ttm_dma_tt_alloc_page_directory(struct ttm_dma_tt *ttm) { - ttm->ttm.pages = drm_calloc_large(ttm->ttm.num_pages, sizeof(void*)); - ttm->dma_address = drm_calloc_large(ttm->ttm.num_pages, - sizeof(*ttm->dma_address)); + ttm->ttm.pages = drm_calloc_large(ttm->ttm.num_pages, + sizeof(*ttm->ttm.pages) + + sizeof(*ttm->dma_address) + + sizeof(*ttm->cpu_address)); + ttm->cpu_address = (void *) (ttm->ttm.pages + ttm->ttm.num_pages); + ttm->dma_address = (void *) (ttm->cpu_address + ttm->ttm.num_pages); } #ifdef CONFIG_X86 @@ -228,7 +231,7 @@ int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev, INIT_LIST_HEAD(&ttm_dma->pages_list); ttm_dma_tt_alloc_page_directory(ttm_dma); - if (!ttm->pages || !ttm_dma->dma_address) { + if (!ttm->pages) { ttm_tt_destroy(ttm); pr_err("Failed allocating page table\n"); return -ENOMEM; @@ -243,7 +246,7 @@ void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma) drm_free_large(ttm->pages); ttm->pages = NULL; - drm_free_large(ttm_dma->dma_address); + ttm_dma->cpu_address = NULL; ttm_dma->dma_address = NULL; } EXPORT_SYMBOL(ttm_dma_tt_fini); diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 202f0a7171e8..1d9f0f1ff52d 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -133,6 +133,7 @@ struct ttm_tt { * struct ttm_dma_tt * * @ttm: Base ttm_tt struct. + * @cpu_address: The CPU address of the pages * @dma_address: The DMA (bus) addresses of the pages * @pages_list: used by some page allocation backend * @@ -142,6 +143,7 @@ struct ttm_tt { */ struct ttm_dma_tt { struct ttm_tt ttm; + void **cpu_address; dma_addr_t *dma_address; struct list_head pages_list; }; -- 2.0.3

2 1

[Bug 74250] New: [HAWAII][DPM] New Version 3.1 for ASIC_ProfilingInfo / ci_upload_dpm_level_enable_mask failed
by bugzilla-daemon＠freedesktop.org 04 Aug '14

04 Aug '14

https://bugs.freedesktop.org/show_bug.cgi?id=74250 Priority: medium Bug ID: 74250 Assignee: dri-devel(a)lists.freedesktop.org Summary: [HAWAII][DPM] New Version 3.1 for ASIC_ProfilingInfo / ci_upload_dpm_level_enable_mask failed Severity: normal Classification: Unclassified OS: Linux (All) Reporter: luziphermcleod(a)yahoo.ie Hardware: x86-64 (AMD64) Status: NEW Version: unspecified Component: DRM/Radeon Product: DRI Created attachment 93090 --> https://bugs.freedesktop.org/attachment.cgi?id=93090&action=edit dmesg WITHOUT the patch Observation: ============ System starts up fine (radeondrmfb high res text mode), but I get eight of the following error messages in dmesg: [drm:radeon_atom_get_leakage_vddc_based_on_leakage_params] *ERROR* Unknown table version 3, 1 With the patch from Bug 73420 ( https://bugs.freedesktop.org/attachment.cgi?id=93015 ) I don't get those messages, but one occurance of: [drm:ci_dpm_set_power_state] *ERROR* ci_upload_dpm_level_enable_mask failed Without the patch, I do NOT get the "ci_upload_dpm_level_enable_mask failed " message. Software Details: ===================== 0) Gentoo Linux 1) Kernel: drm-next (airlied's from http://cgit.freedesktop.org/~airlied/linux/?h=drm-next , commit ef64cf9d06049e4e9df661f3be60b217e476bee1) 2) libdrm: git 3) mesa: git 4) Xorg-server: 1.15.0 5) xf86-video-ati: git 6) glamor: git 7) llvm: 3.5svn (updated on 30.01.2014) 8) pixman: git (All git versions were updated on 30.01.2014) Hardware Details: ===================== Graphics Card: Hawaii XT, Sapphire Radeon R9 290X Tri-X OC (11226-00-50G) Graphics Chip: HAWAII 0x1002:0x67B0 0x174B:0xE285 Monitors: 3 (HP LP2475w via DVI, Samsung 214T via DVI, Samsung TV via HDMI) Processor: Core i7-965 (LGA 1366) Mainboard: Asus P6T Deluxe RAM: 6GB -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH] radeon: allow write_reloc with unaccounted buffers to cope with Mesa R200 bug
by Marek Olšák 04 Aug '14

04 Aug '14

From: Marek Olšák <marek.olsak(a)amd.com> --- I'm not really interested in studying the R200 driver to fix it. This has to suffice. radeon/radeon_cs_gem.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index b87c6b1..bcfa05b 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -178,6 +178,15 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs, uint32_t idx; unsigned i; + if (!boi->space_accounted) { + struct radeon_cs *rcs = (struct radeon_cs*)cs; + int r; + + radeon_cs_space_add_persistent_bo(rcs, bo, read_domain, write_domain); + r = radeon_cs_space_check(rcs); + if (r) + return r; + } assert(boi->space_accounted); /* check domains */ -- 1.9.1

2 2

[PATCH 1/4] drm/radeon: use packet2 for nop on hawaii with old firmware
by Andreas Boll 04 Aug '14

04 Aug '14

From: Alex Deucher <alexander.deucher(a)amd.com> Older firmware didn't support the new nop packet. v2 (Andreas Boll): - Drop usage of packet3 for new firmware Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> (v1) Signed-off-by: Andreas Boll <andreas.boll.dev(a)gmail.com> Cc: stable(a)vger.kernel.org --- drivers/gpu/drm/radeon/cik.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index c0ea661..e5985d5 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -7900,6 +7900,7 @@ restart_ih: static int cik_startup(struct radeon_device *rdev) { struct radeon_ring *ring; + u32 nop; int r; /* enable pcie gen2/3 link */ @@ -8033,9 +8034,15 @@ static int cik_startup(struct radeon_device *rdev) } cik_irq_set(rdev); + if (rdev->family == CHIP_HAWAII) { + nop = RADEON_CP_PACKET2; + } else { + nop = PACKET3(PACKET3_NOP, 0x3FFF); + } + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, - PACKET3(PACKET3_NOP, 0x3FFF)); + nop); if (r) return r; @@ -8043,7 +8050,7 @@ static int cik_startup(struct radeon_device *rdev) /* type-2 packets are deprecated on MEC, use type-3 instead */ ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, - PACKET3(PACKET3_NOP, 0x3FFF)); + nop); if (r) return r; ring->me = 1; /* first MEC */ @@ -8054,7 +8061,7 @@ static int cik_startup(struct radeon_device *rdev) /* type-2 packets are deprecated on MEC, use type-3 instead */ ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, - PACKET3(PACKET3_NOP, 0x3FFF)); + nop); if (r) return r; /* dGPU only have 1 MEC */ -- 2.0.1

2 4

[pull] drm/msm: msm-next for 3.17
by Rob Clark 04 Aug '14

04 Aug '14

Dave, This time around we have a mix of new hw enablement (mdp5 v1.3 / apq8084), plus devicetree and various upstream changes (mostly adapting to CCF vs downstream clk driver differences) for mdp4 / apq8064. With these drm/msm patches plus a few other small patchsets (from linaro qcom integration branch.. mostly stuff queued up for 3.17) we have the inforce ifc6410 board working, with gpu. Much nicer to work with than ancient vendor android branch :-) The following changes since commit c759606c96dc052373d4c36ea383595da46b04e9: Merge tag 'drm-intel-next-2014-07-25-merged' of git://anongit.freedesktop.org/drm-intel into drm-next (2014-08-04 17:57:34 +1000) are available in the git repository at: git://people.freedesktop.org/~robclark/linux msm-next for you to fetch changes up to a2fe6cdc03d7a9b0d048a7f32f9d8827e06c67fa: drm/msm/hdmi: fix HDMI_MUX_EN gpio request typo (2014-08-04 11:55:30 -0400) ---------------------------------------------------------------- Beeresh Gopal (2): drm/msm/hdmi: enable lpm-mux if it is present drm/msm/hdmi: fix HDMI_MUX_EN gpio request typo Hai Li (1): drm/msm: Implement msm drm fb_mmap callback function Rob Clark (9): drm/msm: fix double struct_mutex acquire drm/msm: DT support for 8960/8064 (v3) drm/msm: update generated headers drm/msm: hdmi phy 8960 phy pll drm/msm/mdp4: add mdp axi clk drm/msm: fix BUG_ON() in error cleanup path drm/msm: no mmu is only error if not using vram carveout drm/msm: use upstream iommu drm/msm: fix potential deadlock in gpu init Stephane Viau (2): drm/msm: activate iommu support drm/msm/mdp5: add support for MDP5 v1.3 Documentation/devicetree/bindings/drm/msm/gpu.txt | 52 +++ Documentation/devicetree/bindings/drm/msm/hdmi.txt | 46 +++ Documentation/devicetree/bindings/drm/msm/mdp.txt | 48 +++ drivers/gpu/drm/msm/Kconfig | 1 - drivers/gpu/drm/msm/adreno/a2xx.xml.h | 58 ++- drivers/gpu/drm/msm/adreno/a3xx.xml.h | 296 +++++++++++--- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 7 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.h | 5 + drivers/gpu/drm/msm/adreno/adreno_common.xml.h | 56 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 239 +++++++++++- drivers/gpu/drm/msm/dsi/dsi.xml.h | 4 +- drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 4 +- drivers/gpu/drm/msm/dsi/sfpb.xml.h | 4 +- drivers/gpu/drm/msm/hdmi/hdmi.c | 69 ++-- drivers/gpu/drm/msm/hdmi/hdmi.h | 1 + drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 109 +++++- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 23 +- drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 377 +++++++++++++++++- drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 4 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 4 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 25 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1 + drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 431 +++++++++++++-------- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 159 +++++++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 25 ++ drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 4 +- drivers/gpu/drm/msm/msm_drv.c | 52 ++- drivers/gpu/drm/msm/msm_fbdev.c | 45 ++- drivers/gpu/drm/msm/msm_gem.c | 15 +- drivers/gpu/drm/msm/msm_gpu.c | 12 +- drivers/gpu/drm/msm/msm_iommu.c | 31 +- drivers/gpu/drm/msm/msm_mmu.h | 8 +- 33 files changed, 1837 insertions(+), 392 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/msm/gpu.txt create mode 100644 Documentation/devicetree/bindings/drm/msm/hdmi.txt create mode 100644 Documentation/devicetree/bindings/drm/msm/mdp.txt

1 0

[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded
by bugzilla-daemon＠bugzilla.kernel.org 04 Aug '14

04 Aug '14

https://bugzilla.kernel.org/show_bug.cgi?id=81021 --- Comment #8 from Alex Deucher <alexdeucher(a)gmail.com> --- I'm not sure why you don't think you need a GPU driver installed. When the driver is installed it not only allows the GPU to dynamically adjust it clocks and voltages up for performance, but also enables low power states and turns off certain blocks when they are not in use, so overall, you'll probably save more power with the GPU driver loaded than just leaving the GPU in the state set up by the bios. -- You are receiving this mail because: You are watching the assignee of the bug.

1 0

Re: [PATCH 1/1] Documentation: drm: describing drm properties exposed by various drivers
by Ville Syrjälä 04 Aug '14

04 Aug '14

On Wed, Mar 12, 2014 at 12:25:06PM +0100, Laurent Pinchart wrote: > Hi Sagar, > > On Wednesday 12 March 2014 16:46:05 Sagar Arun Kamble wrote: > > On Mon, 2014-03-10 at 15:36 +0100, Laurent Pinchart wrote: > > > On Monday 10 March 2014 06:21:49 Daniel Vetter wrote: > > > > On Wed, Mar 5, 2014 at 11:56 AM, <sagar.a.kamble(a)intel.com> wrote: > > > > > +<table border="1" cellpadding="0" cellspacing="0" > > > > > > +<tbody> > > > > > +<tr style="font-weight: bold;" > > > > > > +<td valign="top" >Owner Module/Drivers</td> > > > > > +<td valign="top" >Group</td> > > > > > +<td valign="top" >Property Object</td> > > > > > +<td valign="top" >Property Name</td> > > > > > +<td valign="top" >Type</td> > > > > > +<td valign="top" >Property Values</td> > > > > > +<td valign="top" >Object attached</td> > > > > > +<td valign="top" >Description</td> > > > > > +</tr> > > > > > > > > In my opinion this is a horrible way to write property documentations > > > > - explicitly constructing html tables is error prone and really hard > > > > to read in the source. Imo docbook in general is rather horrible, > > > > which is way I write almost all my docs as kerneldoc ;-) > > > > > > > > I think a simple asciidoc/markdown would be much simpler, with a bit > > > > of free-form structure to group properties into relevant groups. > > > > Long-term we might even need to split it up into different spec files > > > > to keep a good overview. > > > > > > Docbook is indeed hard to read and write when it comes to such tables. > > > However I like having the properties documented in the DRM core > > > documentation. Maybe we could come up with a simpler text format that > > > would be transformed into docbook when compiling the documentation ? > > > > Does this mean we need to create comment block with "Doc: drm > > properties" style section in each driver where drm properties are > > instantiated. And then in drm.tmpl collect all these using !P escape > > sequence? > > How do create table out of these across all drivers? > > I don't have a strong preference here. Documenting properties in source code > comments would be fine, so would an external central documentation file in a > non Docbook format. For the record I'm personally fine with using Docbook as > in this patch :-) > > If we decide to go for property documentation inside the source code then I > believe we'll have to create our own format, as creating a properties table > from kerneldoc information extracted from comments is probably not possible. Can comeone pick up the ball here and figure out what needs to be done? The reason why I want a central place for the documentation is to force people to collaborate outside their own sandbox when adding properties. Whether that's docbook or some text file I don't care so much at this point. The fact that it's a central place should mandate that the patches changing it will go through dri-devel and so everyone should se them, and when adding new properties it would make the patch author more likely to look around a bit before adding another slighty incompatible version of the same property. If someone has a better suggestion how to encforce this I'm all ears. Of course this idea can still fail if our esteemed maintainer merges stuff without checking for violations of this policy. Dave, any thoughts on the subject? Either way I can tell you that I'm not very enthusiastic about reviewing any property patches until some kind of decision about this is reached, be it "docbook", "text", "plan c", or "fuck it, let the world burn!". -- Ville Syrjälä Intel OTC

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dri-devel August 2014