dri-devel September 2014

dri-devel@lists.freedesktop.org

173 participants
1045 discussions

[PATCH 9/9] drm/ttm: Sanity check mapping attributes on powerpc in ttm_io_prot()
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

On all current cache coherent powerpc processors, it is not legit to map system memory non-cachable. This will cause aliases with the linear mapping which can be fatal. The TTM should generally avoid it after Jerome placement patches but let's add a sanity check anyway to catch any possible remaining issue. Signed-off-by: Benjamin Herrenschmidt <benh(a)palm4.ozlabs.ibm.com> --- drivers/gpu/drm/ttm/ttm_bo_util.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index ef2ac3c..48095be 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -37,6 +37,9 @@ #include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/module.h> +#if defined(__powerpc__) +#include <asm/machdep.h> +#endif void ttm_bo_free_old_node(struct ttm_buffer_object *bo) { @@ -498,6 +501,20 @@ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp) tmp = pgprot_noncached(tmp); #endif +#if defined(__powerpc__) && !defined(CONFIG_NOT_COHERENT_CACHE) + /* + * Using a non-cachable mapping of system memory on + * cache coherent powerpc's can be fatal, let's make + * sure this doesn't happen and warn if it does. The + * only exception is powermac with AGP which has to + * take the risk. + */ + if (!machine_is(powermac) && + ((caching_flags & TTM_PL_FLAG_SYSTEM) || + (caching_flags & TTM_PL_FLAG_TT))) { + pr_err_once("TTM: Attempt to use a non-cached" + " mapping on RAM unsupported !\n"); + return tmp; } #endif #if defined(__ia64__) || defined(__arm__) || defined(__powerpc__)

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[git pull] drm fixes
by Dave Airlie 04 Sep '14

04 Sep '14

Hi Linus, just i915 and vmwgfx fixes, i915 contains a bunch of fixes for recent regressions in outputs, vmwgfx fixes a possible loop for ever and a bad return code. Dave. The following changes since commit 59753a805499f1ffbca4ac0a24b3dff67bf00001: Merge tag 'backlight-fixes-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight (2014-08-28 10:47:10 -0700) are available in the git repository at: git://people.freedesktop.org/~airlied/linux drm-fixes for you to fetch changes up to 3aacfda0ecd9040521fbfb4a2c53cd6bf77ae4ee: Merge tag 'drm-intel-fixes-2014-09-03' of git://anongit.freedesktop.org/drm-intel into drm-fixes (2014-09-04 11:20:00 +1000) ---------------------------------------------------------------- Dave Airlie (4): Merge tag 'drm-intel-fixes-2014-08-28' of git://anongit.freedesktop.org/drm-intel into drm-fixes drm/i915: handle G45/GM45 pulse detection connected state. Merge branch 'vmwgfx-fixes-3.17' of git://people.freedesktop.org/~thomash/linux into drm-fixes Merge tag 'drm-intel-fixes-2014-09-03' of git://anongit.freedesktop.org/drm-intel into drm-fixes Mathias Krause (1): drm/i915: Remove bogus __init annotation from DMI callbacks Paulo Zanoni (1): drm/i915: fix plane/cursor handling when runtime suspended Scot Doyle (2): drm/i915: Ignore VBT backlight presence check on Acer C720 (4005U) drm/i915: don't warn if backlight unexpectedly enabled Thomas Hellstrom (2): drm/vmwgfx: Fix an incorrect OOM return value drm/vmwgfx: Fix a potential infinite spin waiting for fifo idle Ville Syrjälä (2): drm/i915: Move intel_ddi_set_vc_payload_alloc(false) to haswell_crtc_disable() drm/i915: Fix lock dropping in intel_tv_detect() drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++--- drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 8 ++--- drivers/gpu/drm/i915/intel_tv.c | 10 ++++-- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 11 +++---- drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | 3 +- 9 files changed, 88 insertions(+), 39 deletions(-)

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[PATCH 6/9] drm/ttm: force cached mapping on non x86 platform
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

From: Jérôme Glisse <jglisse(a)redhat.com> People interested in providing uncached or write combined mapping on there architecture need to do the ground work inside there arch specific code to allow to break the linear kernel mapping so that page mapping attributes can be updated, in the meantime force cached mapping for non x86 architecture. Signed-off-by: Jérôme Glisse <jglisse(a)redhat.com> Signed-off-by: Benjamin Herrenschmidt <benh(a)palm4.ozlabs.ibm.com> --- [Minor compile fixes on top of Jerome original v3] drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 32 +++++++++++++++++++++----------- include/drm/ttm/ttm_bo_driver.h | 2 +- 5 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 72afe82..4dd5060 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -304,7 +304,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, return r; } - r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); + r = ttm_tt_set_placement_caching(bo->ttm, &tmp_mem.placement); if (unlikely(r)) { goto out_cleanup; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 3da89d5..4dc21c3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -305,7 +305,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, goto out_err; } - ret = ttm_tt_set_placement_caching(bo->ttm, mem->placement); + ret = ttm_tt_set_placement_caching(bo->ttm, &mem->placement); if (ret) goto out_err; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 30e5d90..e31d48c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -59,7 +59,7 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo, old_mem->mem_type = TTM_PL_SYSTEM; } - ret = ttm_tt_set_placement_caching(ttm, new_mem->placement); + ret = ttm_tt_set_placement_caching(ttm, &new_mem->placement); if (unlikely(ret != 0)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index bf080ab..19ae8ee 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -89,14 +89,6 @@ static inline int ttm_tt_set_page_caching(struct page *p, return ret; } -#else /* CONFIG_X86 */ -static inline int ttm_tt_set_page_caching(struct page *p, - enum ttm_caching_state c_old, - enum ttm_caching_state c_new) -{ - return 0; -} -#endif /* CONFIG_X86 */ /* * Change caching policy for the linear kernel map @@ -149,19 +141,37 @@ out_err: return ret; } -int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement) +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement) { enum ttm_caching_state state; - if (placement & TTM_PL_FLAG_WC) + if (*placement & TTM_PL_FLAG_WC) state = tt_wc; - else if (placement & TTM_PL_FLAG_UNCACHED) + else if (*placement & TTM_PL_FLAG_UNCACHED) state = tt_uncached; else state = tt_cached; return ttm_tt_set_caching(ttm, state); } +#else /* CONFIG_X86 */ +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement) +{ + if (*placement & (TTM_PL_TT | TTM_PL_FLAG_SYSTEM)) { + ttm->caching_state = tt_cached; + *placement &= ~TTM_PL_MASK_CACHING; + *placement |= TTM_PL_FLAG_CACHED; + } else { + if (*placement & TTM_PL_FLAG_WC) + ttm->caching_state = tt_wc; + else if (*placement & TTM_PL_FLAG_UNCACHED) + ttm->caching_state = tt_uncached; + else + ttm->caching_state = tt_cached; + } + return 0; +} +#endif /* CONFIG_X86 */ EXPORT_SYMBOL(ttm_tt_set_placement_caching); void ttm_tt_destroy(struct ttm_tt *ttm) diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 1d9f0f1..cbc5ad2 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -669,7 +669,7 @@ extern int ttm_tt_swapin(struct ttm_tt *ttm); * hit RAM. This function may be very costly as it involves global TLB * and cache flushes and potential page splitting / combining. */ -extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); +extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement); extern int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage);

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[PATCH 4/9] drm/ast: Don't assume DVO enabled means SIL164 on uninitialized chips
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

It looks like the AST2400 comes up with the DVO enable bit set, which causes us to incorrectly assume we have a SIL164 regardless of the value of the scratch registers setup by the BMC firmware. So let's limit that test to the case where the chip has already been setup by a BIOS. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- drivers/gpu/drm/ast/ast_main.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 556d065..48998b2 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -158,16 +158,22 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) /* * VGACRA3 Enhanced Color Mode Register, check if DVO is already * enabled, in that case, assume we have a SIL164 TMDS transmitter + * + * Don't make that assumption if we the chip wasn't enabled and + * is at power-on reset, otherwise we'll incorrectly "detect" a + * SIL164 when there is none. */ - jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); - if (jreg & 0x80) - ast->tx_chip_type = AST_TX_SIL164; + if (!*need_post) { + jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); + if (jreg & 0x80) + ast->tx_chip_type = AST_TX_SIL164; + } if ((ast->chip == AST2300) || (ast->chip == AST2400)) { /* * On AST2300 and 2400, look the configuration set by the SoC in * the SOC scratch register #1 bits 11:8 (interestingly marked - * as "reserved" in the spec + * as "reserved" in the spec) */ jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg) {

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[PATCH 3/9] drm/ast: Properly initialize P2A base before using it in ast_init_3rdtx()
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

If the P2A has been used to target other SOC registers before that call, we're going to hit the wrong place so make sure we set the base address up properly before using it. (P2A stands for PCIe to AHB bridge and is the bride that allows accessing the AST's internal AHB bus using a relocatable 64k window in the second half of the PCIe MMIO BAR) Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- drivers/gpu/drm/ast/ast_dp501.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c index 5da4b62..7e2ddde 100644 --- a/drivers/gpu/drm/ast/ast_dp501.c +++ b/drivers/gpu/drm/ast/ast_dp501.c @@ -400,7 +400,18 @@ void ast_init_3rdtx(struct drm_device *dev) if (ast->tx_chip_type == AST_TX_SIL164) ast_init_dvo(dev); else { + /* + * Set DAC source to VGA mode in SCU2C via the P2A + * bridge. First configure the P2U to target the SCU + * in case it isn't at this stage. + */ + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + /* Then unlock the SCU with the magic password */ ast_write32(ast, 0x12000, 0x1688a8a8); + ast_write32(ast, 0x12000, 0x1688a8a8); + ast_write32(ast, 0x12000, 0x1688a8a8); + /* Finally, clear bits [17:16] of SCU2c */ data = ast_read32(ast, 0x1202c); data &= 0xfffcffff; ast_write32(ast, 0, data);

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[PATCH 2/9] drm/ast: POST chip at probe time if VGA not enabled
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

We need to do it on machines without a BIOS such as POWER8. Also for detection to work without triggering PCIe errors, we need to enable VGA early on, inside ast_detect_chip(). While touching those files, replace a few hard coded register numbers with the corresponding symbolic constant. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- drivers/gpu/drm/ast/ast_drv.h | 3 +++ drivers/gpu/drm/ast/ast_main.c | 47 ++++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/ast/ast_post.c | 23 +++++++++++++-------- 3 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index a203a6f..78fc683 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -384,6 +384,9 @@ int ast_bo_push_sysram(struct ast_bo *bo); int ast_mmap(struct file *filp, struct vm_area_struct *vma); /* ast post */ +void ast_enable_vga(struct drm_device *dev); +void ast_enable_mmio(struct drm_device *dev); +bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index c2ff793..556d065 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -63,7 +63,7 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, } -static int ast_detect_chip(struct drm_device *dev) +static int ast_detect_chip(struct drm_device *dev, bool *need_post) { struct ast_private *ast = dev->dev_private; uint32_t data, jreg; @@ -109,6 +109,21 @@ static int ast_detect_chip(struct drm_device *dev) } } + /* + * If VGA isn't enabled, we need to enable now or subsequent + * access to the scratch registers will fail. We also inform + * our caller that it needs to POST the chip + * (Assumption: VGA not enabled -> need to POST) + */ + if (!ast_is_vga_enabled(dev)) { + ast_enable_vga(dev); + ast_enable_mmio(dev); + DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); + *need_post = true; + } else + *need_post = false; + + /* Check if we support wide screen */ switch (ast->chip) { case AST1180: ast->support_wide_screen = true; @@ -124,6 +139,7 @@ static int ast_detect_chip(struct drm_device *dev) ast->support_wide_screen = true; else { ast->support_wide_screen = false; + /* Read SCU7c (silicon revision register) */ ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); data = ast_read32(ast, 0x1207c); @@ -136,11 +152,23 @@ static int ast_detect_chip(struct drm_device *dev) break; } + /* Check 3rd Tx option (digital output afaik) */ ast->tx_chip_type = AST_TX_NONE; + + /* + * VGACRA3 Enhanced Color Mode Register, check if DVO is already + * enabled, in that case, assume we have a SIL164 TMDS transmitter + */ jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); if (jreg & 0x80) ast->tx_chip_type = AST_TX_SIL164; + if ((ast->chip == AST2300) || (ast->chip == AST2400)) { + /* + * On AST2300 and 2400, look the configuration set by the SoC in + * the SOC scratch register #1 bits 11:8 (interestingly marked + * as "reserved" in the spec + */ jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg) { case 0x04: @@ -161,6 +189,17 @@ static int ast_detect_chip(struct drm_device *dev) } } + /* Print stuff for diagnostic purposes */ + switch(ast->tx_chip_type) { + case AST_TX_SIL164: + DRM_INFO("Using Sil164 TMDS transmitter\n"); + break; + case AST_TX_DP501: + DRM_INFO("Using DP501 DisplayPort transmitter\n"); + break; + default: + DRM_INFO("Analog VGA only\n"); + } return 0; } @@ -345,6 +384,7 @@ static u32 ast_get_vram_info(struct drm_device *dev) int ast_driver_load(struct drm_device *dev, unsigned long flags) { struct ast_private *ast; + bool need_post; int ret = 0; ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); @@ -379,7 +419,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) } } - ast_detect_chip(dev); + ast_detect_chip(dev, &need_post); if (ast->chip != AST1180) { ast_get_dram_info(dev); @@ -387,6 +427,9 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); } + if (need_post) + ast_post_gpu(dev); + ret = ast_mm_init(ast); if (ret) goto out_free; diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 38d437f..810c51d 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -33,18 +33,23 @@ static void ast_init_dram_2300(struct drm_device *dev); -static void -ast_enable_vga(struct drm_device *dev) +void ast_enable_vga(struct drm_device *dev) +{ + struct ast_private *ast = dev->dev_private; + + ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); +} + +void ast_enable_mmio(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; - ast_io_write8(ast, 0x43, 0x01); - ast_io_write8(ast, 0x42, 0x01); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); } -#if 0 /* will use later */ -static bool -ast_is_vga_enabled(struct drm_device *dev) + +bool ast_is_vga_enabled(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 ch; @@ -52,7 +57,7 @@ ast_is_vga_enabled(struct drm_device *dev) if (ast->chip == AST1180) { /* TODO 1180 */ } else { - ch = ast_io_read8(ast, 0x43); + ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); if (ch) { ast_open_key(ast); ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff); @@ -61,7 +66,6 @@ ast_is_vga_enabled(struct drm_device *dev) } return 0; } -#endif static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff }; @@ -371,6 +375,7 @@ void ast_post_gpu(struct drm_device *dev) pci_write_config_dword(ast->dev->pdev, 0x04, reg); ast_enable_vga(dev); + ast_enable_mmio(dev); ast_open_key(ast); ast_set_def_ext_reg(dev);

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[PATCH 8/9] drm/ttm: Clean usage of ttm_io_prot() with TTM_PL_FLAG_CACHED
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

Today, most callers of ttm_io_prot() check TTM_PL_FLAG_CACHED before calling it since on some archs it will unconditionally create non-cached mappings. But not all callers do which is incorrect as far as I can tell. Instead, move that check inside ttm_io_port() itself for all archs and make powerpc use the same implementation as ia64 and arm Signed-off-by: Benjamin Herrenschmidt <benh(a)palm4.ozlabs.ibm.com> --- drivers/gpu/drm/ttm/ttm_bo_util.c | 19 ++++++++----------- drivers/gpu/drm/ttm/ttm_bo_vm.c | 5 ++--- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index e31d48c..ef2ac3c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -487,28 +487,27 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp) { + /* Cached mappings need no adjustment */ + if (caching_flags & TTM_PL_FLAG_CACHED) + return tmp; + #if defined(__i386__) || defined(__x86_64__) if (caching_flags & TTM_PL_FLAG_WC) tmp = pgprot_writecombine(tmp); else if (boot_cpu_data.x86 > 3) tmp = pgprot_noncached(tmp); -#elif defined(__powerpc__) - if (!(caching_flags & TTM_PL_FLAG_CACHED)) { - pgprot_val(tmp) |= _PAGE_NO_CACHE; - if (caching_flags & TTM_PL_FLAG_UNCACHED) - pgprot_val(tmp) |= _PAGE_GUARDED; +#endif } #endif -#if defined(__ia64__) || defined(__arm__) +#if defined(__ia64__) || defined(__arm__) || defined(__powerpc__) if (caching_flags & TTM_PL_FLAG_WC) tmp = pgprot_writecombine(tmp); else tmp = pgprot_noncached(tmp); #endif #if defined(__sparc__) || defined(__mips__) - if (!(caching_flags & TTM_PL_FLAG_CACHED)) - tmp = pgprot_noncached(tmp); + tmp = pgprot_noncached(tmp); #endif return tmp; } @@ -567,9 +566,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, * We need to use vmap to get the desired page protection * or to make the buffer object look contiguous. */ - prot = (mem->placement & TTM_PL_FLAG_CACHED) ? - PAGE_KERNEL : - ttm_io_prot(mem->placement, PAGE_KERNEL); + prot = ttm_io_prot(mem->placement, PAGE_KERNEL); map->bo_kmap_type = ttm_bo_map_vmap; map->virtual = vmap(ttm->pages + start_page, num_pages, 0, prot); diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 0ce48e5..4ce8dc1 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -200,9 +200,8 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) cvma.vm_page_prot); } else { ttm = bo->ttm; - if (!(bo->mem.placement & TTM_PL_FLAG_CACHED)) - cvma.vm_page_prot = ttm_io_prot(bo->mem.placement, - cvma.vm_page_prot); + cvma.vm_page_prot = ttm_io_prot(bo->mem.placement, + cvma.vm_page_prot); /* Allocate all page at once, most common usage */ if (ttm->bdev->driver->ttm_tt_populate(ttm)) {

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[PATCH 7/9] drm: powerpc can use a simpler drm_io_prot()
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

What the code does is equivalent to the x86 code, so let's use it as well Signed-off-by: Benjamin Herrenschmidt <benh(a)palm4.ozlabs.ibm.com> --- drivers/gpu/drm/drm_vm.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index 24e045c..ed02563 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -48,15 +48,11 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, { pgprot_t tmp = vm_get_page_prot(vma->vm_flags); -#if defined(__i386__) || defined(__x86_64__) +#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); else tmp = pgprot_writecombine(tmp); -#elif defined(__powerpc__) - pgprot_val(tmp) |= _PAGE_NO_CACHE; - if (map->type == _DRM_REGISTERS) - pgprot_val(tmp) |= _PAGE_GUARDED; #elif defined(__ia64__) if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))

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[PATCH 5/9] drm/ast: Cleanup analog init code path
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

Move the MMIO mangling to a separate routine and actually disable the DVO output when using pure analog. Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> --- drivers/gpu/drm/ast/ast_dp501.c | 49 ++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c index 7e2ddde..76f07f3 100644 --- a/drivers/gpu/drm/ast/ast_dp501.c +++ b/drivers/gpu/drm/ast/ast_dp501.c @@ -379,11 +379,39 @@ static bool ast_init_dvo(struct drm_device *dev) return true; } + +static void ast_init_analog(struct drm_device *dev) +{ + struct ast_private *ast = dev->dev_private; + u32 data; + + /* + * Set DAC source to VGA mode in SCU2C via the P2A + * bridge. First configure the P2U to target the SCU + * in case it isn't at this stage. + */ + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + + /* Then unlock the SCU with the magic password */ + ast_write32(ast, 0x12000, 0x1688a8a8); + ast_write32(ast, 0x12000, 0x1688a8a8); + ast_write32(ast, 0x12000, 0x1688a8a8); + + /* Finally, clear bits [17:16] of SCU2c */ + data = ast_read32(ast, 0x1202c); + data &= 0xfffcffff; + ast_write32(ast, 0, data); + + /* Disable DVO */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00); +} + void ast_init_3rdtx(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; - u32 data; + if (ast->chip == AST2300 || ast->chip == AST2400) { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg & 0x0e) { @@ -399,23 +427,8 @@ void ast_init_3rdtx(struct drm_device *dev) default: if (ast->tx_chip_type == AST_TX_SIL164) ast_init_dvo(dev); - else { - /* - * Set DAC source to VGA mode in SCU2C via the P2A - * bridge. First configure the P2U to target the SCU - * in case it isn't at this stage. - */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - /* Then unlock the SCU with the magic password */ - ast_write32(ast, 0x12000, 0x1688a8a8); - ast_write32(ast, 0x12000, 0x1688a8a8); - ast_write32(ast, 0x12000, 0x1688a8a8); - /* Finally, clear bits [17:16] of SCU2c */ - data = ast_read32(ast, 0x1202c); - data &= 0xfffcffff; - ast_write32(ast, 0, data); - } + else + ast_init_analog(dev); } } }

1 0

[PATCH 4/9] drm/ast: Don't assume DVO enabled means SIL164 on uninitialized chips
by Benjamin Herrenschmidt 04 Sep '14

04 Sep '14

1 0

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dri-devel September 2014