dri-devel May 2015

dri-devel@lists.freedesktop.org

191 participants
1132 discussions

[Bug 90534] integrated LVDS displays stays dark (firmware-linux-nonfree-0.43)
by bugzilla-daemon＠freedesktop.org 21 May '15

21 May '15

1 0

[PATCH] drm/msm: dsi: fix compile errors when CONFIG_GPIOLIB=n
by Brian Norris 20 May '15

20 May '15

I'm not sure where, exactly, but somewhere in here we must be relying on an implicit include. drivers/gpu/drm/msm/dsi/dsi_host.c: In function ‘dsi_host_init_panel_gpios’: drivers/gpu/drm/msm/dsi/dsi_host.c:1356:2: error: implicit declaration of function ‘devm_gpiod_get’ [-Werror=implicit-function-declaration] msm_host->disp_en_gpio = devm_gpiod_get(panel_device, ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1356:25: warning: assignment makes pointer from integer without a cast [enabled by default] msm_host->disp_en_gpio = devm_gpiod_get(panel_device, ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1364:3: error: implicit declaration of function ‘gpiod_direction_output’ [-Werror=implicit-function-declaration] ret = gpiod_direction_output(msm_host->disp_en_gpio, 0); ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1371:20: warning: assignment makes pointer from integer without a cast [enabled by default] msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te"); ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1378:3: error: implicit declaration of function ‘gpiod_direction_input’ [-Werror=implicit-function-declaration] ret = gpiod_direction_input(msm_host->te_gpio); ^ drivers/gpu/drm/msm/dsi/dsi_host.c: In function ‘msm_dsi_host_power_on’: drivers/gpu/drm/msm/dsi/dsi_host.c:1918:3: error: implicit declaration of function ‘gpiod_set_value’ [-Werror=implicit-function-declaration] gpiod_set_value(msm_host->disp_en_gpio, 1); ^ Signed-off-by: Brian Norris <computersforpeace(a)gmail.com> Cc: David Airlie <airlied(a)linux.ie> Cc: Rob Clark <robdclark(a)gmail.com> Cc: Hai Li <hali(a)codeaurora.org> Cc: dri-devel(a)lists.freedesktop.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 956b22492c9a..98aae759f2fd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -15,6 +15,7 @@ #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/of_device.h> #include <linux/of_gpio.h> -- 1.9.1

1 0

Radeon Verde displayport failure.
by Dave Jones 20 May '15

20 May '15

I just bought a new radeon (1002:682c), to pair with my shiny new displayport monitor. It shows a display during through the BIOS POST, and grub, but when the kernel starts up, it's a coin toss whether or not I get anything. Sometimes it just goes straight into power saving. When I do get something on the console, it continues to boot and then X starts up and puts it into power saving too. Trying to flip back to tty1 doesn't light up the display again. I'm running On debian stable, with copied-by-hand verde_* firmware files from the linux-firmware git tree. Here's a log from the 4.0-rc2 kernel. Any other info I can provide ? Dave [drm] register mmio base: 0xFBE00000 [drm] register mmio size: 262144 radeon 0000:01:00.0: Invalid ROM contents ATOM BIOS: C755 radeon 0000:01:00.0: VRAM: 2048M 0x0000000000000000 - 0x000000007FFFFFFF (2048M used) radeon 0000:01:00.0: GTT: 1024M 0x0000000080000000 - 0x00000000BFFFFFFF [drm] Detected VRAM RAM=2048M, BAR=256M [drm] RAM width 128bits DDR [TTM] Zone kernel: Available graphics memory: 16400232 kiB [TTM] Zone dma32: Available graphics memory: 2097152 kiB [TTM] Initializing pool allocator [TTM] Initializing DMA pool allocator [drm] radeon: 2048M of VRAM memory ready [drm] radeon: 1024M of GTT memory ready. [drm] Loading verde Microcode [drm] Internal thermal controller with fan control [drm] probing gen 2 caps for device 8086:2f08 = 77a3103/e input: HDA ATI HDMI HDMI as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card0/input4 input: HDA ATI HDMI HDMI as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card0/input5 [drm] radeon: dpm initialized [drm] GART: num cpu pages 262144, num gpu pages 262144 [drm] probing gen 2 caps for device 8086:2f08 = 77a3103/e [drm] PCIE gen 3 link speeds already enabled [drm] PCIE GART of 1024M enabled (table at 0x0000000000277000). radeon 0000:01:00.0: WB enabled radeon 0000:01:00.0: fence driver on ring 0 use gpu addr 0x0000000080000c00 and cpu addr 0xffff880807d0ac00 radeon 0000:01:00.0: fence driver on ring 1 use gpu addr 0x0000000080000c04 and cpu addr 0xffff880807d0ac04 radeon 0000:01:00.0: fence driver on ring 2 use gpu addr 0x0000000080000c08 and cpu addr 0xffff880807d0ac08 radeon 0000:01:00.0: fence driver on ring 3 use gpu addr 0x0000000080000c0c and cpu addr 0xffff880807d0ac0c radeon 0000:01:00.0: fence driver on ring 4 use gpu addr 0x0000000080000c10 and cpu addr 0xffff880807d0ac10 radeon 0000:01:00.0: fence driver on ring 5 use gpu addr 0x0000000000075a18 and cpu addr 0xffffc90001035a18 [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [drm] Driver supports precise vblank timestamp query. radeon 0000:01:00.0: radeon: MSI limited to 32-bit radeon 0000:01:00.0: radeon: using MSI. [drm] radeon: irq initialized. [drm] ring test on 0 succeeded in 1 usecs [drm] ring test on 1 succeeded in 1 usecs [drm] ring test on 2 succeeded in 1 usecs [drm] ring test on 3 succeeded in 9 usecs [drm] ring test on 4 succeeded in 3 usecs [drm] ring test on 5 succeeded in 2 usecs [drm] UVD initialized successfully. [drm] ib test on ring 0 succeeded in 0 usecs [drm] ib test on ring 1 succeeded in 0 usecs [drm] ib test on ring 2 succeeded in 0 usecs [drm] ib test on ring 3 succeeded in 0 usecs [drm] ib test on ring 4 succeeded in 0 usecs [drm] ib test on ring 5 succeeded [drm] Radeon Display Connectors [drm] Connector 0: [drm] DP-1 [drm] HPD4 [drm] DDC: 0x6540 0x6540 0x6544 0x6544 0x6548 0x6548 0x654c 0x654c [drm] Encoders: [drm] DFP1: INTERNAL_UNIPHY2 [drm] Connector 1: [drm] DP-2 [drm] HPD5 [drm] DDC: 0x6530 0x6530 0x6534 0x6534 0x6538 0x6538 0x653c 0x653c [drm] Encoders: [drm] DFP2: INTERNAL_UNIPHY1 [drm] Connector 2: [drm] DP-3 [drm] HPD1 [drm] DDC: 0x6560 0x6560 0x6564 0x6564 0x6568 0x6568 0x656c 0x656c [drm] Encoders: [drm] DFP3: INTERNAL_UNIPHY1 [drm] Connector 3: [drm] DP-4 [drm] HPD2 [drm] DDC: 0x6580 0x6580 0x6584 0x6584 0x6588 0x6588 0x658c 0x658c [drm] Encoders: [drm] DFP4: INTERNAL_UNIPHY [drm:si_dpm_set_power_state [radeon]] *ERROR* si_enable_smc_cac failed [drm] fb mappable at 0xD047A000 [drm] vram apper at 0xD0000000 [drm] size 3145728 [drm] fb depth is 24 [drm] pitch is 4096 fbcon: radeondrmfb (fb0) is primary device [drm:si_dpm_set_power_state [radeon]] *ERROR* si_enable_smc_cac failed [drm:radeon_dp_link_train [radeon]] *ERROR* displayport link status failed [drm:radeon_dp_link_train [radeon]] *ERROR* clock recovery failed Console: switching to colour frame buffer device 128x48 radeon 0000:01:00.0: fb0: radeondrmfb frame buffer device radeon 0000:01:00.0: registered panic notifier [drm] Initialized radeon 2.42.0 20080528 for 0000:01:00.0 on minor 0 [drm:radeon_dp_link_train [radeon]] *ERROR* displayport link status failed [drm:radeon_dp_link_train [radeon]] *ERROR* clock recovery failed

4 13

[Bug 73338] Fan speed in idle at 40% with radeonsi and at 18% with catalyst
by bugzilla-daemon＠freedesktop.org 20 May '15

20 May '15

https://bugs.freedesktop.org/show_bug.cgi?id=73338 --- Comment #89 from Pär Forsling <electropura(a)forsling.net> --- (In reply to Oliver Winker from comment #88) > (In reply to r.andersen from comment #84) > > ... and I should add > > > > echo "50" > pwm1 > > > > also makes my computer hang. > > Exactly the same on my HD7850 (see [1]) on kernel v4.0. > > Are there maybe hints how to debug this ? <snip> Sorry, I have no debug hints. For what it's worth, I have a nearly identical card and the same kernel version (see below), and both manual and automatic modes works flawlessly. $ uname -a Linux wallace 4.0.0-1-pelle #1 SMP PREEMPT Thu Apr 23 20:32:42 CEST 2015 x86_64 GNU/Linux $ sudo lspci -v 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Pitcairn PRO [Radeon HD 7850] (prog-if 00 [VGA controller]) Subsystem: Gigabyte Technology Co., Ltd Device 2553 Flags: bus master, fast devsel, latency 0, IRQ 33 Memory at d0000000 (64-bit, prefetchable) [size=256M] Memory at fe780000 (64-bit, non-prefetchable) [size=256K] I/O ports at b000 [size=256] Expansion ROM at fe7c0000 [disabled] [size=128K] Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [58] Express Legacy Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] #19 Capabilities: [2b0] Address Translation Service (ATS) Capabilities: [2c0] #13 Capabilities: [2d0] #1b Kernel driver in use: radeon Kernel modules: radeon -- You are receiving this mail because: You are the assignee for the bug.

1 0

[PATCH 00/11] Add H/W Debugger module support to amdkfd
by Oded Gabbay 20 May '15

20 May '15

This patch-set adds the H/W debugger module support to amdkfd. The H/W debugger module support enables a userspace debugger, e.g gdb, to debug GPU kernels running in HSA mode. The available operations in this patch-set are setting watchpoints in the GPU kernel and controlling wave-fronts. It is important to mention that due to security reasons, the userspace process can only debug itself. This means that the process should contain an "agent" that could be connected to remotely by a debugger, which will provide the front-end to the user. There is ongoing work inside AMD to provide such a tool via gdb extensions. In addition, this patch-set enables amdkfd to "kill" all running waves, in case of an infinite GPU kernel (due to bug or malicious attack), by using the debugger infrastructure. This provides greater control to the kernel level, which is always a good thing, IMO. More data is inside the individual commit messages. Please review. Thanks, Oded Alexey Skidanov (1): drm/radeon: Add ATC VMID<-->PASID functions to kfd->kgd Ben Goz (1): drm/amdkfd: Enforce kill all waves on process termination Yair Shachar (9): drm/radeon: Add H/W debugger kfd->kgd functions drm/amdkfd: add H/W debugger IOCTL set definitions drm/amdkfd: Add static user-mode queues support drm/amdkfd: Add skeleton H/W debugger module support drm/amdkfd: Add wave control operation to debugger drm/amdkfd: Add address watch operation to debugger drm/amdkfd: Implement (un)register debugger IOCTLs drm/amdkfd: Implement wave control debugger IOCTL drm/amdkfd: Implement address watch debugger IOCTL drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 310 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 886 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h | 193 +++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c | 168 ++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h | 294 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 5 + .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 48 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 6 + drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 46 +- drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h | 6 +- drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h | 290 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 18 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 + .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 18 +- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 21 + drivers/gpu/drm/radeon/cik_reg.h | 56 +- drivers/gpu/drm/radeon/cikd.h | 9 +- drivers/gpu/drm/radeon/radeon_kfd.c | 151 +++- include/uapi/linux/kfd_ioctl.h | 43 +- 20 files changed, 2548 insertions(+), 31 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h -- 2.1.0

1 11

[PATCH v2] drm/exynos: calculate vrefresh instead of use a fixed value
by Gustavo Padovan 20 May '15

20 May '15

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> When mode's vrefresh is zero we should ask DRM core to calculate vrefresh for us so we can get the correct value instead of relying on fixed value defined in a macro. But if vrefresh is still zero we should fail the update. Suggested-by: Daniel Stone <daniels(a)collabora.com> Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 9819fa6..ea7da0e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -42,7 +42,6 @@ * CPU Interface. */ -#define FIMD_DEFAULT_FRAMERATE 60 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 /* position control register for hardware window 0, 2 ~ 4.*/ @@ -329,7 +328,9 @@ static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { if (adjusted_mode->vrefresh == 0) - adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; + adjusted_mode->vrefresh = drm_mode_vrefresh(mode); + if (adjusted_mode->vrefresh == 0) + return false; return true; } -- 2.1.0

2 2

[Bug 73338] Fan speed in idle at 40% with radeonsi and at 18% with catalyst
by bugzilla-daemon＠freedesktop.org 20 May '15

20 May '15

https://bugs.freedesktop.org/show_bug.cgi?id=73338 --- Comment #88 from Oliver Winker <oliverml1(a)oli1170.net> --- (In reply to r.andersen from comment #84) > ... and I should add > > echo "50" > pwm1 > > also makes my computer hang. Exactly the same on my HD7850 (see [1]) on kernel v4.0. Are there maybe hints how to debug this ? [1] --- Linux gamix64 4.0.0-owi1+ #1 SMP Sat May 9 10:17:17 CEST 2015 x86_64 GNU/Linux --- 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Pitcairn PRO [Radeon HD 7850] (prog-if 00 [VGA controller]) Subsystem: PC Partner Limited / Sapphire Technology Radeon HD 7850 2GB GDDR5 DVI-I/DVI-D/HDMI/DP Flags: bus master, fast devsel, latency 0, IRQ 36 Memory at e0000000 (64-bit, prefetchable) [size=256M] Memory at f5000000 (64-bit, non-prefetchable) [size=256K] I/O ports at a000 [size=256] [virtual] Expansion ROM at f4000000 [disabled] [size=128K] Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [58] Express Legacy Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] #19 Capabilities: [2b0] Address Translation Service (ATS) Capabilities: [2c0] #13 Capabilities: [2d0] #1b Kernel driver in use: radeon --- -- You are receiving this mail because: You are the assignee for the bug.

1 0

[PATCH 1/2] drm/exynos: calculate vrefresh instead of use a fixed value
by Gustavo Padovan 20 May '15

20 May '15

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> When mode's vrefresh is zero we should ask DRM core to calculate vrefresh for us so we can get the correct value instead of relying on fixed value defined in a macro. Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 9819fa6..08f7197 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -42,7 +42,6 @@ * CPU Interface. */ -#define FIMD_DEFAULT_FRAMERATE 60 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 /* position control register for hardware window 0, 2 ~ 4.*/ @@ -329,7 +328,7 @@ static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { if (adjusted_mode->vrefresh == 0) - adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; + adjusted_mode->vrefresh = drm_mode_vrefresh(mode); return true; } -- 2.1.0

3 8

[PATCH 00/12] treewide: Use DECLARE_BITMAP
by Joe Perches 20 May '15

20 May '15

Use the standard method to declare a bitmap array. Joe Perches (12): ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP dmaengine: rcar-dmac: Use DECLARE_BITMAP drm/amdkfd: Use DECLARE_BITMAP drm/radeon: Use DECLARE_BITMAP IB/ehca: Use DECLARE_BITMAP bcache: Use DECLARE_BITMAP spider_net: Use DECLARE_BITMAP s390/sclp: Use DECLARE_BITMAP [SCSI] qla4xxx: Use DECLARE_BITMAP scsi: Use DECLARE_BITMAP logfs: Use DECLARE_BITMAP sunrpc: Use DECLARE_BITMAP arch/arm/mach-imx/iomux-imx31.c | 2 +- drivers/dma/sh/rcar-dmac.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 ++--- drivers/gpu/drm/radeon/radeon.h | 2 +- drivers/infiniband/hw/ehca/ipz_pt_fn.h | 2 +- drivers/md/bcache/journal.c | 2 +- drivers/net/ethernet/toshiba/spider_net.c | 3 +-- drivers/s390/char/sclp_cmd.c | 2 +- drivers/scsi/qla4xxx/ql4_def.h | 2 +- drivers/scsi/sr.c | 2 +- fs/logfs/logfs.h | 2 +- net/sunrpc/auth_gss/svcauth_gss.c | 2 +- 12 files changed, 13 insertions(+), 15 deletions(-) -- 2.1.2

3 4

[PATCH] drm/msm/mdp4: Support NV12MT format in mdp4
by Rob Clark 20 May '15

20 May '15

Using fb modifier flag, support NV12MT format in MDP4. v2: - rework the modifier's description [Daniel Vetter's comment] - drop .set_mode_config() callback [Rob Clark's comment] v3: - change VENDOR's name and restrict usage to NV12 [pointed by Daniel] Signed-off-by: Rob Clark <robdclark(a)gmail.com> --- drivers/gpu/drm/drm_crtc.c | 14 ++++++++++++++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 2 ++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 22 ++++++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 15 +++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3007b44..ed5d3f9 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -3304,6 +3304,20 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) r->modifier[i], i); return -EINVAL; } + + /* modifier specific checks: */ + switch (r->modifier[i]) { + case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: + if (r->pixel_format != DRM_FORMAT_NV12 || + width % 128 || height % 32) { + DRM_DEBUG_KMS("bad modifier data for plane %d\n", i); + return -EINVAL; + } + break; + + default: + break; + } } return 0; diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c index d847b94..88a75cb 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c @@ -119,6 +119,8 @@ static int mdp4_hw_init(struct msm_kms *kms) if (mdp4_kms->rev > 1) mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); + dev->mode_config.allow_fb_modifiers = true; + out: pm_runtime_put_sync(dev->dev); diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c index dbc0689..0d1dbb7 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c @@ -33,6 +33,21 @@ struct mdp4_plane { }; #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base) +/* MDP format helper functions */ +static inline +enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb) +{ + bool is_tile = false; + + if (fb->modifier[1] == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) + is_tile = true; + + if (fb->pixel_format == DRM_FORMAT_NV12 && is_tile) + return FRAME_TILE_YCBCR_420; + + return FRAME_LINEAR; +} + static void mdp4_plane_set_scanout(struct drm_plane *plane, struct drm_framebuffer *fb); static int mdp4_plane_mode_set(struct drm_plane *plane, @@ -205,6 +220,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, uint32_t op_mode = 0; uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT; + enum mdp4_frame_format frame_type = mdp4_get_frame_format(fb); if (!(crtc && fb)) { DBG("%s: disabled!", mdp4_plane->name); @@ -304,6 +320,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) | MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) | + MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) | COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT)); mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe), @@ -324,6 +341,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step); mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step); + if (frame_type != FRAME_LINEAR) + mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe), + MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) | + MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h)); + return 0; } diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 0773582..2f295cd 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -207,4 +207,19 @@ */ #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) +/* + * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks + * + * Macroblocks are laid in a Z-shape, and each pixel data is following the + * standard NV12 style. + * As for NV12, an image is the result of two frame buffers: one for Y, + * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). + * Alignment requirements are (for each buffer): + * - multiple of 128 pixels for the width + * - multiple of 32 pixels for the height + * + * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html + */ +#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) + #endif /* DRM_FOURCC_H */ -- 2.4.1

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dri-devel May 2015