dri-devel June 2015

dri-devel@lists.freedesktop.org

188 participants
1140 discussions

[Bug 83436] New: Sudden framerate drops in multiple games
by bugzilla-daemon＠freedesktop.org 23 Aug '15

23 Aug '15

https://bugs.freedesktop.org/show_bug.cgi?id=83436 Priority: medium Bug ID: 83436 Assignee: dri-devel(a)lists.freedesktop.org Summary: Sudden framerate drops in multiple games Severity: major Classification: Unclassified OS: Linux (All) Reporter: gutigen(a)outlook.com Hardware: x86-64 (AMD64) Status: NEW Version: git Component: Drivers/Gallium/radeonsi Product: Mesa Created attachment 105680 --> https://bugs.freedesktop.org/attachment.cgi?id=105680&action=edit dmesg I'm having a lot of fps drops in TF2, Unigine Heaven, Xonotic, Wine games. Framerate goes from even something like stable 100fps to sudden 5-15fps, it hangs there for few seconds and goes back up to usual. On top of that I've noticed some performance decrease in above apps by even 20%. This is happening since last week (maybe friday? something around the weekend). -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 66384] New: VDPAU playback hangs when moving window between xrandr monitors
by bugzilla-daemon＠freedesktop.org 20 Aug '15

20 Aug '15

https://bugs.freedesktop.org/show_bug.cgi?id=66384 Priority: medium Bug ID: 66384 Assignee: dri-devel(a)lists.freedesktop.org Summary: VDPAU playback hangs when moving window between xrandr monitors Severity: normal Classification: Unclassified OS: All Reporter: mgorny(a)gentoo.org Hardware: Other Status: NEW Version: unspecified Component: Drivers/Gallium/r600 Product: Mesa I'm running live xorg/mesa with Radeon HD5450. I have two monitors connected and set up side-by-side using xrandr like the following: $ xrandr --output VGA-0 --mode 1280x960 --right-of DVI-0 Now, when I play a movie using mplayer2 with VDPAU driver and move the movie onto second monitor without pausing it first, the playback hangs for a minute or two. Then it resumes like nothing happened, no messages neither on console nor in dmesg. What's interesting is that it seems to happen only after moving half of the window. If I have it partially on both monitors, it plays back fine. After the hang it plays fine again, and if I then move it back to the first monitor, it again hangs after moving half of it. -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 93701] New: radeon: two "empty" pixel lines on left side of screen, rest of screen gets slightly squished
by bugzilla-daemon＠bugzilla.kernel.org 19 Aug '15

19 Aug '15

https://bugzilla.kernel.org/show_bug.cgi?id=93701 Bug ID: 93701 Summary: radeon: two "empty" pixel lines on left side of screen, rest of screen gets slightly squished Product: Drivers Version: 2.5 Kernel Version: 4.0-rc1 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: frederik.hofe(a)gmail.com Regression: No This happens in the current 4.0-rc1. 3.19 does not show this. Basicly it looks like my resolution of 1920x1080 gets blitted into 1918,1080 with linear filtering somewhere before it gets on my screen. When I take a screenshot with gimp, I get a normal 1920x1080 image without the defect. I use a Radeon 7870 (Pitcairn) -> HDMI -> Samsung S22A350H Also I use the padoka PPA for bleeding edge mesa/llvm drivers. glxinfo|grep OpenGL OpenGL vendor string: X.Org OpenGL renderer string: Gallium 0.4 on AMD PITCAIRN OpenGL core profile version string: 3.3 (Core Profile) Mesa 10.6.0-devel (padoka PPA) OpenGL core profile shading language version string: 3.30 OpenGL core profile context flags: (none) OpenGL core profile profile mask: core profile OpenGL core profile extensions: OpenGL version string: 3.0 Mesa 10.6.0-devel (padoka PPA) OpenGL shading language version string: 1.30 OpenGL context flags: (none) OpenGL extensions: OpenGL ES profile version string: OpenGL ES 3.0 Mesa 10.6.0-devel (padoka PPA) OpenGL ES profile shading language version string: OpenGL ES GLSL ES 3.00 OpenGL ES profile extensions: -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH RFC v2 0/7] Implement generic ASoC HDMI codec
by Jyri Sarha 17 Aug '15

17 Aug '15

Only the first three patches are meant for serious review. The ASoC part should be ready for review in other respects but the EDID SADs handling is waiting for Russell King's DRM ELD helper patches. There is a copy-pasted not-to-be-merged patch with the same functionality in the patch series. The tda998x part is not complete and I do not think Jean-Francois' binding are ready as such either. At least the usage of reg property in a port node for something that is not an address or even guaranteed to be unique is not a good idea. Some documentation of how to configure AP0-AP4 pins (REG_ENA_AP?) would help in making a proper binding for the tda998x audio configuration. These patches, my tilcdc refactoring[1], and my latest BCLK fixes for davinci-mcasp driver [2], can be found in a branch that produces working HDMI audio on Beaglebone-Black here: https://github.com/jsarha/linux.git linux-master-bbb-hdmi-20150512 [1] http://lists.freedesktop.org/archives/dri-devel/2015-May/082537.html [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2015-April/090974.html Jean-Francois Moine (1): drm/i2c: tda998x: Add support of a DT graph of ports DO NOT MERGE Jyri Sarha (6): ASoC: core: If component doesn't have of_node use parent's node instead ASoC: hdmi: Remove obsolete dummy HDMI codec ASoC: hdmi-codec: Add hdmi-codec for external HDMI-encoders ASoC: hdmi-codec: Add ELD based audio pcm rules DO NOT MERGE drm/i2c: tda998x: Register ASoC HDMI codec for audio functionality DO NOT MERGE ARM: dts: am335x-boneblack: Add HDMI audio support DO NOT MERGE .../devicetree/bindings/drm/i2c/tda998x.txt | 51 ++ arch/arm/boot/dts/am335x-boneblack.dts | 78 ++- drivers/gpu/drm/i2c/Kconfig | 1 + drivers/gpu/drm/i2c/tda998x_drv.c | 328 +++++++++++- include/sound/hdmi-codec.h | 99 ++++ include/sound/tda998x.h | 8 + sound/soc/codecs/Kconfig | 2 +- sound/soc/codecs/Makefile | 4 +- sound/soc/codecs/hdmi-codec.c | 560 +++++++++++++++++++++ sound/soc/codecs/hdmi.c | 109 ---- sound/soc/soc-core.c | 14 +- 11 files changed, 1129 insertions(+), 125 deletions(-) create mode 100644 include/sound/hdmi-codec.h create mode 100644 include/sound/tda998x.h create mode 100644 sound/soc/codecs/hdmi-codec.c delete mode 100644 sound/soc/codecs/hdmi.c -- 1.9.1

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[Bug 53118] New: Rendering error in unigine heaven when GL_ARB_shader_bit_encoding is used.
by bugzilla-daemon＠freedesktop.org 16 Aug '15

16 Aug '15

https://bugs.freedesktop.org/show_bug.cgi?id=53118 Bug #: 53118 Summary: Rendering error in unigine heaven when GL_ARB_shader_bit_encoding is used. Classification: Unclassified Product: Mesa Version: git Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/r600 AssignedTo: dri-devel(a)lists.freedesktop.org ReportedBy: thomas.lindroth(a)gmail.com Created attachment 65111 --> https://bugs.freedesktop.org/attachment.cgi?id=65111 screenshot Textures are rendered incorrectly in unigine heaven on latest git drivers with kernel 3.5.0 when shaders are set to high and ambient occlusion is on. The problem is fixed when exporting MESA_EXTENSION_OVERRIDE="-GL_ARB_shader_bit_encoding" Hardware is juniper. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug.

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[Bug 89228] Regression with left for dead 2
by bugzilla-daemon＠freedesktop.org 14 Aug '15

14 Aug '15

https://bugs.freedesktop.org/show_bug.cgi?id=89228 Bug ID: 89228 Summary: Regression with left for dead 2 Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/radeonsi Assignee: dri-devel(a)lists.freedesktop.org Reporter: kdj0c(a)djinvi.net QA Contact: dri-devel(a)lists.freedesktop.org L4d2 used to work with mesa 10.3, I now have graphical glitches, and it ends up in GPU hang after ~5min of game. might be related to https://bugs.freedesktop.org/show_bug.cgi?id=88561 Hardware is Radeon HD7950 llvm 3.7svn, Linux 3.19.0-g18320f2 OpenGL vendor string: X.Org OpenGL renderer string: Gallium 0.4 on AMD TAHITI OpenGL core profile version string: 3.3 (Core Profile) Mesa 10.6.0-devel (git-9216348) OpenGL core profile shading language version string: 3.30 I'm uploading an apitrace, will add a comment with the link when it's done. -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 74329] New: Please expose OES_texture_float and OES_texture_half_float on the ES3 context
by bugzilla-daemon＠freedesktop.org 14 Aug '15

14 Aug '15

https://bugs.freedesktop.org/show_bug.cgi?id=74329 Priority: medium Bug ID: 74329 Assignee: dri-devel(a)lists.freedesktop.org Summary: Please expose OES_texture_float and OES_texture_half_float on the ES3 context Severity: minor Classification: Unclassified OS: Linux (All) Reporter: org.freedesktop(a)io7m.com Hardware: All Status: NEW Version: 10.0 Component: Drivers/DRI/R600 Product: Mesa Hello. Original discussion on mailing list: http://lists.freedesktop.org/archives/mesa-users/2014-February/000761.html Essentially, for the purposes of testing code in an ES3 context as it would be run on an ES2 context (that is, taking the paths the code would take based on the extensions present on ES2), it would be nice if the ES3 context exposed OES_texture_float and OES_texture_half_float. The current ES3 context on this hardware exposes GL_EXT_texture_rg and GL_EXT_color_buffer_float, and can therefore definitely support OES_texture_float and OES_texture_half_float. All that would (apparently) be required would be for floating point textures to be specified in an ES2 compatible manner (with format and internalformat set to GL_RED|GL_RG, and type set to GL_FLOAT). -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH v2] drm/panel: add lg4573 driver
by Heiko Schocher 14 Aug '15

14 Aug '15

Add support for LG LG4573 480x800 4,3" panel. the LG4573 is used on the LG LCD LB043WV2-SD01, an industrial 4.3" TFT panel with SPI control interface. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Changes in v2: - add comments from Thierry Reding: - fix some spelling issues - remove "power-on-delay" - remove display timings usage from DT, instead specify the timing in the driver. - change config symbol to DRM_PANEL_LG_LG4573 - change filename to panel-lg-lg4573.c - get rid of power_on_delay - use cpu_to_be16() - rework lg4573_spi_write_u16_array() - introduce lg4573_spi_write_dcs() - reworked error reporting .../devicetree/bindings/panel/lg,lg4573.txt | 19 + drivers/gpu/drm/panel/Kconfig | 8 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-lg-lg4573.c | 382 +++++++++++++++++++++ 4 files changed, 410 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/lg,lg4573.txt create mode 100644 drivers/gpu/drm/panel/panel-lg-lg4573.c diff --git a/Documentation/devicetree/bindings/panel/lg,lg4573.txt b/Documentation/devicetree/bindings/panel/lg,lg4573.txt new file mode 100644 index 0000000..824441f --- /dev/null +++ b/Documentation/devicetree/bindings/panel/lg,lg4573.txt @@ -0,0 +1,19 @@ +LG LG4573 TFT Liquid Crystal Display with SPI control bus + +Required properties: + - compatible: "lg,lg4573" + - reg: address of the panel on the SPI bus + +The panel must obey rules for SPI slave device specified in document [1]. + +[1]: Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + + lcd_panel: display@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <0>; + }; diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 6d64c7b..e7a4d16 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -23,6 +23,14 @@ config DRM_PANEL_LD9040 depends on OF && SPI select VIDEOMODE_HELPERS +config DRM_PANEL_LG_LG4573 + tristate "LG4573 RGB/SPI panel" + depends on OF && SPI + select VIDEOMODE_HELPERS + help + Say Y here if you want to enable support for LG4573 RGB panel. + To compile this driver as a module, choose M here. + config DRM_PANEL_S6E8AA0 tristate "S6E8AA0 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 4b2a043..437e8bf 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o +obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o diff --git a/drivers/gpu/drm/panel/panel-lg-lg4573.c b/drivers/gpu/drm/panel/panel-lg-lg4573.c new file mode 100644 index 0000000..9fbe646 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-lg-lg4573.c @@ -0,0 +1,382 @@ +/* + * + * Copyright (C) 2015 Heiko Schocher <hs(a)denx.de> + * + * from: + * drivers/gpu/drm/panel/panel-ld9040.c + * ld9040 AMOLED LCD drm_panel driver. + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd + * Derived from drivers/video/backlight/ld9040.c + * + * Andrzej Hajda <a.hajda(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <drm/drmP.h> +#include <drm/drm_panel.h> + +#include <linux/gpio/consumer.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +#include <video/mipi_display.h> +#include <video/of_videomode.h> +#include <video/videomode.h> + +struct lg4573 { + struct drm_panel panel; + struct device *dev; + struct videomode vm; +}; + +static inline struct lg4573 *panel_to_lg4573(struct drm_panel *panel) +{ + return container_of(panel, struct lg4573, panel); +} + +static int lg4573_spi_write_u16(struct lg4573 *ctx, u16 data) +{ + struct spi_device *spi = to_spi_device(ctx->dev); + struct spi_transfer xfer = { + .len = 2, + }; + struct spi_message msg; + u16 temp = cpu_to_be16(data); + + dev_dbg(ctx->dev, "writing data: %x\n", data); + xfer.tx_buf = &temp; + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + + return spi_sync(spi, &msg); +} + +static int lg4573_spi_write_u16_array(struct lg4573 *ctx, u16 *buf, int cnt) +{ + int i; + int ret; + + for (i = 0; i < cnt; i++) { + ret = lg4573_spi_write_u16(ctx, buf[i]); + if (ret) + return ret; + } + return 0; +} + +static int lg4573_spi_write_dcs(struct lg4573 *ctx, u8 dcs) +{ + return lg4573_spi_write_u16(ctx, (0x70 << 8 | dcs)); +} + +static int lg4573_display_on(struct lg4573 *ctx) +{ + int ret; + + ret = lg4573_spi_write_dcs(ctx, MIPI_DCS_EXIT_SLEEP_MODE); + if (ret) + return ret; + + msleep(5); + return lg4573_spi_write_dcs(ctx, MIPI_DCS_SET_DISPLAY_ON); +} + +static int lg4573_display_off(struct lg4573 *ctx) +{ + int ret; + + ret = lg4573_spi_write_dcs(ctx, MIPI_DCS_SET_DISPLAY_OFF); + if (ret) + return ret; + + msleep(120); + return lg4573_spi_write_dcs(ctx, MIPI_DCS_ENTER_SLEEP_MODE); +} + +static int lg4573_display_mode_settings(struct lg4573 *ctx) +{ + static u16 display_mode_settings[] = { + 0x703A, + 0x7270, + 0x70B1, + 0x7208, + 0x723B, + 0x720F, + 0x70B2, + 0x7200, + 0x72C8, + 0x70B3, + 0x7200, + 0x70B4, + 0x7200, + 0x70B5, + 0x7242, + 0x7210, + 0x7210, + 0x7200, + 0x7220, + 0x70B6, + 0x720B, + 0x720F, + 0x723C, + 0x7213, + 0x7213, + 0x72E8, + 0x70B7, + 0x7246, + 0x7206, + 0x720C, + 0x7200, + 0x7200, + }; + + dev_dbg(ctx->dev, "transfer display mode settings\n"); + return lg4573_spi_write_u16_array(ctx, display_mode_settings, + ARRAY_SIZE(display_mode_settings)); +} + +static int lg4573_power_settings(struct lg4573 *ctx) +{ + static u16 power_settings[] = { + 0x70C0, + 0x7201, + 0x7211, + 0x70C3, + 0x7207, + 0x7203, + 0x7204, + 0x7204, + 0x7204, + 0x70C4, + 0x7212, + 0x7224, + 0x7218, + 0x7218, + 0x7202, + 0x7249, + 0x70C5, + 0x726F, + 0x70C6, + 0x7241, + 0x7263, + }; + + dev_dbg(ctx->dev, "transfer power settings\n"); + return lg4573_spi_write_u16_array(ctx, power_settings, + ARRAY_SIZE(power_settings)); +} + +static int lg4573_gamma_settings(struct lg4573 *ctx) +{ + static u16 gamma_settings[] = { + 0x70D0, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + 0x70D1, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + 0x70D2, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + 0x70D3, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + 0x70D4, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + 0x70D5, + 0x7203, + 0x7207, + 0x7273, + 0x7235, + 0x7200, + 0x7201, + 0x7220, + 0x7200, + 0x7203, + }; + + dev_dbg(ctx->dev, "transfer gamma settings\n"); + return lg4573_spi_write_u16_array(ctx, gamma_settings, + ARRAY_SIZE(gamma_settings)); +} + +static int lg4573_init(struct lg4573 *ctx) +{ + int ret; + + dev_dbg(ctx->dev, "initializing LCD\n"); + + ret = lg4573_display_mode_settings(ctx); + if (ret) + return ret; + + ret = lg4573_power_settings(ctx); + if (ret) + return ret; + + return lg4573_gamma_settings(ctx); +} + +static int lg4573_power_on(struct lg4573 *ctx) +{ + return lg4573_display_on(ctx); +} + +static int lg4573_disable(struct drm_panel *panel) +{ + struct lg4573 *ctx = panel_to_lg4573(panel); + + return lg4573_display_off(ctx); +} + +static int lg4573_enable(struct drm_panel *panel) +{ + struct lg4573 *ctx = panel_to_lg4573(panel); + int ret; + + lg4573_init(ctx); + + ret = lg4573_power_on(ctx); + + return ret; +} + +static const struct drm_display_mode default_mode = { + .clock = 27000, + .hdisplay = 480, + .hsync_start = 480 + 10, + .hsync_end = 480 + 10 + 59, + .htotal = 480 + 10 + 59 + 10, + .vdisplay = 800, + .vsync_start = 800 + 15, + .vsync_end = 800 + 15 + 15, + .vtotal = 800 + 15 + 15 + 15, + .vrefresh = 60, +}; + +static int lg4573_get_modes(struct drm_panel *panel) +{ + struct drm_connector *connector = panel->connector; + struct drm_device *drm = panel->drm; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(drm, &default_mode); + if (!mode) { + dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", + default_mode.hdisplay, default_mode.vdisplay, + default_mode.vrefresh); + return -ENOMEM; + } + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + panel->connector->display_info.width_mm = 61; + panel->connector->display_info.height_mm = 103; + + return 1; +} + +static const struct drm_panel_funcs lg4573_drm_funcs = { + .disable = lg4573_disable, + .enable = lg4573_enable, + .get_modes = lg4573_get_modes, +}; + +static int lg4573_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct lg4573 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(struct lg4573), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + spi_set_drvdata(spi, ctx); + ctx->dev = dev; + + spi->bits_per_word = 8; + ret = spi_setup(spi); + if (ret < 0) { + dev_err(dev, "SPI setup failed. err = %d\n", ret); + return ret; + } + + drm_panel_init(&ctx->panel); + ctx->panel.dev = dev; + ctx->panel.funcs = &lg4573_drm_funcs; + + return drm_panel_add(&ctx->panel); +} + +static int lg4573_remove(struct spi_device *spi) +{ + struct lg4573 *ctx = spi_get_drvdata(spi); + + lg4573_display_off(ctx); + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id lg4573_of_match[] = { + { .compatible = "lg,lg4573" }, + { } +}; +MODULE_DEVICE_TABLE(of, lg4573_of_match); + +static struct spi_driver lg4573_driver = { + .probe = lg4573_probe, + .remove = lg4573_remove, + .driver = { + .name = "lg4573", + .owner = THIS_MODULE, + .of_match_table = lg4573_of_match, + }, +}; +module_spi_driver(lg4573_driver); + +MODULE_AUTHOR("Heiko Schocher <hs(a)denx.de>"); +MODULE_DESCRIPTION("lg4573 LCD Driver"); +MODULE_LICENSE("GPL v2"); -- 2.1.0

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[PATCH] drm/panel: Add display timing for Okaya RS800480T-7X0GP
by Gary Bisson 13 Aug '15

13 Aug '15

Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson <gary.bisson(a)boundarydevices.com> --- Hi all, This patch is the follow-up of a request from Philipp to add the Okaya display to the simple panel driver. http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/346657.html Regards, Gary --- .../bindings/panel/okaya,rs800480t_7x0gp.txt | 7 ++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + drivers/gpu/drm/panel/panel-simple.c | 27 ++++++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt diff --git a/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt new file mode 100644 index 0000000..f7c729d --- /dev/null +++ b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt @@ -0,0 +1,7 @@ +OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel + +Required properties: +- compatible: should be "okaya,rs800480t_7x0gp" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4f35a00..06ce91c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -145,6 +145,7 @@ nintendo Nintendo nokia Nokia nvidia NVIDIA nxp NXP Semiconductors +okaya OKAYA Electric America, Inc. onnn ON Semiconductor Corp. opencores OpenCores.org ortustech Ortus Technology Co., Ltd. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 97b66b8..e511a22 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -942,6 +942,30 @@ static const struct panel_desc lg_lp129qe = { }, }; +static const struct display_timing okaya_rs800480t_7x0gp_timing = { + .pixelclock = { 30000000, 30000000, 40000000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 40, 40, 40 }, + .hback_porch = { 40, 40, 40 }, + .hsync_len = { 1, 48, 48 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 13, 13, 13 }, + .vback_porch = { 29, 29, 29 }, + .vsync_len = { 3, 3, 3 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc okaya_rs800480t_7x0gp = { + .timings = &okaya_rs800480t_7x0gp_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 154, + .height = 87, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, +}; + static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { .clock = 25000, .hdisplay = 480, @@ -1112,6 +1136,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "lg,lp129qe", .data = &lg_lp129qe, }, { + .compatible = "okaya,rs800480t_7x0gp", + .data = &okaya_rs800480t_7x0gp, + }, { .compatible = "ortustech,com43h4m85ulc", .data = &ortustech_com43h4m85ulc, }, { -- 2.1.4

4 16

[PATCH 1/9] drm/radeon: rework VCE FW size calculation
by Christian König 12 Aug '15

12 Aug '15

From: Christian König <christian.koenig(a)amd.com> Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/radeon/radeon.h | 2 -- drivers/gpu/drm/radeon/radeon_asic.h | 1 + drivers/gpu/drm/radeon/radeon_vce.c | 3 +-- drivers/gpu/drm/radeon/vce_v2_0.c | 16 +++++++++++++--- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 46eb0fa..34c51a2 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1709,8 +1709,6 @@ int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, * VCE */ #define RADEON_MAX_VCE_HANDLES 16 -#define RADEON_VCE_STACK_SIZE (1024*1024) -#define RADEON_VCE_HEAP_SIZE (4*1024*1024) struct radeon_vce { struct radeon_bo *vcpu_bo; diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index a3ca8cd..cb7787f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -974,6 +974,7 @@ int vce_v1_0_init(struct radeon_device *rdev); int vce_v1_0_start(struct radeon_device *rdev); /* vce v2.0 */ +unsigned vce_v2_0_bo_size(struct radeon_device *rdev); int vce_v2_0_resume(struct radeon_device *rdev); #endif diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 0de5711..5b952bd 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -123,8 +123,7 @@ int radeon_vce_init(struct radeon_device *rdev) /* allocate firmware, stack and heap BO */ - size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) + - RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE; + size = vce_v2_0_bo_size(rdev); r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL, &rdev->vce.vcpu_bo); diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index fbbe78f..cdeaab7 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c @@ -31,6 +31,10 @@ #include "radeon_asic.h" #include "cikd.h" +#define VCE_V2_0_FW_SIZE (256 * 1024) +#define VCE_V2_0_STACK_SIZE (64 * 1024) +#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES) + static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) { u32 tmp; @@ -140,6 +144,12 @@ static void vce_v2_0_init_cg(struct radeon_device *rdev) WREG32(VCE_CLOCK_GATING_B, tmp); } +unsigned vce_v2_0_bo_size(struct radeon_device *rdev) +{ + WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE); + return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE; +} + int vce_v2_0_resume(struct radeon_device *rdev) { uint64_t addr = rdev->vce.gpu_addr; @@ -159,17 +169,17 @@ int vce_v2_0_resume(struct radeon_device *rdev) WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); addr &= 0xff; - size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); + size = VCE_V2_0_FW_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE0, size); addr += size; - size = RADEON_VCE_STACK_SIZE; + size = VCE_V2_0_STACK_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE1, size); addr += size; - size = RADEON_VCE_HEAP_SIZE; + size = VCE_V2_0_DATA_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE2, size); -- 1.9.1

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dri-devel June 2015