dri-devel September 2015

dri-devel@lists.freedesktop.org

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1129 discussions

[PATCH] libdrm: Add framebuffer modifiers uapi
by Tvrtko Ursulin 07 Sep '15

07 Sep '15

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Sync up with new kernel features as per commits: e3eb3250d84ef97b766312345774367b6a310db8 93b81f5102a7cd270a305c2741b17c8d44bb0629 b5ff6e1637b683d5996ae11ac29afe406c0bee90 8c4f83fb1e8bf317e894f62d17a63c32b7a6b75e 570655b09b065d2fff1b8ab9bdb8308f4c5a05a3 Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: dri-devel(a)lists.freedesktop.org Cc: Rob Clark <robdclark(a)gmail.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> --- include/drm/drm.h | 1 + include/drm/drm_fourcc.h | 93 ++++++++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_mode.h | 11 +++++- 3 files changed, 104 insertions(+), 1 deletion(-) diff --git a/include/drm/drm.h b/include/drm/drm.h index 167b7b81b0d0..a950b580cd11 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -816,6 +816,7 @@ struct drm_event_vblank { #define DRM_CAP_PRIME 0x5 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 +#define DRM_CAP_ADDFB2_MODIFIERS 0x10 #define DRM_PRIME_CAP_IMPORT 0x1 #define DRM_PRIME_CAP_EXPORT 0x2 diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 85facb0a17cf..63a80ca5ba39 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -127,4 +127,97 @@ #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ + +/* + * Format Modifiers: + * + * Format modifiers describe, typically, a re-ordering or modification + * of the data in a plane of an FB. This can be used to express tiled/ + * swizzled formats, or compression, or a combination of the two. + * + * The upper 8 bits of the format modifier are a vendor-id as assigned + * below. The lower 56 bits are assigned as vendor sees fit. + */ + +/* Vendor Ids: */ +#define DRM_FORMAT_MOD_NONE 0 +#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 +#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 +#define DRM_FORMAT_MOD_VENDOR_NV 0x03 +#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 +#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 +/* add more to the end as needed */ + +#define fourcc_mod_code(vendor, val) \ + ((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) + +/* + * Format Modifier tokens: + * + * When adding a new token please document the layout with a code comment, + * similar to the fourcc codes above. drm_fourcc.h is considered the + * authoritative source for all of these. + */ + +/* Intel framebuffer modifiers */ + +/* + * Intel X-tiling layout + * + * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) + * in row-major layout. Within the tile bytes are laid out row-major, with + * a platform-dependent stride. On top of that the memory can apply + * platform-depending swizzling of some higher address bits into bit6. + * + * This format is highly platforms specific and not useful for cross-driver + * sharing. It exists since on a given platform it does uniquely identify the + * layout in a simple way for i915-specific userspace. + */ +#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) + +/* + * Intel Y-tiling layout + * + * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) + * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) + * chunks column-major, with a platform-dependent height. On top of that the + * memory can apply platform-depending swizzling of some higher address bits + * into bit6. + * + * This format is highly platforms specific and not useful for cross-driver + * sharing. It exists since on a given platform it does uniquely identify the + * layout in a simple way for i915-specific userspace. + */ +#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) + +/* + * Intel Yf-tiling layout + * + * This is a tiled layout using 4Kb tiles in row-major layout. + * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which + * are arranged in four groups (two wide, two high) with column-major layout. + * Each group therefore consits out of four 256 byte units, which are also laid + * out as 2x2 column-major. + * 256 byte units are made out of four 64 byte blocks of pixels, producing + * either a square block or a 2:1 unit. + * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width + * in pixel depends on the pixel depth. + */ +#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) + +/* + * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks + * + * Macroblocks are laid in a Z-shape, and each pixel data is following the + * standard NV12 style. + * As for NV12, an image is the result of two frame buffers: one for Y, + * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). + * Alignment requirements are (for each buffer): + * - multiple of 128 pixels for the width + * - multiple of 32 pixels for the height + * + * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html + */ +#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) + #endif /* DRM_FOURCC_H */ diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 69c1ac3cf00c..115f36e452d9 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -322,7 +322,8 @@ struct drm_mode_fb_cmd { __u32 handle; }; -#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ +#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ +#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ struct drm_mode_fb_cmd2 { __u32 fb_id; @@ -343,10 +344,18 @@ struct drm_mode_fb_cmd2 { * So it would consist of Y as offset[0] and UV as * offset[1]. Note that offset[0] will generally * be 0. + * + * To accommodate tiled, compressed, etc formats, a per-plane + * modifier can be specified. The default value of zero + * indicates "native" format as specified by the fourcc. + * Vendor specific modifier token. This allows, for example, + * different tiling/swizzling pattern on different planes. + * See discussion above of DRM_FORMAT_MOD_xxx. */ __u32 handles[4]; __u32 pitches[4]; /* pitch for each plane */ __u32 offsets[4]; /* offset of each plane */ + __u64 modifier[4]; /* ie, tiling, compressed (per plane) */ }; #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 -- 2.4.6

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[PATCH] virtio-gpu: fix compilation warnings
by Mike Rapoport 07 Sep '15

07 Sep '15

Update snprintf format in virtgpu_fence.c and virtgpu_debugfs.c to fix the following compilation warnings: C [M] drivers/gpu/drm/virtio/virtgpu_fence.o drivers/gpu/drm/virtio/virtgpu_fence.c: In function ‘virtio_timeline_value_str’ : drivers/gpu/drm/virtio/virtgpu_fence.c:64:2: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘long long int’ [-Wformat=] snprintf(str, size, "%lu", atomic64_read(&fence->drv->last_seq)); ^ CC [M] drivers/gpu/drm/virtio/virtgpu_debugfs.o drivers/gpu/drm/virtio/virtgpu_debugfs.c: In function ‘virtio_gpu_debugfs_irq_info’: drivers/gpu/drm/virtio/virtgpu_debugfs.c:39:6: warning: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘long long int’ [-Wformat=] vgdev->fence_drv.sync_seq); ^ Signed-off-by: Mike Rapoport <mike.rapoport(a)gmail.com> --- drivers/gpu/drm/virtio/virtgpu_debugfs.c | 2 +- drivers/gpu/drm/virtio/virtgpu_fence.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_debugfs.c b/drivers/gpu/drm/virtio/virtgpu_debugfs.c index db8b491..d87b27c 100644 --- a/drivers/gpu/drm/virtio/virtgpu_debugfs.c +++ b/drivers/gpu/drm/virtio/virtgpu_debugfs.c @@ -34,7 +34,7 @@ virtio_gpu_debugfs_irq_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *) m->private; struct virtio_gpu_device *vgdev = node->minor->dev->dev_private; - seq_printf(m, "fence %ld %lld\n", + seq_printf(m, "fence %lld %lld\n", atomic64_read(&vgdev->fence_drv.last_seq), vgdev->fence_drv.sync_seq); return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_fence.c b/drivers/gpu/drm/virtio/virtgpu_fence.c index 1da6326..98dd385 100644 --- a/drivers/gpu/drm/virtio/virtgpu_fence.c +++ b/drivers/gpu/drm/virtio/virtgpu_fence.c @@ -61,7 +61,7 @@ static void virtio_timeline_value_str(struct fence *f, char *str, int size) { struct virtio_gpu_fence *fence = to_virtio_fence(f); - snprintf(str, size, "%lu", atomic64_read(&fence->drv->last_seq)); + snprintf(str, size, "%llu", atomic64_read(&fence->drv->last_seq)); } static const struct fence_ops virtio_fence_ops = { -- 1.8.3.1

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[PATCH libdrm] xf86drm: remove makedev() hack/workaround
by Emil Velikov 07 Sep '15

07 Sep '15

Back when this was introduced commit 569da5a42eb(Merged glxmisc-3-0-0) sys/sysmacros.h was used instead of the respecive headers (as per the manual). We've been handling it correctly for a little while now - in Linux, BSD and Solaris. Thus we can drop this workaround. Signed-off-by: Emil Velikov <emil.l.velikov(a)gmail.com> --- xf86drm.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 5e02969..7e41537 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -94,14 +94,6 @@ #define DRM_MAJOR 226 /* Linux */ #endif -/* - * This definition needs to be changed on some systems if dev_t is a structure. - * If there is a header file we can get it from, there would be best. - */ -#ifndef makedev -#define makedev(x,y) ((dev_t)(((x) << 8) | (y))) -#endif - #define DRM_MSG_VERBOSITY 3 #define memclear(s) memset(&s, 0, sizeof(s)) -- 2.5.0

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[PATCH] gpu: host1x: Fix MLOCK's debug info
by Dmitry Osipenko 07 Sep '15

07 Sep '15

MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted value, while unshifted should be used. Fix it by changing '_F' to '_V'. Signed-off-by: Dmitry Osipenko <digetx(a)gmail.com> --- drivers/gpu/host1x/hw/debug_hw.c | 2 +- drivers/gpu/host1x/hw/hw_host1x01_sync.h | 8 ++++---- drivers/gpu/host1x/hw/hw_host1x02_sync.h | 8 ++++---- drivers/gpu/host1x/hw/hw_host1x04_sync.h | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c index 791de93..cc3f182 100644 --- a/drivers/gpu/host1x/hw/debug_hw.c +++ b/drivers/gpu/host1x/hw/debug_hw.c @@ -298,7 +298,7 @@ static void host1x_debug_show_mlocks(struct host1x *host, struct output *o) host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i)); if (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner)) host1x_debug_output(o, "%d: locked by channel %d\n", - i, HOST1X_SYNC_MLOCK_OWNER_CHID_F(owner)); + i, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner)); else if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner)) host1x_debug_output(o, "%d: locked by cpu\n", i); else diff --git a/drivers/gpu/host1x/hw/hw_host1x01_sync.h b/drivers/gpu/host1x/hw/hw_host1x01_sync.h index ac704e5..31238c2 100644 --- a/drivers/gpu/host1x/hw/hw_host1x01_sync.h +++ b/drivers/gpu/host1x/hw/hw_host1x01_sync.h @@ -131,12 +131,12 @@ static inline u32 host1x_sync_mlock_owner_r(unsigned int id) } #define HOST1X_SYNC_MLOCK_OWNER(id) \ host1x_sync_mlock_owner_r(id) -static inline u32 host1x_sync_mlock_owner_chid_f(u32 v) +static inline u32 host1x_sync_mlock_owner_chid_v(u32 v) { - return (v & 0xf) << 8; + return (v >> 8) & 0xf; } -#define HOST1X_SYNC_MLOCK_OWNER_CHID_F(v) \ - host1x_sync_mlock_owner_chid_f(v) +#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \ + host1x_sync_mlock_owner_chid_v(v) static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r) { return (r >> 1) & 0x1; diff --git a/drivers/gpu/host1x/hw/hw_host1x02_sync.h b/drivers/gpu/host1x/hw/hw_host1x02_sync.h index 4495401..540c7b6 100644 --- a/drivers/gpu/host1x/hw/hw_host1x02_sync.h +++ b/drivers/gpu/host1x/hw/hw_host1x02_sync.h @@ -131,12 +131,12 @@ static inline u32 host1x_sync_mlock_owner_r(unsigned int id) } #define HOST1X_SYNC_MLOCK_OWNER(id) \ host1x_sync_mlock_owner_r(id) -static inline u32 host1x_sync_mlock_owner_chid_f(u32 v) +static inline u32 host1x_sync_mlock_owner_chid_v(u32 v) { - return (v & 0xf) << 8; + return (v >> 8) & 0xf; } -#define HOST1X_SYNC_MLOCK_OWNER_CHID_F(v) \ - host1x_sync_mlock_owner_chid_f(v) +#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \ + host1x_sync_mlock_owner_chid_v(v) static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r) { return (r >> 1) & 0x1; diff --git a/drivers/gpu/host1x/hw/hw_host1x04_sync.h b/drivers/gpu/host1x/hw/hw_host1x04_sync.h index ef2275b..3d6c8ec 100644 --- a/drivers/gpu/host1x/hw/hw_host1x04_sync.h +++ b/drivers/gpu/host1x/hw/hw_host1x04_sync.h @@ -131,12 +131,12 @@ static inline u32 host1x_sync_mlock_owner_r(unsigned int id) } #define HOST1X_SYNC_MLOCK_OWNER(id) \ host1x_sync_mlock_owner_r(id) -static inline u32 host1x_sync_mlock_owner_chid_f(u32 v) +static inline u32 host1x_sync_mlock_owner_chid_v(u32 v) { - return (v & 0xf) << 8; + return (v >> 8) & 0xf; } -#define HOST1X_SYNC_MLOCK_OWNER_CHID_F(v) \ - host1x_sync_mlock_owner_chid_f(v) +#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \ + host1x_sync_mlock_owner_chid_v(v) static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r) { return (r >> 1) & 0x1; -- 2.4.4

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[PATCH:libdrm] Include <alloca.h> when needed before calling alloca
by Alan Coopersmith 06 Sep '15

06 Sep '15

Fixes "error: implicit declaration of function 'alloca'" failures when building on Solaris Signed-off-by: Alan Coopersmith <alan.coopersmith(a)oracle.com> --- amdgpu/amdgpu_cs.c | 3 +++ tests/amdgpu/basic_tests.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index c7910ad..4da9821 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -32,6 +32,9 @@ #include <pthread.h> #include <sched.h> #include <sys/ioctl.h> +#ifdef HAVE_ALLOCA_H +# include <alloca.h> +#endif #include "xf86drm.h" #include "amdgpu_drm.h" diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 7874039..e489e6e 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -28,6 +28,9 @@ #include <stdio.h> #include <stdlib.h> #include <unistd.h> +#ifdef HAVE_ALLOCA_H +# include <alloca.h> +#endif #include "CUnit/Basic.h" -- 1.7.9.2

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create framebuffer device layer overlay
by Alex Vazquez 06 Sep '15

06 Sep '15

Hi,all! I'm using atmel-hlcdc driver to control a LCD panel and an application uses the /dev/fb0 framebuffer created by the driver. The display works fine except that the panel's standard orientation is landscape mode (480x275) and I need to use it in portrait mode (275x480). I know that the driver allow rotation but is only for the overlays layers, and not the baselayer. I have tested with modetest and i can do what i want. I want to know if is posible create a device framebuffer from overlay layer use libdrm (e.g. /dev/fb1). Thanks!

2 2

oops in reservation_object_wait_timeout_rcu
by Marcin Ślusarz 06 Sep '15

06 Sep '15

BUG: unable to handle kernel paging request at ffffc90003161018 IP: [<ffffffff8157d12c>] reservation_object_wait_timeout_rcu+0x35c/0x580 PGD 13a89a067 PUD 13a89b067 PMD 136735067 PTE 0 Oops: 0000 [#1] PREEMPT SMP Modules linked in: ctr ccm rfcomm bnep arc4 iwldvm mac80211 binfmt_misc iwlwifi cfg80211 rtsx_usb uvcvideo btusb btbcm btintel bluetooth videobuf2_vmalloc videobuf2_memops videobuf2_core v4l2_common snd_hda_codec_hdmi videodev snd_hda_codec_idt snd_hda_codec_generic dell_wmi snd_hda_intel sparse_keymap dell_laptop dcdbas snd_hda_controller snd_hda_codec x86_pkg_temp_thermal coretemp snd_hwdep snd_pcm snd_hda_core microcode snd_seq_midi snd_seq_midi_event serio_raw snd_rawmidi snd_seq snd_timer snd_seq_device snd lpc_ich soundcore parport_pc ppdev lp parport hid_generic nouveau mxm_wmi ttm i915 psmouse i2c_algo_bit drm_kms_helper ahci libahci usbhid drm hid wmi video CPU: 1 PID: 920 Comm: Xorg Not tainted 4.1.2+ #57 Hardware name: Dell Inc. Inspiron 7720/04M3YM, BIOS A07 08/16/2012 task: ffff880136dec2c0 ti: ffff880136de4000 task.ti: ffff880136de4000 RIP: 0010:[<ffffffff8157d12c>] [<ffffffff8157d12c>] reservation_object_wait_timeout_rcu+0x35c/0x580 RSP: 0018:ffff880136de7c78 EFLAGS: 00010246 RAX: ffffc90003161000 RBX: ffff8800ab123b00 RCX: 00000000ab123200 RDX: 00000000ab123200 RSI: 0000000000000000 RDI: ffffffff81c5be00 RBP: ffff880136de7cd8 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: ffff880136de7d80 R12: 0000000000000000 R13: 0000000000001d4c R14: 000000000000c326 R15: ffff88003290a1b8 FS: 00007f29a7237980(0000) GS:ffff88013f240000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffffc90003161018 CR3: 0000000032cf8000 CR4: 00000000001407e0 Stack: ffffffff8157ce70 ffff8800336a8898 0000000136de7ca8 ffff88003290a250 ffff88004711ce40 000000020190a3f0 ffff880136de7cd8 00000000fffffff0 0000000000000000 ffff88003290a000 ffff88003290a3f0 0000000000000082 Call Trace: [<ffffffff8157ce70>] ? reservation_object_wait_timeout_rcu+0xa0/0x580 [<ffffffffa0349d9d>] nouveau_gem_ioctl_cpu_prep+0x6d/0x190 [nouveau] [<ffffffff812087db>] ? might_fault+0x8b/0xa0 [<ffffffffa003ed25>] drm_ioctl+0x1a5/0x6b0 [drm] [<ffffffff8110d65d>] ? trace_hardirqs_on+0xd/0x10 [<ffffffff8179f432>] ? _raw_spin_unlock_irqrestore+0x42/0x80 [<ffffffffa033fb92>] nouveau_drm_ioctl+0x72/0xd0 [nouveau] [<ffffffff8125cab8>] do_vfs_ioctl+0x308/0x540 [<ffffffff81268c05>] ? __fget+0x5/0x210 [<ffffffff81268e7a>] ? __fget_light+0x2a/0xa0 [<ffffffff8125cd71>] SyS_ioctl+0x81/0xa0 [<ffffffff8179fd9b>] system_call_fastpath+0x16/0x73 Code: d5 a1 81 be c7 03 00 00 48 c7 c7 25 d0 a1 81 c6 05 d0 66 7a 00 01 e8 34 eb b8 ff e9 f5 fd ff ff 0f 1f 80 00 00 00 00 48 8b 43 08 <48> 8b 40 18 48 85 c0 0f 84 c7 fd ff ff 48 89 df ff d0 84 c0 0f RIP [<ffffffff8157d12c>] reservation_object_wait_timeout_rcu+0x35c/0x580 RSP <ffff880136de7c78> CR2: ffffc90003161018 ---[ end trace c4e9ff6a0281167a ]--- Happened once, while I was "testing" Portal.

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[PATCH] drm/msm/dsi: Parse lane swap information from DT
by Hai Li 06 Sep '15

06 Sep '15

Lane swap configuration is based on the board design. This change allows the DSI host to get this information from device tree, instead of hardcoding in driver. Signed-off-by: Hai Li <hali(a)codeaurora.org> --- Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++++++ drivers/gpu/drm/msm/dsi/dsi_host.c | 49 +++++++++++++++++------ 2 files changed, 49 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt b/Documentation/devicetree/bindings/drm/msm/dsi.txt index d56923c..febcc51 100644 --- a/Documentation/devicetree/bindings/drm/msm/dsi.txt +++ b/Documentation/devicetree/bindings/drm/msm/dsi.txt @@ -44,6 +44,17 @@ Optional properties: - port: DSI controller output port. This contains one endpoint subnode, with its remote-endpoint set to the phandle of the connected panel's endpoint. See Documentation/devicetree/bindings/graph.txt for device graph info. +- qcom,dsi-logical-lane-swap: Character string to swap logical lane to physical + lane mapping. Supported lane mappings: + "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3; + "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; + "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3; + "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3; + "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3; + "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3; + "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3; + "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3; + Default value is "0123", which means no lane swap. DSI PHY: Required properties: @@ -129,6 +140,8 @@ Example: remote-endpoint = <&panel_in>; }; }; + + qcom,dsi-logical-lane-swap = "0123"; }; mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 { diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8d82973f..eaba417 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -131,6 +131,7 @@ struct msm_dsi_host { enum mipi_dsi_pixel_format format; unsigned long mode_flags; + u32 dlane_swap; u32 dma_cmd_ctrl_restore; bool registered; @@ -684,19 +685,9 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, data = DSI_CTRL_CLK_EN; DBG("lane number=%d", msm_host->lanes); - if (msm_host->lanes == 2) { - data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2; - /* swap lanes for 2-lane panel for better performance */ - dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, - DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230)); - } else { - /* Take 4 lanes as default */ - data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 | - DSI_CTRL_LANE3; - /* Do not swap lanes for 4-lane panel */ - dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, - DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); - } + data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); + dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, + DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) dsi_write(msm_host, REG_DSI_LANE_CTRL, @@ -1289,6 +1280,9 @@ static int dsi_host_attach(struct mipi_dsi_host *host, struct msm_dsi_host *msm_host = to_msm_dsi_host(host); int ret; + if (dsi->lanes > 4 || dsi->channel > 3) + return -EINVAL; + msm_host->channel = dsi->channel; msm_host->lanes = dsi->lanes; msm_host->format = dsi->format; @@ -1344,6 +1338,33 @@ static struct mipi_dsi_host_ops dsi_host_ops = { .transfer = dsi_host_transfer, }; +static void dsi_parse_dlane_swap(struct msm_dsi_host *msm_host, + struct device_node *np) +{ + const char *lane_swap; + + lane_swap = of_get_property(np, "qcom,dsi-logical-lane-swap", NULL); + + if (!lane_swap) + msm_host->dlane_swap = LANE_SWAP_0123; + else if (!strncmp(lane_swap, "3012", 5)) + msm_host->dlane_swap = LANE_SWAP_3012; + else if (!strncmp(lane_swap, "2301", 5)) + msm_host->dlane_swap = LANE_SWAP_2301; + else if (!strncmp(lane_swap, "1230", 5)) + msm_host->dlane_swap = LANE_SWAP_1230; + else if (!strncmp(lane_swap, "0321", 5)) + msm_host->dlane_swap = LANE_SWAP_0321; + else if (!strncmp(lane_swap, "1032", 5)) + msm_host->dlane_swap = LANE_SWAP_1032; + else if (!strncmp(lane_swap, "2103", 5)) + msm_host->dlane_swap = LANE_SWAP_2103; + else if (!strncmp(lane_swap, "3210", 5)) + msm_host->dlane_swap = LANE_SWAP_3210; + else + msm_host->dlane_swap = LANE_SWAP_0123; +} + static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { struct device *dev = &msm_host->pdev->dev; @@ -1358,6 +1379,8 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) return ret; } + dsi_parse_dlane_swap(msm_host, np); + /* * Get the first endpoint node. In our case, dsi has one output port * to which the panel is connected. Don't return an error if a port -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation

2 1

[PATCH] pci: Handle 5-bit and 8-bit tag field
by Pierre Moreau 06 Sep '15

06 Sep '15

If the hardware supports extended tag field (8-bit ones), then enabled it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible values to 32. Apparently bits 7:0 of 0x8841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 Signed-off-by: Pierre Moreau <dev(a)pmoreau.org> --- drm/nouveau/nvkm/subdev/pci/base.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/pci/base.c b/drm/nouveau/nvkm/subdev/pci/base.c index d1c148e..70631b3 100644 --- a/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drm/nouveau/nvkm/subdev/pci/base.c @@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) pci->func->wr32(pci, addr, data); } +u32 +nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 add) +{ + u32 data = pci->func->rd32(pci, addr); + pci->func->wr32(pci, addr, (data & ~mask) | add); + return data; +} + void nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow) { @@ -115,6 +123,23 @@ nvkm_pci_init(struct nvkm_subdev *subdev) if (ret) return ret; + if (pci_is_pcie(pdev)) { + /* Tag field is 8-bit long, regardless of EXT_TAG. + * However, if EXT_TAG is disabled, only the lower 5 bits of the tag + * field should be used, limiting the number of request to 32. + * + * Apparently, 0x041c stores some limit on the number of requests + * possible, so if EXT_TAG is disabled, limit that requests number to + * 32 + * + * Fixes fdo#86537 + */ + if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020) + nvkm_pci_mask(pci, 0x0080, 0x00000000, 0x00000100); + else + nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000); + } + pci->irq = pdev->irq; return ret; } -- 2.5.1

1 0

[PATCH] pci: Handle 5-bit and 8-bit tag field
by Pierre Moreau 06 Sep '15

06 Sep '15

If the hardware supports extended tag field (8-bit ones), then enabled it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible values to 32. Apparently bits 7:0 of 0x8841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 Signed-off-by: Pierre Moreau <pierre.morrow(a)free.fr> --- drm/nouveau/nvkm/subdev/pci/base.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/pci/base.c b/drm/nouveau/nvkm/subdev/pci/base.c index d1c148e..70631b3 100644 --- a/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drm/nouveau/nvkm/subdev/pci/base.c @@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) pci->func->wr32(pci, addr, data); } +u32 +nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 add) +{ + u32 data = pci->func->rd32(pci, addr); + pci->func->wr32(pci, addr, (data & ~mask) | add); + return data; +} + void nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow) { @@ -115,6 +123,23 @@ nvkm_pci_init(struct nvkm_subdev *subdev) if (ret) return ret; + if (pci_is_pcie(pdev)) { + /* Tag field is 8-bit long, regardless of EXT_TAG. + * However, if EXT_TAG is disabled, only the lower 5 bits of the tag + * field should be used, limiting the number of request to 32. + * + * Apparently, 0x041c stores some limit on the number of requests + * possible, so if EXT_TAG is disabled, limit that requests number to + * 32 + * + * Fixes fdo#86537 + */ + if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020) + nvkm_pci_mask(pci, 0x0080, 0x00000000, 0x00000100); + else + nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000); + } + pci->irq = pdev->irq; return ret; } -- 2.5.1

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dri-devel September 2015