dri-devel January 2016

dri-devel@lists.freedesktop.org

194 participants
1200 discussions

[PATCH 1/3] drm: add helper to check for wc memory support
by Oded Gabbay 03 Feb '16

03 Feb '16

From: Dave Airlie <airlied(a)redhat.com> Signed-off-by: Dave Airlie <airlied(a)redhat.com> Signed-off-by: Oded Gabbay <oded.gabbay(a)gmail.com> --- include/drm/drm_cache.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 7bfb063..461a055 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -35,4 +35,13 @@ void drm_clflush_pages(struct page *pages[], unsigned long num_pages); +static inline bool drm_arch_can_wc_memory(void) +{ +#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) + return false; +#else + return true; +#endif +} + #endif -- 2.5.0

4 11

[PATCH v8 00/13] MT8173 DRM support
by Philipp Zabel 03 Feb '16

03 Feb '16

Hi, this MT8173 DRM update changes the clock bindings once more, as the MIPI_TX D-PHY and the HDMI PHY have internal PLLs that are better abstracted using the common clock framework. The clock outputs of the PHY modules are routed to the respective encoders, in the HDMI case by way of the TOP clock module. I'd like it if Michael or Stephen could take a look at the clock patches and maybe give an Ack or a Nope for this to be merged through the DRM tree. Various other issues have been fixed, for more details see the individual patches. Some changes since v7: - Added PLL reference input clocks and output clocks to the MIPI TX D-PHY and HDMI PHY nodes - Added HS input clocks to the MIPI DSI encoder nodes - Dropped the hdmitx_dig_cts clock from the TOP dividers, it is not a child of tvdpll_445p5m anyway. This clock signal really is provided by the HDMI PHY - Added "power-domains" properties to all nodes in the MM domain - Documented the merge and split function block bindings - Merged Daniel's wait for exclusive fences on incoming framebuffers using reservation_object_wait_timeout_rcu in .atomic_complete() into the DRM driver patch. This allowed to drop the drm/atomic-helper wait_for_fences export patch again. - Added missing atomic destroy_state callbacks, cleaned up reset callbacks - Added a pending_planes flag to mtk_crtc so we can atomically update the plane configuration - Fixed OD ddp_comp function setup - Separated enabling MIPI TX phy output from enabling the PLL (via CCF), this allows to keep the pixel clock running separately from the encoder output when disabling the crtc, to wait for the last vblank. - Fixed mtk_dpi_power_on reference counting - Fill ELD info in the HDMI driver, for future audio support. - Renamed the MT8173 specific HDMI PHY driver, as MT2701 has a different PHY. - Update iommus binding to v7 IOMMU patches. The following patches are needed to cleanly apply the device tree changes on top of v4.4-rc1: 61aee9342514 ("arm64: dts: mt8173: add MT8173 display PWM driver support node") from https://github.com/mbgg/linux-mediatek.git v4.4-next/arm64 https://patchwork.kernel.org/patch/7880431/ ("dts: mt8173: Add iommu/smi nodes for mt8173") And to build: https://patchwork.kernel.org/patch/7880301/ ("dt-bindings: mediatek: Add smi dts binding") https://patchwork.kernel.org/patch/7880321/ ("memory: mediatek: Add SMI driver") CK Hu (5): dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding drm/mediatek: Add DRM Driver for Mediatek SoC MT8173. drm/mediatek: Add DSI sub driver arm64: dts: mt8173: Add display subsystem related nodes arm64: dts: mt8173: Add HDMI related nodes Jie Qiu (3): drm/mediatek: Add DPI sub driver drm/mediatek: Add HDMI support drm/mediatek: enable hdmi output control bit Philipp Zabel (5): dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding clk: mediatek: make dpi0_sel propagate rate changes clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation clk: mediatek: remove hdmitx_dig_cts from TOP clocks .../bindings/display/connector/hdmi-connector.txt | 1 + .../bindings/display/mediatek/mediatek,disp.txt | 203 +++++ .../bindings/display/mediatek/mediatek,dpi.txt | 35 + .../bindings/display/mediatek/mediatek,dsi.txt | 60 ++ .../bindings/display/mediatek/mediatek,hdmi.txt | 148 ++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 312 ++++++++ drivers/clk/mediatek/clk-mt8173.c | 8 +- drivers/clk/mediatek/clk-mtk.h | 7 +- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/mediatek/Kconfig | 22 + drivers/gpu/drm/mediatek/Makefile | 22 + drivers/gpu/drm/mediatek/mtk_cec.c | 245 ++++++ drivers/gpu/drm/mediatek/mtk_cec.h | 25 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 301 ++++++++ drivers/gpu/drm/mediatek/mtk_dpi.c | 737 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi.h | 84 ++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 ++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 603 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 32 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 41 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 275 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 148 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 581 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 55 ++ drivers/gpu/drm/mediatek/mtk_drm_fb.c | 165 ++++ drivers/gpu/drm/mediatek/mtk_drm_fb.h | 29 + drivers/gpu/drm/mediatek/mtk_drm_gem.c | 227 ++++++ drivers/gpu/drm/mediatek/mtk_drm_gem.h | 55 ++ drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c | 610 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 242 ++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 59 ++ drivers/gpu/drm/mediatek/mtk_dsi.c | 847 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.h | 58 ++ drivers/gpu/drm/mediatek/mtk_hdmi.c | 482 ++++++++++++ drivers/gpu/drm/mediatek/mtk_hdmi.h | 231 ++++++ drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c | 362 +++++++++ drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 768 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_hdmi_hw.h | 76 ++ drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 222 ++++++ drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 487 ++++++++++++ drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 506 ++++++++++++ include/dt-bindings/clock/mt8173-clk.h | 3 +- 44 files changed, 9955 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt create mode 100644 drivers/gpu/drm/mediatek/Kconfig create mode 100644 drivers/gpu/drm/mediatek/Makefile create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_hdmi_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_drv.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_hw.h create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c -- 2.6.2

2 18

[PATCH v3 00/10] Add DRM Driver for HiSilicon Kirin hi6220 SoC
by Xinliang Liu 03 Feb '16

03 Feb '16

This patch set adds a new drm driver for HiSilicon Kirin hi6220 SoC. Current testing and support board is Hikey board which is one of Linaro 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. Hardware Detail --------------- The display subsystem of Hi6220 SoC is shown as bellow: +-----+ +----------+ +-----+ +---------+ | | | | | | | | | FB |------>| ADE |---->| DSI |---->| External| | | | | | | | HDMI | +-----+ +----------+ +-----+ +---------+ - ADE(Advanced Display Engine) is the display controller. It contains 7 channels, 3 overlay compositors and a LDI. - A channel looks like: DMA-->clip-->scale-->ctrans(or called csc). - Overlay compositor is response to compose planes which come from 7 channels and pass composed image to LDI. - LDI is response to generate timings and RGB data stream. - DSI converts the RGB data stream from ADE to DSI packets. - External HDMI module is connected with DSI bus. Now Hikey use a ADI's ADV7533 external HDMI chip. Change History ------------- Changes in v3: - Move and rename all the files to kirin sub-directory. So that we could separate different seires SoCs' driver. - Make ade as the drm master node. - Replace drm_platform_init, load, unload implementation. - Use assigned-clocks to set clock rate. - Use ports to connect display relavant nodes. - Rename hisi_drm_dsi.c to dw_drm_dsi.c - Make encoder type as DRM_MODE_ENCODER_DSI. - A few cleanup on regs and code. Changes in v2: - Remove abtraction layer of plane/crtc/encoder/connector. - Refactor atomic implementation according to Daniel Vetter's guides: http://blog.ffwll.ch/2014/11/atomic-modeset-support-for-kms-drivers.html http://blog.ffwll.ch/2015/09/xdc-2015-atomic-modesetting-for-drivers.html http://blog.ffwll.ch/2015/08/atomic-modesetting-design-overview.html - Use bridge instead of slave encoder to connect external HDMI. - Move dt binding docs to bindings/display/hisilicon directory. Xinliang Liu (10): drm/hisilicon: Add device tree binding for hi6220 display subsystem drm/hisilicon: Add hisilicon kirin drm master driver drm/hisilicon: Add crtc driver for ADE drm/hisilicon: Add plane driver for ADE drm/hisilicon: Add vblank driver for ADE drm/hisilicon: Add cma fbdev and hotplug drm/hisilicon: Add designware dsi encoder driver drm/hisilicon: Add designware dsi host driver drm/hisilicon: Add support for external bridge MAINTAINERS: Add maintainer for hisilicon DRM driver .../bindings/display/hisilicon/dw-dsi.txt | 60 ++ .../bindings/display/hisilicon/hisi-ade.txt | 56 ++ MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/hisilicon/Kconfig | 5 + drivers/gpu/drm/hisilicon/Makefile | 5 + drivers/gpu/drm/hisilicon/kirin/Kconfig | 10 + drivers/gpu/drm/hisilicon/kirin/Makefile | 5 + drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 845 ++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 ++ drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 280 ++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 1053 ++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 382 +++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 31 + 15 files changed, 2827 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt create mode 100644 drivers/gpu/drm/hisilicon/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/kirin/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h -- 1.9.1

2 12

[PATCH 1/4] drm/fsl-dcu: Cleanup vblank interrupt mask and status setting code
by Meng Yi 03 Feb '16

03 Feb '16

From: Jianwei Wang <jianwei.wang.chn(a)gmail.com> Switch update interrupt mask bit with regmap_update_bits, and clear interrupt status by writing 1 to relevant bit before setting mask in fsl_dcu_drm_irq_init function. Signed-off-by: JianWei Wang <jianwei.wang.chn(a)gmail.com> Signed-off-by: Meng Yi <meng.yi(a)nxp.com> --- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index fca97d3..cbef47c 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -38,21 +38,17 @@ static const struct regmap_config fsl_dcu_regmap_config = { static int fsl_dcu_drm_irq_init(struct drm_device *dev) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - unsigned int value; int ret; ret = drm_irq_install(dev, fsl_dev->irq); if (ret < 0) dev_err(dev->dev, "failed to install IRQ handler\n"); - ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0); + ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff); if (ret) dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); - ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); - if (ret) - dev_err(dev->dev, "read DCU_INT_MASK failed\n"); - value &= DCU_INT_MASK_VBLANK; - ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value); + ret = regmap_update_bits(fsl_dev->regmap, DCU_INT_MASK, + DCU_INT_MASK_VBLANK, ~DCU_INT_MASK_VBLANK); if (ret) dev_err(dev->dev, "set DCU_INT_MASK failed\n"); ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, @@ -143,14 +139,10 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - unsigned int value; int ret; - ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); - if (ret) - dev_err(dev->dev, "read DCU_INT_MASK failed\n"); - value &= ~DCU_INT_MASK_VBLANK; - ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value); + ret = regmap_update_bits(fsl_dev->regmap, DCU_INT_MASK, + DCU_INT_MASK_VBLANK, ~DCU_INT_MASK_VBLANK); if (ret) dev_err(dev->dev, "set DCU_INT_MASK failed\n"); return 0; @@ -160,14 +152,10 @@ static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - unsigned int value; int ret; - ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); - if (ret) - dev_err(dev->dev, "read DCU_INT_MASK failed\n"); - value |= DCU_INT_MASK_VBLANK; - ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value); + ret = regmap_update_bits(fsl_dev->regmap, DCU_INT_MASK, + DCU_INT_MASK_VBLANK, DCU_INT_MASK_VBLANK); if (ret) dev_err(dev->dev, "set DCU_INT_MASK failed\n"); } -- 2.1.0.27.g96db324

3 9

[PATCH 1/2] drm/fsl-dcu: fix register initialization
by Stefan Agner 03 Feb '16

03 Feb '16

The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for Vybrid) whereas the register enumeration start from 1 (1-10 for LS1021a and 1-9 for Vybrid). The loop started off from 0 for both iterations and initialized the number of layers inclusive, which is one layer too many. All extensively written registers seem to be unassigned, it seems that the write to those registers did not do any harm in practice. Signed-off-by: Stefan Agner <stefan(a)agner.ch> --- This two patches apply cleanly on top of my earlier DCU fixes patchset: https://lkml.org/lkml/2015/11/18/953 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index db69725..3c92889 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -169,8 +169,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) reg_num = LS1021A_LAYER_REG_NUM; else reg_num = VF610_LAYER_REG_NUM; - for (i = 0; i <= fsl_dev->soc->total_layer; i++) { - for (j = 0; j < reg_num; j++) + for (i = 0; i < fsl_dev->soc->total_layer; i++) { + for (j = 1; j <= reg_num; j++) regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0); } regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, -- 2.7.0

1 2

[PATCH] drm/dp/mst: deallocate payload on port destruction
by Harry Wentland 02 Feb '16

02 Feb '16

From: Mykola Lysenko <Mykola.Lysenko(a)amd.com> This is needed to properly deallocate port payload after downstream branch get unplugged. In order to do this unplugged MST topology should be preserved, to find first alive port on path to unplugged MST topology, and send payload deallocation request to branch device of found port. For this mstb and port kref's are used in reversed order to track when port and branch memory could be freed. Added additional functions to find appropriate mstb as described above. Signed-off-by: Mykola Lysenko <Mykola.Lysenko(a)amd.com> Reviewed-by: Harry Wentland <Harry.Wentland(a)amd.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 91 ++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index fc589265068b..5662e68ecccd 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -803,6 +803,18 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad) return mstb; } +static void drm_dp_free_mst_port(struct kref *kref); + +static void drm_dp_free_mst_branch_device(struct kref *kref) +{ + struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref); + if (mstb->port_parent) { + if (list_empty(&mstb->port_parent->next)) + kref_put(&mstb->port_parent->kref, drm_dp_free_mst_port); + } + kfree(mstb); +} + static void drm_dp_destroy_mst_branch_device(struct kref *kref) { struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref); @@ -810,6 +822,15 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) bool wake_tx = false; /* + * init kref again to be used by ports to remove mst branch when it is + * not needed anymore + */ + kref_init(kref); + + if (mstb->port_parent && list_empty(&mstb->port_parent->next)) + kref_get(&mstb->port_parent->kref); + + /* * destroy all ports - don't need lock * as there are no more references to the mst branch * device at this point. @@ -835,7 +856,8 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) if (wake_tx) wake_up(&mstb->mgr->tx_waitq); - kfree(mstb); + + kref_put(kref, drm_dp_free_mst_branch_device); } static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb) @@ -883,6 +905,7 @@ static void drm_dp_destroy_port(struct kref *kref) * from an EDID retrieval */ mutex_lock(&mgr->destroy_connector_lock); + kref_get(&port->parent->kref); list_add(&port->next, &mgr->destroy_connector_list); mutex_unlock(&mgr->destroy_connector_lock); schedule_work(&mgr->destroy_connector_work); @@ -1617,6 +1640,37 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, return 0; } +static struct drm_dp_mst_port *drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch *mstb) +{ + if (!mstb->port_parent) + return NULL; + + if (mstb->port_parent->mstb != mstb) + return mstb->port_parent; + + return drm_dp_get_last_connected_port_to_mstb(mstb->port_parent->parent); +} + +static struct drm_dp_mst_branch *drm_dp_get_last_connected_port_and_mstb(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_branch *mstb, + int *port_num) +{ + struct drm_dp_mst_branch *rmstb = NULL; + struct drm_dp_mst_port *found_port; + mutex_lock(&mgr->lock); + if (mgr->mst_primary) { + found_port = drm_dp_get_last_connected_port_to_mstb(mstb); + + if (found_port) { + rmstb = found_port->parent; + kref_get(&rmstb->kref); + *port_num = found_port->port_num; + } + } + mutex_unlock(&mgr->lock); + return rmstb; +} + static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int id, @@ -1624,13 +1678,18 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, { struct drm_dp_sideband_msg_tx *txmsg; struct drm_dp_mst_branch *mstb; - int len, ret; + int len, ret, port_num; u8 sinks[DRM_DP_MAX_SDP_STREAMS]; int i; + port_num = port->port_num; mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); - if (!mstb) - return -EINVAL; + if (!mstb) { + mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num); + + if (!mstb) + return -EINVAL; + } txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) { @@ -1642,7 +1701,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, sinks[i] = i; txmsg->dst = mstb; - len = build_allocate_payload(txmsg, port->port_num, + len = build_allocate_payload(txmsg, port_num, id, pbn, port->num_sdp_streams, sinks); @@ -2787,6 +2846,13 @@ static void drm_dp_tx_work(struct work_struct *work) mutex_unlock(&mgr->qlock); } +static void drm_dp_free_mst_port(struct kref *kref) +{ + struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref); + kref_put(&port->parent->kref, drm_dp_free_mst_branch_device); + kfree(port); +} + static void drm_dp_destroy_connector_work(struct work_struct *work) { struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work); @@ -2807,13 +2873,22 @@ static void drm_dp_destroy_connector_work(struct work_struct *work) list_del(&port->next); mutex_unlock(&mgr->destroy_connector_lock); + kref_init(&port->kref); + INIT_LIST_HEAD(&port->next); + mgr->cbs->destroy_connector(mgr, port->connector); drm_dp_port_teardown_pdt(port, port->pdt); - if (!port->input && port->vcpi.vcpi > 0) - drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); - kfree(port); + if (!port->input && port->vcpi.vcpi > 0) { + if (mgr->mst_state) { + drm_dp_mst_reset_vcpi_slots(mgr, port); + drm_dp_update_payload_part1(mgr); + drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); + } + } + + kref_put(&port->kref, drm_dp_free_mst_port); send_hotplug = true; } if (send_hotplug) -- 2.1.4

2 1

[PATCH v2 0/2] Add a DRM display driver to the Allwinner H3
by Jean-Francois Moine 02 Feb '16

02 Feb '16

The proposed DRM driver works on a Orange PI 2 with a kernel 4.4.0 and the H3 patches found in Hans de Goede's GIT repository. As there is no documentation about the HDMI of the H3, the associated encoder/connector driver has not been included in this patch series. For tests, it may be built as a out-of-tree driver from the tarball: http://moinejf.free.fr/opi2/h3-hdmi.tar.gz and the DT files: http://moinejf.free.fr/opi2/sun8i-h3.dtsi http://moinejf.free.fr/opi2/sun8i-h3-orangepi-plus.dts Jean-Francois Moine (2): clk: sunxi: Add sun6i/8i video support drm: sunxi: Add a basic DRM driver for Allwinner DE2 Documentation/devicetree/bindings/clock/sunxi.txt | 2 + .../devicetree/bindings/display/sunxi.txt | 81 ++++ drivers/clk/sunxi/clk-sun6i-display.c | 106 +++++ drivers/clk/sunxi/clk-sun6i-pll3.c | 174 ++++++++ drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/sunxi/Kconfig | 20 + drivers/gpu/drm/sunxi/Makefile | 7 + drivers/gpu/drm/sunxi/de2_crtc.c | 425 +++++++++++++++++++ drivers/gpu/drm/sunxi/de2_crtc.h | 43 ++ drivers/gpu/drm/sunxi/de2_de.c | 461 +++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_drm.h | 55 +++ drivers/gpu/drm/sunxi/de2_drv.c | 376 +++++++++++++++++ drivers/gpu/drm/sunxi/de2_plane.c | 114 +++++ 14 files changed, 1867 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sunxi.txt create mode 100644 drivers/clk/sunxi/clk-sun6i-display.c create mode 100644 drivers/clk/sunxi/clk-sun6i-pll3.c create mode 100644 drivers/gpu/drm/sunxi/Kconfig create mode 100644 drivers/gpu/drm/sunxi/Makefile create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h create mode 100644 drivers/gpu/drm/sunxi/de2_de.c create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c -- 2.7.0

2 6

[PATCH RFC 0/2] Add a display driver to the Allwinner H3
by Jean-Francois Moine 02 Feb '16

02 Feb '16

The proposed DRM driver works on a Orange PI 2 with a kernel 4.4-rc1 and the H3 patches found in Hans de Goede's GIT repository. As there is no documentation about the DE2 nor about the HDMI which are found in the H3, this driver has been built from Allwiiner's sources. So, there may be license problems, especially for the file de2_hdmi_h3.c which contains a lot of magic values. The associated DT and documentation will be submitted when the H3 DTs will be in the kernel. Jean-Francois Moine (2): clk: sunxi: Add sun8i display support drm: sunxi: Add a basic DRM driver for Allwinner DE2 drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-sun8i-display.c | 257 ++++++++++++++++++ drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/sunxi/Kconfig | 21 ++ drivers/gpu/drm/sunxi/Makefile | 8 + drivers/gpu/drm/sunxi/de2_crtc.c | 409 +++++++++++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_crtc.h | 42 +++ drivers/gpu/drm/sunxi/de2_de.c | 467 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_drm.h | 51 ++++ drivers/gpu/drm/sunxi/de2_drv.c | 376 ++++++++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_hdmi.c | 381 +++++++++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_hdmi.h | 34 +++ drivers/gpu/drm/sunxi/de2_hdmi_h3.c | 478 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sunxi/de2_hdmi_h3.h | 14 + drivers/gpu/drm/sunxi/de2_plane.c | 102 ++++++++ 16 files changed, 2644 insertions(+) create mode 100644 drivers/clk/sunxi/clk-sun8i-display.c create mode 100644 drivers/gpu/drm/sunxi/Kconfig create mode 100644 drivers/gpu/drm/sunxi/Makefile create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h create mode 100644 drivers/gpu/drm/sunxi/de2_de.c create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.c create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.h create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_h3.c create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_h3.h create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c -- 2.6.4

5 17

[PATCH 00/10] android sync framework: clean up IOCTLs and ABI.
by Gustavo Padovan 02 Feb '16

02 Feb '16

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> Hi, This patch series clean up IOCTLs and abi of sync framework and it is a follow up on the clean up series I've sent on Jan 21: http://thread.gmane.org/gmane.comp.video.dri.devel/145509 The main changes here are: * remove of SYNC_WAIT ioctl, poll() should be used instead. * rename some structs and macros to better reflect the new internal names. * clean up and improve ABI on SYNC_IOC_FILE_INFO * add flags filed to all ABI structs Please review, thanks! Gustavo Padovan (10): staging/android: remove SYNC_WAIT ioctl staging/android: rename sync_pt_info to fence_info staging/android: rename sync_file_info_data to sync_file_info staging/android: remove driver_data from struct fence_info staging/android: remove len field from struct fence_info staging/android: turn fence_info into a __64 pointer staging/android: add num_fences field to struct sync_file_info staging/android: rename SYNC_IOC_FENCE_INFO staging/android: add flags member to sync ioctl structs staging/android: remove redundant comments on sync_merge_data drivers/staging/android/sw_sync.c | 14 ----- drivers/staging/android/sync.c | 113 +++++++---------------------------- drivers/staging/android/sync.h | 20 ------- drivers/staging/android/trace/sync.h | 44 -------------- drivers/staging/android/uapi/sync.h | 45 +++++++------- 5 files changed, 40 insertions(+), 196 deletions(-) -- 2.5.0

3 17

[PATCH 0/4] virtio-gpu: Fixes for atomic support
by Rob Herring 01 Feb '16

01 Feb '16

Dave, This series is the minimal changes to get virtio-gpu working with Android DRM based hwcomposer. The first 3 patches are fixes, but I assume they are only hit if using the atomic APIs which is dependent on the 4th patch. I suspect async commit support is also missing, but Android doesn't seem to need it. I also have a few more patches for fb emulation to support panning and mmapping the framebuffer. I'm not too sure that is really worth supporting though. Rob Rob Herring (4): drm: virtio-gpu: get the fb from the plane state for atomic updates drm: virtio-gpu: ensure plane is flushed to host on atomic update drm: virtio-gpu: transfer dumb buffers to host on plane update drm: virtio-gpu: set atomic flag drivers/gpu/drm/virtio/virtgpu_drv.c | 2 +- drivers/gpu/drm/virtio/virtgpu_plane.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) -- 2.5.0

2 6

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel January 2016