dri-devel April 2016

dri-devel@lists.freedesktop.org

197 participants
1285 discussions

[PATCH] drm/ttm: Fix TTM BO accounting
by Alex Deucher 12 Apr '16

12 Apr '16

From: Felix Kuehling <Felix.Kuehling(a)amd.com> TTM BO accounting is out of sync with how memory is really allocated in ttm[_dma]_tt_alloc_page_directory. This resulted in excessive estimated overhead with many small allocations. ttm_dma_tt_alloc_page_directory makes a single allocation for three arrays: pages, DMA and CPU addresses. It uses drm_calloc_large, which uses kmalloc internally for allocations smaller than PAGE_SIZE. ttm_round_pot should be a good approximation of its memory usage both above and below PAGE_SIZE. Signed-off-by: Felix Kuehling <Felix.Kuehling(a)amd.com> Reviewed-by: Monk Liu <monk.liu(a)amd.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 4cbf265..870a87a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1215,7 +1215,7 @@ size_t ttm_bo_acc_size(struct ttm_bo_device *bdev, size_t size = 0; size += ttm_round_pot(struct_size); - size += PAGE_ALIGN(npages * sizeof(void *)); + size += ttm_round_pot(npages * sizeof(void *)); size += ttm_round_pot(sizeof(struct ttm_tt)); return size; } @@ -1229,8 +1229,7 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev, size_t size = 0; size += ttm_round_pot(struct_size); - size += PAGE_ALIGN(npages * sizeof(void *)); - size += PAGE_ALIGN(npages * sizeof(dma_addr_t)); + size += ttm_round_pot(npages * (2*sizeof(void *) + sizeof(dma_addr_t))); size += ttm_round_pot(sizeof(struct ttm_dma_tt)); return size; } -- 2.5.5

3 3

[PATCH] drm/core: Add drm_accurate_vblank_count_and_time.
by Maarten Lankhorst 12 Apr '16

12 Apr '16

This function is useful for gen2 intel devices which have no frame counter, but need a way to determine the current vblank count without racing with the vblank interrupt handler. intel_pipe_update_start checks if no vblank interrupt will occur during vblank evasion, but cannot check whether the vblank handler has run to completion. This function uses the timestamps to determine when the last vblank has happened, and interpolates from there. Cc: Mario Kleiner <mario.kleiner.de(a)gmail.com> Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> --- Unfortunately only compile time tested, I don't have a gen2 to test with. drivers/gpu/drm/drm_irq.c | 90 +++++++++++++++++++++++++++++++++++------------ include/drm/drmP.h | 2 ++ 2 files changed, 69 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 881c5a6c180c..44d8f9607ccd 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -155,24 +155,10 @@ static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe spin_unlock(&dev->vblank_time_lock); } -/** - * drm_update_vblank_count - update the master vblank counter - * @dev: DRM device - * @pipe: counter to update - * - * Call back into the driver to update the appropriate vblank counter - * (specified by @pipe). Deal with wraparound, if it occurred, and - * update the last read value so we can deal with wraparound on the next - * call if necessary. - * - * Only necessary when going from off->on, to account for frames we - * didn't get an interrupt for. - * - * Note: caller must hold dev->vbl_lock since this reads & writes - * device vblank fields. - */ -static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, - unsigned long flags) +static u32 __drm_accurate_vblank_count_and_time(struct drm_device *dev, unsigned int pipe, + const struct timeval *t_old, + unsigned long flags, u32 *pdiff, + struct timeval *tv_ret) { struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; u32 cur_vblank, diff; @@ -202,10 +188,8 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, /* trust the hw counter when it's around */ diff = (cur_vblank - vblank->last) & dev->max_vblank_count; } else if (rc && framedur_ns) { - const struct timeval *t_old; u64 diff_ns; - t_old = &vblanktimestamp(dev, pipe, vblank->count); diff_ns = timeval_to_ns(&t_vblank) - timeval_to_ns(t_old); /* @@ -286,9 +270,13 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, " current=%u, diff=%u, hw=%u hw_last=%u\n", pipe, vblank->count, diff, cur_vblank, vblank->last); + *pdiff = diff; + *tv_ret = t_vblank; + if (diff == 0) { WARN_ON_ONCE(cur_vblank != vblank->last); - return; + + return cur_vblank; } /* @@ -298,9 +286,65 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, * for now, to mark the vblanktimestamp as invalid. */ if (!rc && (flags & DRM_CALLED_FROM_VBLIRQ) == 0) - t_vblank = (struct timeval) {0, 0}; + *tv_ret = (struct timeval) {0, 0}; + + return cur_vblank; +} + +/** + * drm_accurate_vblank_count_and_time - retrieve the master vblank counter + * @crtc: which counter to retrieve + * @tv_ret: last time counter was updated + * + * This function is similar to @drm_update_vblank_count_and_time but + * this function interpolates to handle a race with vblank irq's, and + * is only useful for crtc's that have no hw vblank counter. + */ + +u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc, + struct timeval *tv_ret) +{ + struct drm_device *dev = crtc->dev; + u32 pdiff, old_vblank; + struct timeval tv_old = {}; + + WARN(dev->max_vblank_count, "This function is only useful when a hw counter is unavailable."); + + old_vblank = drm_crtc_vblank_count_and_time(crtc, &tv_old); + + __drm_accurate_vblank_count_and_time(dev, drm_crtc_index(crtc), + &tv_old, 0, &pdiff, tv_ret); + + return old_vblank + pdiff; +} +EXPORT_SYMBOL(drm_accurate_vblank_count_and_time); + +/** + * drm_update_vblank_count - update the master vblank counter + * @dev: DRM device + * @pipe: counter to update + * + * Call back into the driver to update the appropriate vblank counter + * (specified by @pipe). Deal with wraparound, if it occurred, and + * update the last read value so we can deal with wraparound on the next + * call if necessary. + * + * Only necessary when going from off->on, to account for frames we + * didn't get an interrupt for. + * + * Note: caller must hold dev->vbl_lock since this reads & writes + * device vblank fields. + */ +static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, + unsigned long flags) +{ + u32 diff, cur_vblank, old_vblank = dev->vblank[pipe].count; + struct timeval t_vblank; + const struct timeval *tv_old = &vblanktimestamp(dev, pipe, old_vblank); - store_vblank(dev, pipe, diff, &t_vblank, cur_vblank); + cur_vblank = __drm_accurate_vblank_count_and_time(dev, pipe, tv_old, flags, &diff, &t_vblank); + if (diff) + store_vblank(dev, pipe, diff, &t_vblank, cur_vblank); } /* diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 31483c2fef51..1df65922c7c6 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -995,6 +995,8 @@ extern void drm_crtc_vblank_off(struct drm_crtc *crtc); extern void drm_crtc_vblank_reset(struct drm_crtc *crtc); extern void drm_crtc_vblank_on(struct drm_crtc *crtc); extern void drm_vblank_cleanup(struct drm_device *dev); +extern u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc, + struct timeval *tv_ret); extern u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe); extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, -- 2.1.0

3 10

[GIT PULL] exynos-drm-fixes
by Inki Dae 12 Apr '16

12 Apr '16

HI Dave, This pull request includes several regression fixups. Please kindly let me know if there is any problem. Thanks, Inki Dae The following changes since commit 928815245cbdaa611873424759d5e7a7293dd18b: Merge tag 'drm-intel-fixes-2016-04-07' of git://anongit.freedesktop.org/drm-intel into drm-fixes (2016-04-11 13:30:05 +1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git exynos-drm-fixes for you to fetch changes up to 2072fe51466f86e1f0eedf12bff7106913807efc: drm/exynos: Use VIDEO_SAMSUNG_S5P_G2D=n as G2D Kconfig dependency (2016-04-13 00:23:49 +0900) ---------------------------------------------------------------- Andrzej Hajda (2): drm/exynos: fix adjusted_mode pointer in exynos_plane_mode_set drm/exynos: build fbdev code conditionally Arnd Bergmann (1): drm/exynos: fix error handling in exynos_drm_subdrv_open Dan Carpenter (2): drm/exynos: mic: fix an error code drm/exynos: fix a warning message Javier Martinez Canillas (1): drm/exynos: Use VIDEO_SAMSUNG_S5P_G2D=n as G2D Kconfig dependency Marek Szyprowski (1): drm/exynos: fimd: fix broken dp_clock control drivers/gpu/drm/exynos/Kconfig | 2 +- drivers/gpu/drm/exynos/Makefile | 6 +++--- drivers/gpu/drm/exynos/exynos_drm_core.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_fb.c | 11 ----------- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 11 +++++++++++ drivers/gpu/drm/exynos/exynos_drm_fbdev.h | 23 ++++++++++++++++++++++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_mic.c | 3 ++- drivers/gpu/drm/exynos/exynos_drm_plane.c | 12 +++++++----- 9 files changed, 48 insertions(+), 24 deletions(-)

1 0

[PATCH] drm/amdgpu: handle more than 10 UVD sessions (v2)
by Christian König 12 Apr '16

12 Apr '16

From: Arindam Nath <arindam.nath(a)amd.com> Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath(a)amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu(a)amd.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 30 ++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +++-- .../gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 1 + 6 files changed, 41 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 36afabb..4805e45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1592,16 +1592,19 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev); /* * UVD */ -#define AMDGPU_MAX_UVD_HANDLES 10 -#define AMDGPU_UVD_STACK_SIZE (1024*1024) -#define AMDGPU_UVD_HEAP_SIZE (1024*1024) -#define AMDGPU_UVD_FIRMWARE_OFFSET 256 +#define AMDGPU_DEFAULT_UVD_HANDLES 10 +#define AMDGPU_MAX_UVD_HANDLES 40 +#define AMDGPU_UVD_STACK_SIZE (200*1024) +#define AMDGPU_UVD_HEAP_SIZE (256*1024) +#define AMDGPU_UVD_SESSION_SIZE (50*1024) +#define AMDGPU_UVD_FIRMWARE_OFFSET 256 struct amdgpu_uvd { struct amdgpu_bo *vcpu_bo; void *cpu_addr; uint64_t gpu_addr; void *saved_bo; + unsigned max_handles; atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; struct delayed_work idle_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 338da80..76ebc10 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -151,6 +151,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) return r; } + /* Set the default UVD handles that the firmware can handle */ + adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; family_id = le32_to_cpu(hdr->ucode_version) & 0xff; version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; @@ -158,8 +161,19 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", version_major, version_minor, family_id); + /* + * Limit the number of UVD handles depending on microcode major + * and minor versions. The firmware version which has 40 UVD + * instances support is 1.80. So all subsequent versions should + * also have the same support. + */ + if ((version_major > 0x01) || + ((version_major == 0x01) && (version_minor >= 0x50))) + adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; + bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) - + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; + + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE + + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, @@ -202,7 +216,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) return r; } - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { atomic_set(&adev->uvd.handles[i], 0); adev->uvd.filp[i] = NULL; } @@ -248,7 +262,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) if (adev->uvd.vcpu_bo == NULL) return 0; - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) if (atomic_read(&adev->uvd.handles[i])) break; @@ -303,7 +317,7 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) struct amdgpu_ring *ring = &adev->uvd.ring; int i, r; - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { uint32_t handle = atomic_read(&adev->uvd.handles[i]); if (handle != 0 && adev->uvd.filp[i] == filp) { struct fence *fence; @@ -563,7 +577,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, amdgpu_bo_kunmap(bo); /* try to alloc a new handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { if (atomic_read(&adev->uvd.handles[i]) == handle) { DRM_ERROR("Handle 0x%x already in use!\n", handle); return -EINVAL; @@ -586,7 +600,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, return r; /* validate the handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + for (i = 0; i < adev->uvd.max_handles; ++i) { if (atomic_read(&adev->uvd.handles[i]) == handle) { if (adev->uvd.filp[i] != ctx->parser->filp) { DRM_ERROR("UVD handle collision detected!\n"); @@ -601,7 +615,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, case 2: /* it's a destroy msg, free the handle */ - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); amdgpu_bo_kunmap(bo); return 0; @@ -1013,7 +1027,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) fences = amdgpu_fence_count_emitted(&adev->uvd.ring); - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + for (i = 0; i < adev->uvd.max_handles; ++i) if (atomic_read(&adev->uvd.handles[i])) ++handles; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index cb46375..0d6b9e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -559,12 +559,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); addr += size; - size = AMDGPU_UVD_STACK_SIZE >> 3; + size = AMDGPU_UVD_HEAP_SIZE >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); addr += size; - size = AMDGPU_UVD_HEAP_SIZE >> 3; + size = (AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 16476d8..24f03d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -271,12 +271,13 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_UVD_STACK_SIZE; + size = AMDGPU_UVD_HEAP_SIZE; WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_UVD_HEAP_SIZE; + size = AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index d493791..b06cae6 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -270,18 +270,21 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_UVD_STACK_SIZE; + size = AMDGPU_UVD_HEAP_SIZE; WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_UVD_HEAP_SIZE; + size = AMDGPU_UVD_STACK_SIZE + + (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE2, size); WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + + WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); } static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h index b2d4aaf..6f6fb34 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h @@ -111,5 +111,6 @@ #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 #define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 #define mmUVD_JPEG_ADDR_CONFIG 0x3a1f +#define mmUVD_GP_SCRATCH4 0x3d38 #endif /* UVD_6_0_D_H */ -- 1.9.1

3 3

[PATCH] drm/msm/mdp: Add support for more RGBX formats
by Rob Herring 12 Apr '16

12 Apr '16

Android needs XBGR8888 format. Add all the missing 32-bpp formats without alpha for completeness. Cc: Archit Taneja <architt(a)codeaurora.org> Cc: Rob Clark <robdclark(a)gmail.com> Signed-off-by: Rob Herring <robh(a)kernel.org> --- drivers/gpu/drm/msm/mdp/mdp_format.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c b/drivers/gpu/drm/msm/mdp/mdp_format.c index 1c2caff..b4a8aa4 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_format.c +++ b/drivers/gpu/drm/msm/mdp/mdp_format.c @@ -105,6 +105,12 @@ static const struct mdp_format formats[] = { MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4, MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), + FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), + FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), + FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3, MDP_PLANE_INTERLEAVED, CHROMA_FULL, false), FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3, -- 2.5.0

2 1

[PATCH 1/2] drm/radeon: add support for loading new UVD fw
by Leo Liu 12 Apr '16

12 Apr '16

From: Arindam Nath <arindam.nath(a)amd.com> Signed-off-by: Christian König <christian.koenig(a)amd.com> Signed-off-by: Arindam Nath <arindam.nath(a)amd.com> Reviewed-by: Leo Liu <leo.liu(a)amd.com> --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_uvd.c | 55 +++++++++++++++++++++++++++---------- drivers/gpu/drm/radeon/uvd_v4_2.c | 8 +++++- 3 files changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 78a51b3..34694ad 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1674,6 +1674,7 @@ int radeon_pm_get_type_index(struct radeon_device *rdev, #define RADEON_UVD_HEAP_SIZE (1024*1024) struct radeon_uvd { + bool fw_header_present; struct radeon_bo *vcpu_bo; void *cpu_addr; uint64_t gpu_addr; diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6edcb54..0897c66 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c @@ -34,6 +34,7 @@ #include <drm/drm.h> #include "radeon.h" +#include "radeon_ucode.h" #include "r600d.h" /* 1 second timeout */ @@ -47,7 +48,8 @@ #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" -#define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" +#define FIRMWARE_BONAIRE_LEGACY "radeon/BONAIRE_uvd.bin" +#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" MODULE_FIRMWARE(FIRMWARE_R600); MODULE_FIRMWARE(FIRMWARE_RS780); @@ -56,6 +58,7 @@ MODULE_FIRMWARE(FIRMWARE_RV710); MODULE_FIRMWARE(FIRMWARE_CYPRESS); MODULE_FIRMWARE(FIRMWARE_SUMO); MODULE_FIRMWARE(FIRMWARE_TAHITI); +MODULE_FIRMWARE(FIRMWARE_BONAIRE_LEGACY); MODULE_FIRMWARE(FIRMWARE_BONAIRE); static void radeon_uvd_idle_work_handler(struct work_struct *work); @@ -63,7 +66,7 @@ static void radeon_uvd_idle_work_handler(struct work_struct *work); int radeon_uvd_init(struct radeon_device *rdev) { unsigned long bo_size; - const char *fw_name; + const char *fw_name = NULL, *legacy_fw_name = NULL; int i, r; INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); @@ -74,22 +77,22 @@ int radeon_uvd_init(struct radeon_device *rdev) case CHIP_RV670: case CHIP_RV620: case CHIP_RV635: - fw_name = FIRMWARE_R600; + legacy_fw_name = FIRMWARE_R600; break; case CHIP_RS780: case CHIP_RS880: - fw_name = FIRMWARE_RS780; + legacy_fw_name = FIRMWARE_RS780; break; case CHIP_RV770: - fw_name = FIRMWARE_RV770; + legacy_fw_name = FIRMWARE_RV770; break; case CHIP_RV710: case CHIP_RV730: case CHIP_RV740: - fw_name = FIRMWARE_RV710; + legacy_fw_name = FIRMWARE_RV710; break; case CHIP_CYPRESS: @@ -97,7 +100,7 @@ int radeon_uvd_init(struct radeon_device *rdev) case CHIP_JUNIPER: case CHIP_REDWOOD: case CHIP_CEDAR: - fw_name = FIRMWARE_CYPRESS; + legacy_fw_name = FIRMWARE_CYPRESS; break; case CHIP_SUMO: @@ -107,7 +110,7 @@ int radeon_uvd_init(struct radeon_device *rdev) case CHIP_BARTS: case CHIP_TURKS: case CHIP_CAICOS: - fw_name = FIRMWARE_SUMO; + legacy_fw_name = FIRMWARE_SUMO; break; case CHIP_TAHITI: @@ -115,7 +118,7 @@ int radeon_uvd_init(struct radeon_device *rdev) case CHIP_PITCAIRN: case CHIP_ARUBA: case CHIP_OLAND: - fw_name = FIRMWARE_TAHITI; + legacy_fw_name = FIRMWARE_TAHITI; break; case CHIP_BONAIRE: @@ -123,6 +126,7 @@ int radeon_uvd_init(struct radeon_device *rdev) case CHIP_KAVERI: case CHIP_HAWAII: case CHIP_MULLINS: + legacy_fw_name = FIRMWARE_BONAIRE_LEGACY; fw_name = FIRMWARE_BONAIRE; break; @@ -130,11 +134,34 @@ int radeon_uvd_init(struct radeon_device *rdev) return -EINVAL; } - r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); - if (r) { - dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", - fw_name); - return r; + rdev->uvd.fw_header_present = false; + if (fw_name) { + /* Let's try to load the newer firmware first */ + r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); + if (r) { + dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", + fw_name); + } else { + r = radeon_ucode_validate(rdev->uvd_fw); + if (r) + return r; + + rdev->uvd.fw_header_present = true; + } + } + + /* + * In case there is only legacy firmware, or we encounter an error + * while loading the new firmware, we fall back to loading the legacy + * firmware now. + */ + if (!fw_name || r) { + r = request_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev); + if (r) { + dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", + legacy_fw_name); + return r; + } } bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + diff --git a/drivers/gpu/drm/radeon/uvd_v4_2.c b/drivers/gpu/drm/radeon/uvd_v4_2.c index d04d507..205562f 100644 --- a/drivers/gpu/drm/radeon/uvd_v4_2.c +++ b/drivers/gpu/drm/radeon/uvd_v4_2.c @@ -41,7 +41,13 @@ int uvd_v4_2_resume(struct radeon_device *rdev) uint32_t size; /* programm the VCPU memory controller bits 0-27 */ - addr = rdev->uvd.gpu_addr >> 3; + + /* skip over the header of the new firmware format */ + if (rdev->uvd.fw_header_present) + addr = (rdev->uvd.gpu_addr + 0x200) >> 3; + else + addr = rdev->uvd.gpu_addr >> 3; + size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; WREG32(UVD_VCPU_CACHE_OFFSET0, addr); WREG32(UVD_VCPU_CACHE_SIZE0, size); -- 1.9.1

3 3

Re: tgsi: add support for buffer/atomic operations to tgsi_exec
by Dieter Nützel 12 Apr '16

12 Apr '16

Warning during compilation after git pull: tgsi/tgsi_exec.c: In function 'exec_atomop_buf': tgsi/tgsi_exec.c:4060:8: warning: array subscript is above array bounds [-Warray-bounds] r[3].f[j] = rgba[3][j]; ^ Any hints where I should look? Dieter

1 0

[PATCH] drm/core: Fix ordering in drm_mode_config_cleanup.
by Maarten Lankhorst 12 Apr '16

12 Apr '16

__drm_atomic_helper_plane_destroy_state calls drm_framebuffer_unreference, which means that if drm_framebuffer_free is called before plane->destroy freed memory will be accessed. A similar case happens for the blob list, which was freed before the crtc state was, resulting in the unreference_blob from crtc_destroy_state pointing to garbage memory causing another opportunity for a GPF. Signed-off-by: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> --- drivers/gpu/drm/drm_crtc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 51c5a00ffdff..5a13b1afccbe 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -5958,6 +5958,15 @@ void drm_mode_config_cleanup(struct drm_device *dev) drm_property_destroy(dev, property); } + list_for_each_entry_safe(plane, plt, &dev->mode_config.plane_list, + head) { + plane->funcs->destroy(plane); + } + + list_for_each_entry_safe(crtc, ct, &dev->mode_config.crtc_list, head) { + crtc->funcs->destroy(crtc); + } + list_for_each_entry_safe(blob, bt, &dev->mode_config.property_blob_list, head_global) { drm_property_unreference_blob(blob); @@ -5976,15 +5985,6 @@ void drm_mode_config_cleanup(struct drm_device *dev) drm_framebuffer_free(&fb->refcount); } - list_for_each_entry_safe(plane, plt, &dev->mode_config.plane_list, - head) { - plane->funcs->destroy(plane); - } - - list_for_each_entry_safe(crtc, ct, &dev->mode_config.crtc_list, head) { - crtc->funcs->destroy(crtc); - } - ida_destroy(&dev->mode_config.connector_ida); idr_destroy(&dev->mode_config.tile_idr); idr_destroy(&dev->mode_config.crtc_idr); -- 2.1.0

3 4

[RFC 0/5] drm: Add support for tiny LCD displays
by Noralf Trønnes 12 Apr '16

12 Apr '16

This is an attempt at providing a DRM version of drivers/staging/fbtft. I'm sending this early before cleaning up the code hoping to get some feedback in case there are better ways to structure this. The tinydrm module provides a very simplified view of DRM for displays that has onboard video memory and is connected through a slow bus like SPI/I2C. A driver using tinydrm has to provide a function that will be called from the dirtyfb ioctl and optionally drm_panel functions which can be used to set up the display controller and control backlight. tinydrm also has fbdev support using fb_deferred_io which is tied in through the dirtyfb function call. A driver can use the provided deferred work code to collect dirtyfb calls and schedule display memory updates if it whishes. The various display controllers can have library modules that handles display updates. Display controllers that have a similar register interface as the MIPI DBI/DCS controllers can use the lcdreg module for register access. struct tinydrm_device { struct drm_device *base; u32 width, height; struct drm_panel panel; [...] int (*dirtyfb)(struct drm_framebuffer *fb, void *vmem, unsigned flags, unsigned color, struct drm_clip_rect *clips, unsigned num_clips); }; +------------------------------+---------+ | | fbdev | | DRM +------+ | | | | +-------------------------------------+--+ | | | tinydrm | | | +------------------+ . . . . . . . | | | deferred work | | Display driver +---------------------+ | | Controller module | +------------------+---------------------+ | lcdreg | +----------------------------------------+ | Interface (SPI, I2C, parallel) | +----------------------------------------+ Noralf Trønnes (5): drm: Add DRM support for tiny LCD displays drm/tinydrm: Add lcd register abstraction drm/tinydrm/lcdreg: Add SPI support drm/tinydrm: Add mipi-dbi support drm/tinydrm: Add support for several Adafruit TFT displays drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/tinydrm/Kconfig | 27 + drivers/gpu/drm/tinydrm/Makefile | 8 + drivers/gpu/drm/tinydrm/adafruit-tft.c | 256 ++++++++ drivers/gpu/drm/tinydrm/core/Makefile | 8 + drivers/gpu/drm/tinydrm/core/internal.h | 43 ++ drivers/gpu/drm/tinydrm/core/tinydrm-core.c | 194 ++++++ drivers/gpu/drm/tinydrm/core/tinydrm-crtc.c | 203 ++++++ drivers/gpu/drm/tinydrm/core/tinydrm-deferred.c | 116 ++++ drivers/gpu/drm/tinydrm/core/tinydrm-fbdev.c | 345 ++++++++++ drivers/gpu/drm/tinydrm/core/tinydrm-framebuffer.c | 112 ++++ drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c | 97 +++ drivers/gpu/drm/tinydrm/core/tinydrm-plane.c | 50 ++ drivers/gpu/drm/tinydrm/lcdreg/Kconfig | 8 + drivers/gpu/drm/tinydrm/lcdreg/Makefile | 5 + drivers/gpu/drm/tinydrm/lcdreg/internal.h | 8 + drivers/gpu/drm/tinydrm/lcdreg/lcdreg-core.c | 190 ++++++ drivers/gpu/drm/tinydrm/lcdreg/lcdreg-debugfs.c | 281 ++++++++ drivers/gpu/drm/tinydrm/lcdreg/lcdreg-spi.c | 720 +++++++++++++++++++++ drivers/gpu/drm/tinydrm/mipi-dbi.c | 231 +++++++ include/drm/tinydrm/ili9340.h | 85 +++ include/drm/tinydrm/lcdreg-spi.h | 63 ++ include/drm/tinydrm/lcdreg.h | 126 ++++ include/drm/tinydrm/mipi-dbi.h | 24 + include/drm/tinydrm/tinydrm.h | 142 ++++ 26 files changed, 3345 insertions(+) create mode 100644 drivers/gpu/drm/tinydrm/Kconfig create mode 100644 drivers/gpu/drm/tinydrm/Makefile create mode 100644 drivers/gpu/drm/tinydrm/adafruit-tft.c create mode 100644 drivers/gpu/drm/tinydrm/core/Makefile create mode 100644 drivers/gpu/drm/tinydrm/core/internal.h create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-core.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-crtc.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-deferred.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-fbdev.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-framebuffer.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-plane.c create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/Kconfig create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/Makefile create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/internal.h create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/lcdreg-core.c create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/lcdreg-debugfs.c create mode 100644 drivers/gpu/drm/tinydrm/lcdreg/lcdreg-spi.c create mode 100644 drivers/gpu/drm/tinydrm/mipi-dbi.c create mode 100644 include/drm/tinydrm/ili9340.h create mode 100644 include/drm/tinydrm/lcdreg-spi.h create mode 100644 include/drm/tinydrm/lcdreg.h create mode 100644 include/drm/tinydrm/mipi-dbi.h create mode 100644 include/drm/tinydrm/tinydrm.h -- 2.2.2

4 22

[PATCH 0/7] drm/exynos: HDMI and DECON fixes and enhancements
by Andrzej Hajda 12 Apr '16

12 Apr '16

Hi Inki, This set of patches provides set of different fixes and enhancements for DECON -> HDMI path. It is based on: - my HDMI patches which are not yet merged[1], could you look at them by the way, they were posted about 5 months ago :) - IOMMU patches by Marek (for some mysterious reason HDMI path on 5433 works only with IOMMU enabled), - latest exynos-drm-next patches. [1]: http://permalink.gmane.org/gmane.comp.video.dri.devel/140109 Regards Andrzej Andrzej Hajda (7): drm/exynos/hdmi: fix PHY configuration sequence drm/exynos/hdmi: add PHY power off signal handling drm/exynos/hdmi: add core reset code drm/exynos/hdmi: remove registry dump drm/exynos/decon5433: fix DECON standalone update drm/exynos/decon5433: reset decon on start drm/exynos/decon5433: do not protect window in plane disable drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 22 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 293 ++------------------------ 2 files changed, 29 insertions(+), 286 deletions(-) -- 1.9.1

2 12

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel April 2016