dri-devel June 2016

dri-devel@lists.freedesktop.org

231 participants
1446 discussions

[PULL] drm-intel-next
by Daniel Vetter 07 Jun '16

07 Jun '16

Hi Dave, drm-intel-next-2016-06-06: - some polish for the guc code (Dave Gordon) - big refactoring of gen9 display clock handling code (Ville) - refactoring work in the context code (Chris Wilson) - give encoder/crtc/planes useful names for debug output (Ville) - improvements to skl/kbl wm computation code (Mahesh Kumar) - bunch of smaller improvements all over as usual Cheers, Daniel The following changes since commit 66fd7a66e8b9e11e49f46ea77910f935c4dee5c3: Merge branch 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel into drm-next (2016-06-02 07:58:36 +1000) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-2016-06-06 for you to fetch changes up to 1750d59dfa3caf1fc5354a2217f0e83d717c9b22: drm/i915: Update DRIVER_DATE to 20160606 (2016-06-06 00:29:53 +0200) ---------------------------------------------------------------- - some polish for the guc code (Dave Gordon) - big refactoring of gen9 display clock handling code (Ville) - refactoring work in the context code (Chris Wilson) - give encoder/crtc/planes useful names for debug output (Ville) - improvements to skl/kbl wm computation code (Mahesh Kumar) - bunch of smaller improvements all over as usual ---------------------------------------------------------------- Ander Conselvan de Oliveira (1): drm/i915: Fix NULL pointer deference when out of PLLs in IVB Chris Wilson (14): drm/i915/opregion: Convert to using native drm_i915_private drm/i915/opregion: Rename init/fini functions to register/unregister drm/i915: Rename struct intel_context drm/i915: Apply lockdep annotations to i915_gem_context.c drm/i915: Rename and inline i915_gem_context_get() drm/i915: Name the inner most per-engine intel_context struct drm/i915: Move pinning of dev_priv->kernel_context into its creator drm/i915: Show i915_gem_context owner in debugfs drm/i915: Put the kernel_context in drm_i915_private next to its friends drm/i915: Merge legacy+execlists context structs drm/i915: Rearrange i915_gem_context drm/i915/debugfs: Show context objects in i915_gem_objects drm/i915: Only ignore eDP ports that are connected drm/i915: Silence "unexpected child device config size" for VBT on 845g Clint Taylor (1): drm/i915/skl: SKL CDCLK change on modeset tracking VCO Daniel Vetter (3): drm/i915: Revert async unpin and nonblocking atomic commit Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued drm/i915: Update DRIVER_DATE to 20160606 Dave Gordon (6): drm/i915/guc: rename loader entry points drm/i915/guc: distinguish HAS_GUC() from HAS_GUC_UCODE/HAS_GUC_SCHED drm/i915/guc: add enable_guc_loading parameter drm/i915/guc: pass request (not client) to i915_guc_{wq_check_space, submit}() drm/i915/guc: don't spinwait if the GuC's workqueue is full drm/i915/guc: rework guc_add_workqueue_item() Imre Deak (2): drm/i915/gen9: Assume CDCLK PLL is off if it's not locked drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume Kumar, Mahesh (3): drm/i915/skl+: calculate ddb minimum allocation (v6) drm/i915/skl+: calculate plane pixel rate (v4) drm/i915/skl+: Use scaling amount for plane data rate calculation (v4) Lyude (1): drm/i915/ilk: Don't disable SSC source if it's in use Matt Roper (1): drm/i915: Don't try to calculate relative data rates during hw readout Sagar Arun Kamble (1): drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled Tvrtko Ursulin (1): drm/i915/guc: Disable automatic GuC firmware loading Ville Syrjälä (31): drm/i915: Enable GSE interrupt on BDW+ drm/i915: Fix BXT min_pixclk after state readout drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config() drm/i915: Extract skl_calc_cdclk() drm/i915: Actually read out DPLL0 vco on skl from hardware drm/i915: Report the current DPLL0 vco on SKL/KBL drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL drm/i915: Keep track of preferred cdclk vco frequency on SKL drm/i915: Beef up skl_sanitize_cdclk() a bit drm/i915: Unify SKL cdclk init paths drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL drm/i915: Rename skl_vco_freq to cdclk_pll.vco drm/i915: Store cdclk PLL reference clock under dev_priv drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk() drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv drm/i915: Update cached cdclk state from broxton_init_cdclk() drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check drm/i915: Set BXT cdclk to minimum initially drm/i915: Assert the dbuf is enabled when disabling DC5/6 drm/i915: Reject modeset if the dotclock is too high drm/i915: Use crtc->name in debug messages drm/i915: Use plane->name in debug prints drm/i915: Set crtc->name to "pipe A", "pipe B", etc. drm/i915: Don't leak primary/cursor planes on crtc init failure drm/i915: Give meaningful names to all the planes drm/i915: Give encoders useful names drm/i915: kill STANDARD/CURSOR plane screams drm/i915: Extract physical display dimensions from VBT drivers/gpu/drm/i915/i915_debugfs.c | 106 ++-- drivers/gpu/drm/i915/i915_dma.c | 12 +- drivers/gpu/drm/i915/i915_drv.c | 18 +- drivers/gpu/drm/i915/i915_drv.h | 104 ++-- drivers/gpu/drm/i915/i915_gem.c | 17 +- drivers/gpu/drm/i915/i915_gem_context.c | 209 +++---- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 +- drivers/gpu/drm/i915/i915_guc_submission.c | 167 +++--- drivers/gpu/drm/i915/i915_irq.c | 30 +- drivers/gpu/drm/i915/i915_params.c | 14 +- drivers/gpu/drm/i915/i915_params.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_sysfs.c | 2 +- drivers/gpu/drm/i915/i915_trace.h | 12 +- drivers/gpu/drm/i915/intel_bios.c | 9 +- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 863 ++++++++++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 41 +- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 38 +- drivers/gpu/drm/i915/intel_drv.h | 9 +- drivers/gpu/drm/i915/intel_dsi.c | 5 +- drivers/gpu/drm/i915/intel_dvo.c | 18 +- drivers/gpu/drm/i915/intel_fbdev.c | 4 +- drivers/gpu/drm/i915/intel_guc.h | 37 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 3 +- drivers/gpu/drm/i915/intel_guc_loader.c | 153 +++-- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 145 ++--- drivers/gpu/drm/i915/intel_lrc.h | 9 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_opregion.c | 105 ++-- drivers/gpu/drm/i915/intel_pm.c | 176 ++++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 56 +- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 16 +- drivers/gpu/drm/i915/intel_tv.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 2 +- drivers/gpu/drm/i915/intel_vbt_defs.h | 7 +- 41 files changed, 1467 insertions(+), 957 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

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[PATCH v3] drm/dsi: Implement set tear scanline
by Vinay Simha BN 07 Jun '16

07 Jun '16

Provide a small convenience wrapper that transmits a set_tear_scanline command. Cc: Archit Taneja <archit.taneja(a)gmail.com> Cc: John Stultz <john.stultz(a)linaro.org> Cc: Thierry Reding <thierry.reding(a)gmail.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Signed-off-by: Vinay Simha BN <simhavcs(a)gmail.com> -- v1: * helper function suggested by Thierry for set_tear_scanline * Also includes small build fixes from Sumit Semwal. v2: * one scanline parameter suggested by jani v3: * passing the payload properly as suggested by jani -- --- drivers/gpu/drm/drm_mipi_dsi.c | 22 ++++++++++++++++++++++ include/drm/drm_mipi_dsi.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index f5d8083..7938ce7 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -983,6 +983,28 @@ int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_on); /** + * mipi_dsi_set_tear_scanline() - turn on the display module's Tearing Effect + * output signal on the TE signal line when display module reaches line N + * defined by STS[n:0]. + * @dsi: DSI peripheral device + * @param: STS[10:0] + * Return: 0 on success or a negative error code on failure + */ +int mipi_dsi_set_tear_scanline(struct mipi_dsi_device *dsi, u16 param) +{ + u8 payload[3] = { MIPI_DCS_SET_TEAR_SCANLINE, param >> 8, + param & 0xff }; + ssize_t err; + + err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_set_tear_scanline); + +/** * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image * data used by the interface * @dsi: DSI peripheral device diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 7a9840f..ec55285 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -263,6 +263,7 @@ int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, u16 end); int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, u16 end); +int mipi_dsi_set_tear_scanline(struct mipi_dsi_device *dsi, u16 param); int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi); int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, enum mipi_dsi_dcs_tear_mode mode); -- 2.1.2

4 3

[PATCH] drm/fb_cma_helper: Implement fb_mmap callback
by Robin Murphy 07 Jun '16

07 Jun '16

In the absence of an fb_mmap callback, the fbdev code falls back to a naive implementation which relies upon the DMA address being the same as the physical address, and the buffer being physically contiguous from there. Whilst this often holds for standard CMA allocations via the platform's regular DMA ops, if the allocation is provided by an IOMMU then such assumptions can fall apart spectacularly. To resolve this, reroute the fb_mmap call to the appropriate DMA API implementation, as per the other cma_helper calls. Acked-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> Signed-off-by: Robin Murphy <robin.murphy(a)arm.com> --- Resending rebased to 4.7-rc1 with Daniel's ack. I know Russell raised some concerns about the general way fb_cma_helper uses fb_info[1], but AFAICS that's a longstanding separate problem orthogonal to this patch. Robin. [1]:http://thread.gmane.org/gmane.comp.video.dri.devel/149288 drivers/gpu/drm/drm_fb_cma_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index 172cafe11c71..a25afc068d3f 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -23,6 +23,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_fb_cma_helper.h> +#include <linux/dma-mapping.h> #include <linux/module.h> #define DEFAULT_FBDEFIO_DELAY_MS 50 @@ -297,6 +298,12 @@ int drm_fb_cma_debugfs_show(struct seq_file *m, void *arg) EXPORT_SYMBOL_GPL(drm_fb_cma_debugfs_show); #endif +static int drm_fb_cma_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + return dma_mmap_writecombine(info->device, vma, info->screen_base, + info->fix.smem_start, info->fix.smem_len); +} + static struct fb_ops drm_fbdev_cma_ops = { .owner = THIS_MODULE, .fb_fillrect = drm_fb_helper_sys_fillrect, @@ -307,6 +314,7 @@ static struct fb_ops drm_fbdev_cma_ops = { .fb_blank = drm_fb_helper_blank, .fb_pan_display = drm_fb_helper_pan_display, .fb_setcmap = drm_fb_helper_setcmap, + .fb_mmap = drm_fb_cma_mmap, }; static int drm_fbdev_cma_deferred_io_mmap(struct fb_info *info, -- 2.8.1.dirty

3 4

[PATCH v6 0/4] drm/omapdrm: gamma table support + drm_crtc_enable_color_mgmt()
by Jyri Sarha 07 Jun '16

07 Jun '16

Implements gamma tables for OMAP4, OMAP5, and dra7xx SoCs and adds a workaround for errata that may break LCD1 channel if gamma tables are in use. Also adds new drm_crtc_enable_color_mgmt() as suggested[1] by Daniel Vetter and get rid of the old drm_helper_crtc_enable_color_mgmt(). I have not tested the change to i915 driver, only compiled it, but functionally it should be exactly the same. [1] http://www.spinics.net/lists/dri-devel/msg108092.html Changes from v5 to v6 - Rebased on top of Tomi's 4.8/omapdrm branch (git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git 4.8/omapdrm) - "drm: drm_helper_crtc_enable_color_mgmt() => drm_crtc_enable_color_mgmt()" - No change - "drm/omapdrm: Add gamma table support to DSS dispc" - Don't crash to gamma table with lenght < 2 - Deal with input table size > output table size, in interpolation code - "drm/omapdrm: Workaround for errata i734 (LCD1 Gamma) in DSS dispc" - No change - "drm/omapdrm: Implement gamma_lut atomic crtc properties" - Add "omap_crtc_atomic_check()" - Restore default gamma table if the gamma_lut property is removed Changes from v4 to v5 - No code changes - Reorder the patches so that color_mgmt-patch comes first - Fix some typos from commit descriptions - Squash: "drm: Add drm_crtc_enable_color_mgmt()", "drm/i915: Use drm_crtc_enable_color_mgmt()", and "drm: Remove obsolete drm_helper_crtc_enable_color_mgmt()" to: "drm: drm_helper_crtc_enable_color_mgmt() => drm_crtc_enable_color_mgmt()" - Squash: "drm/omapdrm: Use drm_crtc_enable_color_mgmt() to enable gamma properties" into: "drm/omapdrm: Implement gamma_lut atomic crtc properties" Changes from v3 to v4 - "drm/omapdrm: Add gamma table support to DSS dispc" - use interpolation code in dispc_mgr_set_gamma() to produce default lut - restore default lut table if NULL is given as gamma lut table - "drm/omapdrm: Implement gamma_lut atomic crtc property" - attach gamma_lut_property and gamma_lut_size_property to crtc if gamma tables are supported - restore default table if gamma lut property is deleted - Adds: - drm: Add drm_crtc_enable_color_mgmt() - drm/omapdrm: Use drm_crtc_enable_color_mgmt() to enable gamma properties - drm/i915: Use drm_crtc_enable_color_mgmt() - drm: Remove obsolete drm_helper_crtc_enable_color_mgmt() Changes from v2 to v3 - "drm/omapdrm: Add gamma table support to DSS dispc" - fix dispc_init_gamma_tables() to always return an int - omap54xx_dispc_feats initializes .has_gamma_table not .has_gamma_tables - "drm/omapdrm: Work-a-round for errata i734 (LCD1 Gamma) in DSS dispc" - work-a-round -> workaround - Do not mention LOADMODE in description - dma_alloc_writecombine returns NULL on error - fix last wrong instrance of LCD output gating register - improve comment for framedone busy wait - add {} around busy loop's while statement Changes from v1 to v2 - Drop "drm/omapdrm: omap_modeset_init: Separate crtc id and plane id indexing" - "drm/omapdrm: Add gamma table support to DSS dispc" - Address Tomi's comments here: https://patchwork.kernel.org/patch/9128629/ - "drm/omapdrm: Work-a-round for errata i734 (LCD1 Gamma) in DSS dispc" - Address Tomi's comments here: https://patchwork.kernel.org/patch/9128633/ Jyri Sarha (4): drm: drm_helper_crtc_enable_color_mgmt() => drm_crtc_enable_color_mgmt() drm/omapdrm: Add gamma table support to DSS dispc drm/omapdrm: Workaround for errata i734 (LCD1 Gamma) in DSS dispc drm/omapdrm: Implement gamma_lut atomic crtc properties drivers/gpu/drm/drm_crtc.c | 45 ++++ drivers/gpu/drm/drm_crtc_helper.c | 33 --- drivers/gpu/drm/i915/intel_color.c | 3 +- drivers/gpu/drm/omapdrm/dss/dispc.c | 377 ++++++++++++++++++++++++++++++++-- drivers/gpu/drm/omapdrm/dss/dispc.h | 5 + drivers/gpu/drm/omapdrm/dss/hdmi4.c | 3 - drivers/gpu/drm/omapdrm/dss/hdmi5.c | 3 - drivers/gpu/drm/omapdrm/dss/omapdss.h | 5 + drivers/gpu/drm/omapdrm/omap_crtc.c | 56 +++++ include/drm/drm_crtc.h | 5 +- include/drm/drm_crtc_helper.h | 3 - 11 files changed, 478 insertions(+), 60 deletions(-) -- 1.9.1

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[PATCH] drm/i915/ilk: Disable SSC for DPLLs if we're not using it
by Lyude 07 Jun '16

07 Jun '16

Thanks to Ville Syrjälä for pointing me towards the cause of this issue. Unfortunately one of the sideaffects of having the refclk for a DPLL set to SSC is that as long as it's set to SSC, the GPU will prevent us from powering down any of the pipes or transcoders using it. A couple of BIOSes, despite the fact they don't actually need it, enable SSC both in PCH_DREF_CONTROL and on the DPLL configurations. This causes issues on the first modeset, since we don't expect SSC to be left on and as a result, can't successfully power down the pipes or the transcoders using it. Here's an example from this Dell OptiPlex 990: [drm:intel_modeset_init] SSC enabled by BIOS, overriding VBT which says disabled [drm:intel_modeset_init] 2 display pipes available. [drm:intel_update_cdclk] Current CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [drm:intel_crt_reset] crt adpa set to 0xf40000 [drm:intel_dp_init_connector] Adding DP connector on port C [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1 [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0 [drm:ironlake_init_pch_refclk] Disabling SSC entirely … later we try committing the first modeset … [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88041b02e800 for pipe A [drm:intel_dump_pipe_config] cpu_transcoder: A … [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4016001, dpll_md: 0x0, fp0: 0x20e08, fp1: 0x30d07 [drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [drm:intel_dump_pipe_config] FB:42, fb = 800x600 format = 0x34325258 [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 800x600 dst (0, 0) 800x600 [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [drm:intel_get_shared_dpll] CRTC:26 allocated PCH DPLL A [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [drm:ilk_audio_codec_disable] Disable audio codec on port C, pipe A [drm:intel_disable_pipe] disabling pipe A ------------[ cut here ]------------ WARNING: CPU: 1 PID: 130 at drivers/gpu/drm/i915/intel_display.c:1146 intel_disable_pipe+0x297/0x2d0 [i915] pipe_off wait timed out … ---[ end trace 94fc8aa03ae139e8 ]--- [drm:intel_dp_link_down] [drm:ironlake_crtc_disable [i915]] *ERROR* failed to disable transcoder A Later modesets succeed since they reset the DPLL's configuration anyway, but this is enough to get stuck with a big fat warning in dmesg. Normally we'd need to add some sort of ref counting mechanism to the CRTCs so we avoid accidentally trying to shut off a shared resource, but since ignore what the BIOS does anyway and we shut off the refclks before any modesets, this workaround should suffice for now. Cc: stable(a)vger.kernel.org Signed-off-by: Lyude <cpaul(a)redhat.com> --- drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d500e6f..3fb6025 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8230,7 +8230,8 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_encoder *encoder; - u32 val, final; + int i; + u32 val, temp, final; bool has_lvds = false; bool has_cpu_edp = false; bool has_panel = false; @@ -8369,6 +8370,22 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) I915_WRITE(PCH_DREF_CONTROL, val); POSTING_READ(PCH_DREF_CONTROL); udelay(200); + + /* Unset SSC as the refclk for all of the DPLLs */ + for (i = 0; i < dev_priv->num_shared_dpll; i++) { + temp = I915_READ(PCH_DPLL(i)); + + if (!(temp & PLLB_REF_INPUT_SPREADSPECTRUMIN)) + continue; + + DRM_DEBUG_KMS("Disabling SSC refclk for %s\n", + dev_priv->shared_dplls[i].name); + + /* Change refclk to DREFCLK */ + temp &= ~PLL_REF_INPUT_MASK; + + I915_WRITE(PCH_DPLL(i), temp); + } } BUG_ON(val != final); -- 2.5.5

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[PATCH] drm/imx: check the value returned by regulator_set_voltage()
by Fabio Estevam 07 Jun '16

07 Jun '16

regulator_set_voltage() may fail, so we better check its return value and propagate it in the case of error. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- drivers/gpu/drm/imx/imx-tve.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c index baf7881..c93301c 100644 --- a/drivers/gpu/drm/imx/imx-tve.c +++ b/drivers/gpu/drm/imx/imx-tve.c @@ -633,7 +633,9 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) tve->dac_reg = devm_regulator_get(dev, "dac"); if (!IS_ERR(tve->dac_reg)) { - regulator_set_voltage(tve->dac_reg, 2750000, 2750000); + ret = regulator_set_voltage(tve->dac_reg, 2750000, 2750000); + if (ret) + return ret; ret = regulator_enable(tve->dac_reg); if (ret) return ret; -- 1.9.1

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[PATCH v4 0/2] sti: add audio interface to the hdmi driver
by Arnaud Pouliquen 07 Jun '16

07 Jun '16

This patchset implements audio interface in HDMI drm driver. Implementation is based on ASoC generic hdmi codec driver( https://patchwork.kernel.org/patch/8713141/). It also proposes helper functions to compute N and CTS parameters according to HDMI 1.4b specification. V4: fixes for "video: hdmi: add helper functions for N and CTS" - typo error and additional comments - cts_1_ratio computation - warning reported by kbuild test robot - add rounded value for 297/1.001 MHz V3: - video: hdmi: add helper function for N and CTS Also used on Mediatek platform (https://patchwork.kernel.org/patch/8887341) delta vs V2: - typo fixes - if/else code optimisation - drm: sti: Add ASoC generic hdmi codec support. - typo fixes - add audio registers in debugfs information V2: RFC https://patchwork.kernel.org/patch/8091531/("video: hdmi: add helper function for N and CTS") https://patchwork.kernel.org/patch/8091561/("ASoC: hdmi-codec: Add hdmi-codec for external HDMI-encoders") - patch: video: hdmi: add helper function for N and CTS Fixes based on Russel King remarks - Duplicate function to have a separte treatment for coherent and non-coherent clocks - Add ratio field for alternate CTS value - Clock frequency in Hz for TMDS and audio clocks - Add information concerning clocks and CTS calculation. V1: This RFC is the implementation of audio HDMI on sti platform based on generic hdmi-codec driver: https://patchwork.kernel.org/patch/7215271/ ("ASoC: hdmi-codec: Add hdmi-codec for external HDMI-encoders") https://patchwork.kernel.org/patch/8062611/ ("video: hdmi: add helper function for N and CTS") Arnaud Pouliquen (2): video: hdmi: add helper functions for N and CTS drm: sti: Add ASoC generic hdmi codec support. drivers/gpu/drm/sti/Kconfig | 1 + drivers/gpu/drm/sti/sti_hdmi.c | 248 ++++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/sti/sti_hdmi.h | 13 +++ drivers/video/hdmi.c | 208 ++++++++++++++++++++++++++++++++++ include/linux/hdmi.h | 24 ++++ 5 files changed, 477 insertions(+), 17 deletions(-) -- 1.9.1

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[PATCH 1/2] drm/amdgpu: add return value for pci config reset
by Alex Deucher 07 Jun '16

07 Jun '16

From: Chunming Zhou <David1.Zhou(a)amd.com> So we know whether or not the reset succeeded. Signed-off-by: Chunming Zhou <David1.Zhou(a)amd.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/cik.c | 14 ++++++++++---- drivers/gpu/drm/amd/amdgpu/vi.c | 12 +++++++----- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 07bc795..924c85c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1152,10 +1152,11 @@ static void kv_restore_regs_for_reset(struct amdgpu_device *adev, WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); } -static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) +static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) { struct kv_reset_save_regs kv_save = { 0 }; u32 i; + int r = -EINVAL; dev_info(adev->dev, "GPU pci config reset\n"); @@ -1171,14 +1172,18 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) + if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { + r = 0; break; + } udelay(1); } /* does asic init need to be run first??? */ if (adev->flags & AMD_IS_APU) kv_restore_regs_for_reset(adev, &kv_save); + + return r; } static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) @@ -1204,13 +1209,14 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu */ static int cik_asic_reset(struct amdgpu_device *adev) { + int r; cik_set_bios_scratch_engine_hung(adev, true); - cik_gpu_pci_config_reset(adev); + r = cik_gpu_pci_config_reset(adev); cik_set_bios_scratch_engine_hung(adev, false); - return 0; + return r; } static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 38bcc05..dcc937e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -583,7 +583,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } -static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) +static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) { u32 i; @@ -599,10 +599,10 @@ static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) - break; + return 0; udelay(1); } - + return -EINVAL; } static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) @@ -628,13 +628,15 @@ static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hun */ static int vi_asic_reset(struct amdgpu_device *adev) { + int r; + vi_set_bios_scratch_engine_hung(adev, true); - vi_gpu_pci_config_reset(adev); + r = vi_gpu_pci_config_reset(adev); vi_set_bios_scratch_engine_hung(adev, false); - return 0; + return r; } static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, -- 2.5.5

1 1

[Bug 96423] radeonfb: BAR 0: can't reserve [mem 0x98000000-0x9fffffff pref]
by bugzilla-daemon＠freedesktop.org 07 Jun '16

07 Jun '16

https://bugs.freedesktop.org/show_bug.cgi?id=96423 Bug ID: 96423 Summary: radeonfb: BAR 0: can't reserve [mem 0x98000000-0x9fffffff pref] Product: DRI Version: XOrg git Hardware: PowerPC OS: All Status: NEW Severity: normal Priority: medium Component: DRM/Radeon Assignee: dri-devel(a)lists.freedesktop.org Reporter: mathieu.malaterre(a)gmail.com On a PowerPC machine, when Open Firmware Frame Buffer is used (OFfb), I cannot `modprobe radeonfb` (but I can load `radeon`). It currently fails with: [ 96.551486] radeonfb 0000:00:10.0: enabling device (0006 -> 0007) [ 96.551526] radeonfb 0000:00:10.0: BAR 0: can't reserve [mem 0x98000000-0x9fffffff pref] [ 96.551531] radeonfb (0000:00:10.0): cannot request region 0. [ 96.551545] radeonfb: probe of 0000:00:10.0 failed with error -16 It seems (to me) that it should be possible to add something like this to `radeonfb`: https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/radeon/radeon… [...] /* Get rid of things like offb */ ret = radeon_kick_out_firmware_fb(pdev); if (ret) [...] -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH 0/4] Centralize format information
by Laurent Pinchart 07 Jun '16

07 Jun '16

Hello, Various pieces of information about DRM formats (number of planes, color depth, chroma subsampling, ...) are scattered across different helper functions in the DRM core. Callers of those functions often need to access more than a single parameter of the format, leading to inefficiencies due to multiple lookups. This patch series addresses this issue by centralizing all format information in a single data structure (1/4). It reimplements the existing format helper functions based on that structure (3/4) and converts the DRM core code to use the new structure (4/4). Two unused format helper functions are removed in the process (2/4). The new API is also useful for drivers. I will shortly post a patch series for the omapdrm driver that makes use of it. Laurent Pinchart (4): drm: Centralize format information drm: Remove unused drm_format_plane_(width|height) helpers drm: Implement the drm_format_*() helpers as drm_format_info() wrappers drm: Use drm_format_info() in DRM core code drivers/gpu/drm/drm_crtc.c | 391 +++++++++++------------------------- drivers/gpu/drm/drm_fb_cma_helper.c | 23 ++- include/drm/drm_crtc.h | 23 ++- 3 files changed, 153 insertions(+), 284 deletions(-) -- Regards, Laurent Pinchart

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