dri-devel August 2016

dri-devel@lists.freedesktop.org

239 participants
1433 discussions

[PATCH v5 0/6] Finally fix watermarks
by Lyude 03 Aug '16

03 Aug '16

Next version of https://patchwork.freedesktop.org/series/10276/ . Notable series-wide changes: - Added the following patches: - "drm/i915/skl: Ensure pipes with changed wms get added to the state" - "drm/i915: Move CRTC updating in atomic_commit into it's own hook" - "drm/i915/skl: Update DDB values atomically with wms/plane attrs" With this, we now actually fix all of the issues causing underruns instead of just working around them. - Since we now are fixing this issue instead of working around it, the following patches were no longer necessary: - "drm/i915/skl: Always wait for pipes to update after a flush" - "drm/i915/skl: Fix extra whitespace in skl_flush_wm_values()" Lyude (5): drm/i915/skl: Add support for the SAGV, fix underrun hangs drm/i915/skl: Update plane watermarks atomically during plane updates drm/i915/skl: Ensure pipes with changed wms get added to the state drm/i915: Move CRTC updating in atomic_commit into it's own hook drm/i915/skl: Update DDB values atomically with wms/plane attrs Matt Roper (1): drm/i915/gen9: Only copy WM results for changed pipes to skl_hw drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_display.c | 190 +++++++++++--- drivers/gpu/drm/i915/intel_drv.h | 17 ++ drivers/gpu/drm/i915/intel_pm.c | 467 +++++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_sprite.c | 6 + 6 files changed, 496 insertions(+), 193 deletions(-) -- 2.7.4

3 14

[PATCH] drm: rcar-du: Link HDMI encoder with bridge
by Laurent Pinchart 03 Aug '16

03 Aug '16

The conversion of the rcar-du driver from the I2C slave encoder to the DRM bridge API left the HDMI encoder's bridge pointer NULL, preventing the bridge from being handled automatically by the DRM core. Fix it. Fixes: 1d926114d8f4 ("drm: rcar-du: Remove i2c slave encoder interface for hdmi encoder") Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas(a)ideasonboard.com> --- drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c | 1 + 1 file changed, 1 insertion(+) Dave, this is a candidate for v4.8 as the offending patch just made it upstream during the merge window. diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c index 4de3ff0dbebd..e03004f4588d 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c @@ -125,6 +125,7 @@ int rcar_du_hdmienc_init(struct rcar_du_device *rcdu, /* Link drm_bridge to encoder */ bridge->encoder = encoder; + encoder->bridge = bridge; ret = drm_bridge_attach(rcdu->ddev, bridge); if (ret) { -- Regards, Laurent Pinchart

1 0

[RFC 0/3] drm: Add DRM text mode
by Noralf Trønnes 03 Aug '16

03 Aug '16

This patchset explores the idea of adding a DRM text mode (like VGA text mode) to get an alternative to fbcon/fbdev. David Hermann has done alot of work on a fbcon replacement: - drm: add kernel-log renderer (Mar 2014)[1] - kmscon: development started Nov 2011 added to systemd Oct 2014 removed from systemd Jul 2015[2] Since this work seems to have stalled, I propose an alternative solution to this problem that will also give VT console support while we're waiting for a userspace console. The idea is that the driver provides a modeset like with the fbdev emulation code, and from this a text buffer representation is made. The console code can now write to this text buffer and ask for the text buffer to be flushed/rendered to the pixel buffer. In this hack/implementation of the idea, I have just hijacked a CMA backed fbdev framebuffer to keep it simple. I have reused the default buffer format that VT uses. Getting panic handling to actually work, seems to be a challenge as Daniel describes on the DRMJanitors page[3]. Is this idea of a DRM text mode worth developing further? Noralf. [1] https://lwn.net/Articles/589858/ [2] https://github.com/systemd/systemd/pull/747 [3] https://www.x.org/wiki/DRMJanitors/#makepanichandlingwork Noralf Trønnes (3): drm: Add support for text framebuffer drm/text: Add panic and boot console support drm/text: Add VT console support drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/drm-text/Makefile | 5 + drivers/gpu/drm/drm-text/drm-text-buffer.c | 340 ++++++++++++++++++++++++++++ drivers/gpu/drm/drm-text/drm-text-console.c | 205 +++++++++++++++++ drivers/gpu/drm/drm-text/drm-text-debugfs.c | 295 ++++++++++++++++++++++++ drivers/gpu/drm/drm-text/drm-text-vt.c | 197 ++++++++++++++++ drivers/gpu/drm/drm-text/drm-text.h | 99 ++++++++ 7 files changed, 1142 insertions(+) create mode 100644 drivers/gpu/drm/drm-text/Makefile create mode 100644 drivers/gpu/drm/drm-text/drm-text-buffer.c create mode 100644 drivers/gpu/drm/drm-text/drm-text-console.c create mode 100644 drivers/gpu/drm/drm-text/drm-text-debugfs.c create mode 100644 drivers/gpu/drm/drm-text/drm-text-vt.c create mode 100644 drivers/gpu/drm/drm-text/drm-text.h -- 2.8.2

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[PATCH 01/10] drm/nouveau: replace legacy vblank helpers
by Gustavo Padovan 03 Aug '16

03 Aug '16

From: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> Replace the legacy drm_send_vblank_event(), drm_arm_vblank_event() and drm_vblank_{get,put}() with the new helper functions. v2: add crtc to nouveau_page_flip_state (comment from Mario Kleiner) Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> Signed-off-by: Gustavo Padovan <gustavo.padovan(a)collabora.co.uk> --- drivers/gpu/drm/nouveau/nouveau_display.c | 22 +++++++++++----------- drivers/gpu/drm/nouveau/nouveau_display.h | 3 ++- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 7c77f96..6072fe2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -760,12 +760,11 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, /* Initialize a page flip struct */ *s = (struct nouveau_page_flip_state) - { { }, event, nouveau_crtc(crtc)->index, - fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, + { { }, event, crtc, fb->bits_per_pixel, fb->pitches[0], new_bo->bo.offset }; /* Keep vblanks on during flip, for the target crtc of this flip */ - drm_vblank_get(dev, nouveau_crtc(crtc)->index); + drm_crtc_vblank_get(crtc); /* Emit a page flip */ if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { @@ -810,7 +809,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, return 0; fail_unreserve: - drm_vblank_put(dev, nouveau_crtc(crtc)->index); + drm_crtc_vblank_put(crtc); ttm_bo_unreserve(&old_bo->bo); fail_unpin: mutex_unlock(&cli->mutex); @@ -842,17 +841,17 @@ nouveau_finish_page_flip(struct nouveau_channel *chan, s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); if (s->event) { if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { - drm_arm_vblank_event(dev, s->crtc, s->event); + drm_crtc_arm_vblank_event(s->crtc, s->event); } else { - drm_send_vblank_event(dev, s->crtc, s->event); + drm_crtc_send_vblank_event(s->crtc, s->event); /* Give up ownership of vblank for page-flipped crtc */ - drm_vblank_put(dev, s->crtc); + drm_crtc_vblank_put(s->crtc); } } else { /* Give up ownership of vblank for page-flipped crtc */ - drm_vblank_put(dev, s->crtc); + drm_crtc_vblank_put(s->crtc); } list_del(&s->head); @@ -873,9 +872,10 @@ nouveau_flip_complete(struct nvif_notify *notify) if (!nouveau_finish_page_flip(chan, &state)) { if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { - nv_set_crtc_base(drm->dev, state.crtc, state.offset + - state.y * state.pitch + - state.x * state.bpp / 8); + nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), + state.offset + state.crtc->y * + state.pitch + state.crtc->x * + state.bpp / 8); } } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 24273ba..0420ee8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -28,7 +28,8 @@ int nouveau_framebuffer_init(struct drm_device *, struct nouveau_framebuffer *, struct nouveau_page_flip_state { struct list_head head; struct drm_pending_vblank_event *event; - int crtc, bpp, pitch, x, y; + struct drm_crtc *crtc; + int bpp, pitch; u64 offset; }; -- 2.5.5

5 16

libdrm-armada repository
by Joshua Clayton 03 Aug '16

03 Aug '16

Greetings Russell, I'm publishing an etnaviv yocto layer on github. One of the components is libdrm-armada, which we get from git://ftp.arm.linux.org.uk/~rmk/libdrm-armada.git I don't want to put an unwanted extra burden on your server. I notice there is also http://git.arm.linux.org.uk/cgit/libdrm-armada.git or we can mirror it on github. Do you have a preference? Thanks Joshua Clayton

3 4

[PATCH 0210/1285] Replace numeric parameter like 0444 with macro
by Baole Ni 03 Aug '16

03 Aug '16

I find that the developers often just specified the numeric value when calling a macro which is defined with a parameter for access permission. As we know, these numeric value for access permission have had the corresponding macro, and that using macro can improve the robustness and readability of the code, thus, I suggest replacing the numeric parameter with the macro. Signed-off-by: Chuansheng Liu <chuansheng.liu(a)intel.com> Signed-off-by: Baole Ni <baolex.ni(a)intel.com> --- drivers/gpu/drm/qxl/qxl_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index dc9df5f..f62a099 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -51,10 +51,10 @@ static int qxl_modeset = -1; int qxl_num_crtc = 4; MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); -module_param_named(modeset, qxl_modeset, int, 0400); +module_param_named(modeset, qxl_modeset, int, S_IRUSR); MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)"); -module_param_named(num_heads, qxl_num_crtc, int, 0400); +module_param_named(num_heads, qxl_num_crtc, int, S_IRUSR); static struct drm_driver qxl_driver; static struct pci_driver qxl_pci_driver; -- 2.9.2

2 1

[PATCH v7] drm/i915/skl: Add support for the SAGV, fix underrun hangs
by Lyude 03 Aug '16

03 Aug '16

Since the watermark calculations for Skylake are still broken, we're apt to hitting underruns very easily under multi-monitor configurations. While it would be lovely if this was fixed, it's not. Another problem that's been coming from this however, is the mysterious issue of underruns causing full system hangs. An easy way to reproduce this with a skylake system: - Get a laptop with a skylake GPU, and hook up two external monitors to it - Move the cursor from the built-in LCD to one of the external displays as quickly as you can - You'll get a few pipe underruns, and eventually the entire system will just freeze. After doing a lot of investigation and reading through the bspec, I found the existence of the SAGV, which is responsible for adjusting the system agent voltage and clock frequencies depending on how much power we need. According to the bspec: "The display engine access to system memory is blocked during the adjustment time. SAGV defaults to enabled. Software must use the GT-driver pcode mailbox to disable SAGV when the display engine is not able to tolerate the blocking time." The rest of the bspec goes on to explain that software can simply leave the SAGV enabled, and disable it when we use interlaced pipes/have more then one pipe active. Sure enough, with this patchset the system hangs resulting from pipe underruns on Skylake have completely vanished on my T460s. Additionally, the bspec mentions turning off the SAGV with more then one pipe enabled as a workaround for display underruns. While this patch doesn't entirely fix that, it looks like it does improve the situation a little bit so it's likely this is going to be required to make watermarks on Skylake fully functional. Changes since v6: - Protect skl_enable_sagv() with intel_state->modeset conditional in intel_atomic_commit_tail() Changes since v5: - Don't use is_power_of_2. Makes things confusing - Don't use the old state to figure out whether or not to enable/disable the sagv, use the new one - Split the loop in skl_disable_sagv into it's own function - Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail() Changes since v4: - Use is_power_of_2 against active_crtcs to check whether we have > 1 pipe enabled - Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0 enabled - Call skl_sagv_enable/disable() from pre/post-plane updates Changes since v3: - Use time_before() to compare timeout to jiffies Changes since v2: - Really apply minor style nitpicks to patch this time Changes since v1: - Added comments about this probably being one of the requirements to fixing Skylake's watermark issues - Minor style nitpicks from Matt Roper - Disable these functions on Broxton, since it doesn't have an SAGV Reviewed-by: Matt Roper <matthew.d.roper(a)intel.com> Signed-off-by: Lyude <cpaul(a)redhat.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Cc: stable(a)vger.kernel.org fixup! drm/i915/skl: Add support for the SAGV, fix underrun hangs --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 5 ++ drivers/gpu/drm/i915/intel_display.c | 11 ++++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 112 +++++++++++++++++++++++++++++++++++ 5 files changed, 132 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 65ada5d..87018d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1962,6 +1962,8 @@ struct drm_i915_private { struct i915_suspend_saved_registers regfile; struct vlv_s0ix_state vlv_s0ix_state; + bool skl_sagv_enabled; + struct { /* * Raw watermark latency values: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f93d4a..5fb1c63 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7170,6 +7170,11 @@ enum { #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define DISPLAY_IPS_CONTROL 0x19 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A +#define GEN9_PCODE_SAGV_CONTROL 0x21 +#define GEN9_SAGV_DISABLE 0x0 +#define GEN9_SAGV_LOW_FREQ 0x1 +#define GEN9_SAGV_HIGH_FREQ 0x2 +#define GEN9_SAGV_DYNAMIC_FREQ 0x3 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a8e8cc8..f4caf4c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13692,6 +13692,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) dev_priv->display.modeset_commit_cdclk(state); + /* + * SKL workaround: bspec recommends we disable the SAGV when we + * have more then one pipe enabled + */ + if (IS_SKYLAKE(dev_priv) && + hweight32(intel_state->active_crtcs) > 1) + skl_disable_sagv(dev_priv); + intel_modeset_verify_disabled(dev); } @@ -13765,6 +13773,9 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); } + if (intel_state->modeset && hweight32(intel_state->active_crtcs) <= 1) + skl_enable_sagv(dev_priv); + drm_atomic_helper_commit_hw_done(state); if (intel_state->modeset) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 50cdc89..6b0532a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1709,6 +1709,8 @@ void ilk_wm_get_hw_state(struct drm_device *dev); void skl_wm_get_hw_state(struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, struct skl_ddb_allocation *ddb /* out */); +int skl_enable_sagv(struct drm_i915_private *dev_priv); +int skl_disable_sagv(struct drm_i915_private *dev_priv); uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); bool ilk_disable_lp_wm(struct drm_device *dev); int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f610b71..68721a5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2884,6 +2884,116 @@ skl_wm_plane_id(const struct intel_plane *plane) } static void +skl_sagv_get_hw_state(struct drm_i915_private *dev_priv) +{ + u32 temp; + int ret; + + if (IS_BROXTON(dev_priv)) + return; + + mutex_lock(&dev_priv->rps.hw_lock); + ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL, &temp); + mutex_unlock(&dev_priv->rps.hw_lock); + + if (!ret) { + dev_priv->skl_sagv_enabled = !(temp & 0x1); + } else { + /* + * If for some reason we can't access the SAGV state, follow + * the bspec and assume it's enabled + */ + DRM_ERROR("Failed to get SAGV state, assuming enabled\n"); + dev_priv->skl_sagv_enabled = true; + } +} + +/* + * SAGV dynamically adjusts the system agent voltage and clock frequencies + * depending on power and performance requirements. The display engine access + * to system memory is blocked during the adjustment time. Having this enabled + * in multi-pipe configurations can cause issues (such as underruns causing + * full system hangs), and the bspec also suggests that software disable it + * when more then one pipe is enabled. + */ +int +skl_enable_sagv(struct drm_i915_private *dev_priv) +{ + int ret; + + if (IS_BROXTON(dev_priv)) + return 0; + if (dev_priv->skl_sagv_enabled) + return 0; + + mutex_lock(&dev_priv->rps.hw_lock); + DRM_DEBUG_KMS("Enabling the SAGV\n"); + + ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, + GEN9_SAGV_DYNAMIC_FREQ); + if (!ret) + dev_priv->skl_sagv_enabled = true; + else + DRM_ERROR("Failed to enable the SAGV\n"); + + /* We don't need to wait for SAGV when enabling */ + mutex_unlock(&dev_priv->rps.hw_lock); + return ret; +} + +static int +skl_do_sagv_disable(struct drm_i915_private *dev_priv) +{ + int ret; + uint32_t temp; + + ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, + GEN9_SAGV_DISABLE); + if (ret) { + DRM_ERROR("Failed to disable the SAGV\n"); + return ret; + } + + ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL, + &temp); + if (ret) { + DRM_ERROR("Failed to check the status of the SAGV\n"); + return ret; + } + + return temp & 0x1; +} + +int +skl_disable_sagv(struct drm_i915_private *dev_priv) +{ + int ret, result; + + if (IS_BROXTON(dev_priv)) + return 0; + if (!dev_priv->skl_sagv_enabled) + return 0; + + mutex_lock(&dev_priv->rps.hw_lock); + DRM_DEBUG_KMS("Disabling the SAGV\n"); + + /* bspec says to keep retrying for at least 1 ms */ + ret = wait_for(result = skl_do_sagv_disable(dev_priv), 1); + mutex_unlock(&dev_priv->rps.hw_lock); + + if (ret == -ETIMEDOUT) + DRM_ERROR("Request to disable SAGV timed out\n"); + else { + if (result == 1) + dev_priv->skl_sagv_enabled = false; + + ret = result; + } + + return ret; +} + +static void skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, const struct intel_crtc_state *cstate, struct skl_ddb_entry *alloc, /* out */ @@ -4236,6 +4346,8 @@ void skl_wm_get_hw_state(struct drm_device *dev) /* Easy/common case; just sanitize DDB now if everything off */ memset(ddb, 0, sizeof(*ddb)); } + + skl_sagv_get_hw_state(dev_priv); } static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) -- 2.7.4

2 1

[PATCH 00/10] drm/edid: Clean up display_info stuff
by ville.syrjala＠linux.intel.com 03 Aug '16

03 Aug '16

From: Ville Syrjälä <ville.syrjala(a)linux.intel.com> This series aims to clean up the way we fill out the display_info structure a bit. Mainly doing a clean separation of the audio and video related bits. My aim is getting i915 to respect the HDMI sink TMDS clock limit (currently we respect only the DP++ dongle limit, and the source limit). But while doing that, I noticed that the display_info stuff was a bit of mess, hence it resulted in this bigger series. Entire series available here: git://github.com/vsyrjala/linux.git hdmi_sink_tmds_limit_3 Ville Syrjälä (10): drm/edid: Clear old audio latency values before parsing the new EDID drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new EDID drm/edid: Make max_tmds_clock kHz instead of MHz drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info drm/edid: Don't pass around drm_display_info needlessly drm/edid: Reduce the number of times we parse the CEA extension block drm/edid: Clear the old cea_rev when there's no CEA extension in the new EDID drm/edid: Move dvi_dual/max_tmds_clock parsing out from drm_edid_to_eld() drm/i915: Replace a bunch of connector->base.display_info with a local variable drm/i915: Account for sink max TMDS clock when checking the port clock drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 +- drivers/gpu/drm/drm_edid.c | 258 +++++++++++++------------ drivers/gpu/drm/i915/intel_display.c | 14 +- drivers/gpu/drm/i915/intel_hdmi.c | 9 +- drivers/gpu/drm/radeon/radeon_connectors.c | 4 +- include/drm/drm_crtc.h | 7 +- 6 files changed, 152 insertions(+), 144 deletions(-) -- 2.7.4

2 11

[PATCH libdrm] Make sure the second argument to container_of() is initialized
by Michel Dänzer 03 Aug '16

03 Aug '16

From: Michel Dänzer <michel.daenzer(a)amd.com> Fixes warnings and miscompilation resulting in crashes with clang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94249 Signed-off-by: Michel Dänzer <michel.daenzer(a)amd.com> --- amdgpu/amdgpu_vamgr.c | 2 +- util_double_list.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 8a707cb..3eaef70 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -157,7 +157,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { - struct amdgpu_bo_va_hole *hole; + struct amdgpu_bo_va_hole *hole = NULL; if (va == AMDGPU_INVALID_VA_ADDRESS) return; diff --git a/util_double_list.h b/util_double_list.h index 5d01f52..fc32da5 100644 --- a/util_double_list.h +++ b/util_double_list.h @@ -114,29 +114,29 @@ static inline void list_delinit(struct list_head *item) #endif #define LIST_FOR_EACH_ENTRY(pos, head, member) \ - for (pos = container_of((head)->next, pos, member); \ + for (pos = NULL, pos = container_of((head)->next, pos, member); \ &pos->member != (head); \ pos = container_of(pos->member.next, pos, member)) #define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head, member) \ - for (pos = container_of((head)->next, pos, member), \ + for (pos = NULL, pos = container_of((head)->next, pos, member), \ storage = container_of(pos->member.next, pos, member); \ &pos->member != (head); \ pos = storage, storage = container_of(storage->member.next, storage, member)) #define LIST_FOR_EACH_ENTRY_SAFE_REV(pos, storage, head, member) \ - for (pos = container_of((head)->prev, pos, member), \ + for (pos = NULL, pos = container_of((head)->prev, pos, member), \ storage = container_of(pos->member.prev, pos, member); \ &pos->member != (head); \ pos = storage, storage = container_of(storage->member.prev, storage, member)) #define LIST_FOR_EACH_ENTRY_FROM(pos, start, head, member) \ - for (pos = container_of((start), pos, member); \ + for (pos = NULL, pos = container_of((start), pos, member); \ &pos->member != (head); \ pos = container_of(pos->member.next, pos, member)) #define LIST_FOR_EACH_ENTRY_FROM_REV(pos, start, head, member) \ - for (pos = container_of((start), pos, member); \ + for (pos = NULL, pos = container_of((start), pos, member); \ &pos->member != (head); \ pos = container_of(pos->member.prev, pos, member)) -- 2.8.1

4 4

[Bug 94249] Linux incorrectly detects a Radeon GPU
by bugzilla-daemon＠freedesktop.org 03 Aug '16

03 Aug '16

https://bugs.freedesktop.org/show_bug.cgi?id=94249 Bug ID: 94249 Summary: Linux incorrectly detects a Radeon GPU Product: DRI Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: krejzi(a)email.com I've recently got a HP Probook 470 G3 laptop, which has an onboard Intel Skylake Graphics and an AMD Radeon R7 M340 GPU. However, the Linux seems to detect the GPU as following: 01:00.0 Display controller [0380]: Advanced Micro Devices, Inc. [AMD/ATI] Topaz XT [Radeon R7 M260/M265] [1002:6900] (rev 83) Which makes it a GCN 1.2 GPU which tries to use AMDGPU. That of course doesn't work. The driver loads, but as soon as it does, it corrupts all the available data from lspci -v output. I also can't use it with DRI_PRIME, since X server crashes while loading amdgpu (probably due to it not being an amdgpu supported GPU). Wikipedia identifies the mentioned card as GCN 1.0 OLAND GPU. Windows catalyst also claims it's R7 M340 and not R7 M360. It's probably a BIOS issue, but can it be worked around somehow? -- You are receiving this mail because: You are the assignee for the bug.

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dri-devel August 2016