dri-devel July 2017

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212 participants
1542 discussions

[PATCH] drm: amd: amdgpu: constify ttm_place structures.
by Arvind Yadav 03 Jul '17

03 Jul '17

ttm_place are not supposed to change at runtime. All functions working with ttm_place provided by <drm/ttm/ttm_placement.h> work with const ttm_place. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs(a)gmail.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5db0230..a2c8380 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -186,7 +186,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo; - static struct ttm_place placements = { + static const struct ttm_place placements = { .fpfn = 0, .lpfn = 0, .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM -- 2.7.4

2 2

[PATCH] drm: radeon: radeon_ttm: constify ttm_place structures.
by Arvind Yadav 03 Jul '17

03 Jul '17

ttm_place are not supposed to change at runtime. All functions working with ttm_place provided by <drm/ttm/ttm_placement.h> work with const ttm_place. So mark the non-const structs as const. File size before: text data bss dec hex filename 9235 344 136 9715 25f3 drivers/gpu/drm/radeon/radeon_ttm.o File size After adding 'const': text data bss dec hex filename 9267 312 136 9715 25f3 drivers/gpu/drm/radeon/radeon_ttm.o Signed-off-by: Arvind Yadav <arvind.yadav.cs(a)gmail.com> --- drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 8b7623b..6499832 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -178,7 +178,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, static void radeon_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *placement) { - static struct ttm_place placements = { + static const struct ttm_place placements = { .fpfn = 0, .lpfn = 0, .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM -- 2.7.4

2 2

[PATCH] drm: radeon: constify drm_prop_enum_list structures.
by Arvind Yadav 03 Jul '17

03 Jul '17

drm_prop_enum_lists are not supposed to change at runtime. All functions working with drm_prop_enum_list provided by <drm/drm_property.h> work with const drm_prop_enum_list. So mark the non-const structs as const. File size before: text data bss dec hex filename 18276 384 0 18660 48e4 drivers/gpu/drm/radeon/radeon_display.o File size After adding 'const': text data bss dec hex filename 18660 0 0 18660 48e4 drivers/gpu/drm/radeon/radeon_display.o Signed-off-by: Arvind Yadav <arvind.yadav.cs(a)gmail.com> --- drivers/gpu/drm/radeon/radeon_display.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 17d3daf..f339c1c 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1388,12 +1388,12 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = { .output_poll_changed = radeon_output_poll_changed }; -static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = +static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = { { 0, "driver" }, { 1, "bios" }, }; -static struct drm_prop_enum_list radeon_tv_std_enum_list[] = +static const struct drm_prop_enum_list radeon_tv_std_enum_list[] = { { TV_STD_NTSC, "ntsc" }, { TV_STD_PAL, "pal" }, { TV_STD_PAL_M, "pal-m" }, @@ -1404,25 +1404,25 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] = { TV_STD_SECAM, "secam" }, }; -static struct drm_prop_enum_list radeon_underscan_enum_list[] = +static const struct drm_prop_enum_list radeon_underscan_enum_list[] = { { UNDERSCAN_OFF, "off" }, { UNDERSCAN_ON, "on" }, { UNDERSCAN_AUTO, "auto" }, }; -static struct drm_prop_enum_list radeon_audio_enum_list[] = +static const struct drm_prop_enum_list radeon_audio_enum_list[] = { { RADEON_AUDIO_DISABLE, "off" }, { RADEON_AUDIO_ENABLE, "on" }, { RADEON_AUDIO_AUTO, "auto" }, }; /* XXX support different dither options? spatial, temporal, both, etc. */ -static struct drm_prop_enum_list radeon_dither_enum_list[] = +static const struct drm_prop_enum_list radeon_dither_enum_list[] = { { RADEON_FMT_DITHER_DISABLE, "off" }, { RADEON_FMT_DITHER_ENABLE, "on" }, }; -static struct drm_prop_enum_list radeon_output_csc_enum_list[] = +static const struct drm_prop_enum_list radeon_output_csc_enum_list[] = { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, -- 2.7.4

2 1

Status of etnaviv for Linux kernel.
by James Courtier-Dutton 02 Jul '17

02 Jul '17

Hi, I have a Utilite Pro PC that uses the "Freescale i.MX 6 Quad". I am running Linux kernel 4.11.8 I get the following messages: [ 5.234054] etnaviv gpu-subsystem: bound 134000.gpu (ops gpu_ops [etnaviv]) [ 5.234124] etnaviv gpu-subsystem: bound 130000.gpu (ops gpu_ops [etnaviv]) [ 5.234192] etnaviv gpu-subsystem: bound 2204000.gpu (ops gpu_ops [etnaviv]) [ 5.235765] etnaviv-gpu 134000.gpu: model: GC320, revision: 5007 [ 5.291835] etnaviv-gpu 134000.gpu: command buffer outside valid memory window [ 5.298195] etnaviv-gpu 130000.gpu: model: GC2000, revision: 5108 [ 5.392637] etnaviv-gpu 130000.gpu: command buffer outside valid memory window [ 5.400029] etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215 [ 5.400044] etnaviv-gpu 2204000.gpu: Ignoring GPU with VG and FE2.0 [ 5.402024] [drm] Initialized etnaviv 1.0.0 20151214 for gpu-subsystem on minor 0 I would like to see at least 2D support so that I could see a framebuffer console. Is this possible yet with the above gpu hardware? I am hoping that there is some quick fix for the "command buffer outside valid memory window" so that I can at least get some of it working. Kind Regards James

2 1

[PATCH 10/21] drm/etnaviv: use 'sync points' for performance monitor requests
by Christian Gmeiner 02 Jul '17

02 Jul '17

With 'sync points' we can sample the reqeustes perform signals before and/or after the submited command buffer. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 112 +++++++++++++++++++++++++++++----- drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 4 ++ 2 files changed, 102 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 0766861..2e9f031 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1313,12 +1313,47 @@ void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu) pm_runtime_put_autosuspend(gpu->dev); } +static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, + struct etnaviv_event *event, unsigned int flags) +{ + unsigned int i; + + for (i = 0; i < event->nr_pmrs; i++) { + const struct etnaviv_perfmon_request *pmr = event->pmrs + i; + + if (pmr->flags == flags) + etnaviv_perfmon_process(gpu, pmr); + } +} + +static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, + struct etnaviv_event *event) +{ + sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); +} + +static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, + struct etnaviv_event *event) +{ + unsigned int i; + + sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); + + for (i = 0; i < event->nr_pmrs; i++) { + const struct etnaviv_perfmon_request *pmr = event->pmrs + i; + + *pmr->bo_vma = pmr->sequence; + } +} + + /* add bo's to gpu's ring, and kick gpu: */ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf) { struct dma_fence *fence; unsigned int event, i; + unsigned int sync[2] = { ~0U, ~0U }; int ret; ret = etnaviv_gpu_pm_get_sync(gpu); @@ -1341,6 +1376,39 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, goto out_pm_put; } + /* + * if there are performance monitor requests we need to have a sync point to + * re-configure gpu and process ETNA_PM_PROCESS_PRE requests. + */ + if (cmdbuf->nr_pmrs) { + sync[0] = event_alloc(gpu); + + if (unlikely(sync[0] == ~0U)) { + DRM_ERROR("no free events for sync point 0\n"); + event_free(gpu, event); + ret = -EBUSY; + goto out_pm_put; + } + } + + /* + * if there are performance monitor requests we need to have sync point to + * re-configure gpu, process ETNA_PM_PROCESS_POST requests and update the + * sequence number for userspace. + */ + if (cmdbuf->nr_pmrs) { + sync[1] = event_alloc(gpu); + + if (unlikely(sync[1] == ~0U)) { + DRM_ERROR("no free events for sync point 1\n"); + event_free(gpu, event); + if (unlikely(sync[0] == ~0U)) + event_free(gpu, sync[0]); + ret = -EBUSY; + goto out_pm_put; + } + } + mutex_lock(&gpu->lock); fence = etnaviv_gpu_fence_alloc(gpu); @@ -1360,8 +1428,22 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, gpu->lastctx = cmdbuf->ctx; } + if (sync[0] != ~0U) { + gpu->event[sync[0]].sync_point = &sync_point_perfmon_sample_pre; + gpu->event[sync[0]].nr_pmrs = cmdbuf->nr_pmrs; + gpu->event[sync[0]].pmrs = cmdbuf->pmrs; + etnaviv_sync_point_queue(gpu, sync[0]); + } + etnaviv_buffer_queue(gpu, event, cmdbuf); + if (sync[1] != ~0U) { + gpu->event[sync[1]].sync_point = &sync_point_perfmon_sample_post; + gpu->event[sync[1]].nr_pmrs = cmdbuf->nr_pmrs; + gpu->event[sync[1]].pmrs = cmdbuf->pmrs; + etnaviv_sync_point_queue(gpu, sync[1]); + } + cmdbuf->fence = fence; list_add_tail(&cmdbuf->node, &gpu->active_cmd_list); @@ -1455,20 +1537,22 @@ static irqreturn_t irq_handler(int irq, void *data) etnaviv_process_sync_point(gpu, &gpu->event[event]); fence = gpu->event[event].fence; - gpu->event[event].fence = NULL; - dma_fence_signal(fence); - - /* - * Events can be processed out of order. Eg, - * - allocate and queue event 0 - * - allocate event 1 - * - event 0 completes, we process it - * - allocate and queue event 0 - * - event 1 and event 0 complete - * we can end up processing event 0 first, then 1. - */ - if (fence_after(fence->seqno, gpu->completed_fence)) - gpu->completed_fence = fence->seqno; + if (fence) { + gpu->event[event].fence = NULL; + dma_fence_signal(fence); + + /* + * Events can be processed out of order. Eg, + * - allocate and queue event 0 + * - allocate event 1 + * - event 0 completes, we process it + * - allocate and queue event 0 + * - event 1 and event 0 complete + * we can end up processing event 0 first, then 1. + */ + if (fence_after(fence->seqno, gpu->completed_fence)) + gpu->completed_fence = fence->seqno; + } event_free(gpu, event); } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index fee6ed9..71375ab 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -92,6 +92,10 @@ struct etnaviv_event { struct dma_fence *fence; void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); + + /* performance monitor requests */ + unsigned int nr_pmrs; + struct etnaviv_perfmon_request *pmrs; }; struct etnaviv_cmdbuf_suballoc; -- 2.9.4

2 16

[PATCH] drm: qxl: constify ttm_place structures.
by Arvind Yadav 02 Jul '17

02 Jul '17

ttm_place are not supposed to change at runtime. All functions working with ttm_place provided by <drm/ttm/ttm_placement.h> work with const ttm_place. So mark the non-const structs as const. File size before: text data bss dec hex filename 3485 184 264 3933 f5d drivers/gpu/drm/qxl/qxl_ttm.o File size After adding 'const': text data bss dec hex filename 3501 152 264 3917 f4d drivers/gpu/drm/qxl/qxl_ttm.o Signed-off-by: Arvind Yadav <arvind.yadav.cs(a)gmail.com> --- drivers/gpu/drm/qxl/qxl_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 0fdedee..900fb8a 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -187,7 +187,7 @@ static void qxl_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *placement) { struct qxl_bo *qbo; - static struct ttm_place placements = { + static const struct ttm_place placements = { .fpfn = 0, .lpfn = 0, .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM -- 2.7.4

1 0

[PATCH v1 0/2] drm: rcar-du: Repair vblank event handling
by Kieran Bingham 02 Jul '17

02 Jul '17

The recent changes to the rcar-du driver to fix a race condition inadvertently change the order of which vblanks are reported. Correct this by handling vblank events in the same completion handler. This removes the need for the IRQ handler on DU instances which are sourced by a VSP1. For other platforms (Gen2) the vblank handler was enabling the VBK interrupt, but parsing on the FRM interrupt. Fix this by enabling the FRM interrupt using the FRE bit in the DIER register Kieran Bingham (2): drm: rcar-du: Enable the FRM interrupt for vblank drm: rcar-du: Repair vblank for DRM page flips using the VSP1 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 25 ++++++++++++++++++++----- drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 2 ++- drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 8 ++++++-- drivers/media/platform/vsp1/vsp1_drm.c | 5 +++-- drivers/media/platform/vsp1/vsp1_drm.h | 2 +- drivers/media/platform/vsp1/vsp1_pipe.c | 20 ++++++++++---------- drivers/media/platform/vsp1/vsp1_pipe.h | 2 +- drivers/media/platform/vsp1/vsp1_video.c | 6 +++++- include/media/vsp1.h | 2 +- 9 files changed, 49 insertions(+), 23 deletions(-) base-commit: fa5b4114202de0c1a7a64fd407af0b81ca529419 -- git-series 0.9.1

3 6

[PATCH 0/2] Fix a couple of amdgpu de-initialization failures
by John Brooks 02 Jul '17

02 Jul '17

These patches fix problems that occur when attempting to unload the amdgpu module on my R9 290. It now unloads without any (obvious) errors. Unfortunately, however, I hit a snag when trying to load the module again after unloading it: [ 150.849380] [drm] amdgpu kernel modesetting enabled. [ 150.849471] [drm] initializing kernel modesetting (HAWAII 0x1002:0x67B1 0x1043:0x0470 0x00). [ 150.849483] [drm] register mmio base: 0xF7E00000 [ 150.849483] [drm] register mmio size: 262144 [ 150.849488] [drm] probing gen 2 caps for device 8086:c01 = 261ad03/e [ 150.849489] [drm] probing mlw for device 8086:c01 = 261ad03 [ 150.980046] [drm] BIOS signature incorrect 0 0 [ 150.980050] amdgpu 0000:01:00.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0xffff [ 150.980081] ATOM BIOS: 113-AD63300-102 [ 150.980087] [drm] GPU post is not needed [ 150.980215] [drm] vm size is 64 GB, block size is 13-bit [ 150.980220] amdgpu 0000:01:00.0: VRAM: 4096M 0x0000000000000000 - 0x00000000FFFFFFFF (4096M used) [ 150.980221] amdgpu 0000:01:00.0: GTT: 4096M 0x0000000100000000 - 0x00000001FFFFFFFF [ 150.980224] [drm] Detected VRAM RAM=4096M, BAR=256M [ 150.980224] [drm] RAM width 512bits GDDR5 [ 150.980324] [TTM] Zone kernel: Available graphics memory: 10276058 kiB [ 150.980324] [TTM] Zone dma32: Available graphics memory: 2097152 kiB [ 150.980325] [TTM] Initializing pool allocator [ 150.980337] [TTM] Initializing DMA pool allocator [ 150.980351] [drm] amdgpu: 4096M of VRAM memory ready [ 150.980352] [drm] amdgpu: 4096M of GTT memory ready. [ 150.980368] [drm] GART: num cpu pages 1048576, num gpu pages 1048576 [ 151.101593] [drm] PCIE GART of 4096M enabled (table at 0x0000000000040000). [ 151.101611] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 151.101611] [drm] Driver supports precise vblank timestamp query. [ 151.101633] amdgpu 0000:01:00.0: amdgpu: using MSI. [ 151.101643] [drm] amdgpu: irq initialized. [ 151.105091] [drm] Internal thermal controller with fan control [ 151.110444] [drm] Invalid PCC GPIO: 13! [ 151.110445] [drm] amdgpu: dpm initialized [ 151.110610] [drm] AMDGPU Display Connectors [ 151.110611] [drm] Connector 0: [ 151.110611] [drm] DP-1 [ 151.110612] [drm] HPD2 [ 151.110613] [drm] DDC: 0x194c 0x194c 0x194d 0x194d 0x194e 0x194e 0x194f 0x194f [ 151.110613] [drm] Encoders: [ 151.110614] [drm] DFP1: INTERNAL_UNIPHY2 [ 151.110614] [drm] Connector 1: [ 151.110614] [drm] HDMI-A-1 [ 151.110615] [drm] HPD3 [ 151.110615] [drm] DDC: 0x1954 0x1954 0x1955 0x1955 0x1956 0x1956 0x1957 0x1957 [ 151.110615] [drm] Encoders: [ 151.110616] [drm] DFP2: INTERNAL_UNIPHY2 [ 151.110627] [drm] Connector 2: [ 151.110628] [drm] DVI-D-1 [ 151.110628] [drm] HPD1 [ 151.110628] [drm] DDC: 0x1958 0x1958 0x1959 0x1959 0x195a 0x195a 0x195b 0x195b [ 151.110629] [drm] Encoders: [ 151.110629] [drm] DFP3: INTERNAL_UNIPHY1 [ 151.110629] [drm] Connector 3: [ 151.110629] [drm] DVI-D-2 [ 151.110630] [drm] HPD6 [ 151.110630] [drm] DDC: 0x1960 0x1960 0x1961 0x1961 0x1962 0x1962 0x1963 0x1963 [ 151.110630] [drm] Encoders: [ 151.110631] [drm] DFP4: INTERNAL_UNIPHY [ 151.111727] amdgpu 0000:01:00.0: fence driver on ring 0 use gpu addr 0x0000000100000010, cpu addr 0xffff8805029f4010 [ 151.111798] amdgpu 0000:01:00.0: fence driver on ring 1 use gpu addr 0x0000000100000020, cpu addr 0xffff8805029f4020 [ 151.111860] amdgpu 0000:01:00.0: fence driver on ring 2 use gpu addr 0x0000000100000030, cpu addr 0xffff8805029f4030 [ 151.111914] amdgpu 0000:01:00.0: fence driver on ring 3 use gpu addr 0x0000000100000040, cpu addr 0xffff8805029f4040 [ 151.111943] amdgpu 0000:01:00.0: fence driver on ring 4 use gpu addr 0x0000000100000050, cpu addr 0xffff8805029f4050 [ 151.111958] amdgpu 0000:01:00.0: fence driver on ring 5 use gpu addr 0x0000000100000060, cpu addr 0xffff8805029f4060 [ 151.111971] amdgpu 0000:01:00.0: fence driver on ring 6 use gpu addr 0x0000000100000070, cpu addr 0xffff8805029f4070 [ 151.111986] amdgpu 0000:01:00.0: fence driver on ring 7 use gpu addr 0x0000000100000080, cpu addr 0xffff8805029f4080 [ 151.112007] amdgpu 0000:01:00.0: fence driver on ring 8 use gpu addr 0x0000000100000090, cpu addr 0xffff8805029f4090 [ 151.112297] amdgpu 0000:01:00.0: fence driver on ring 9 use gpu addr 0x00000001000000a0, cpu addr 0xffff8805029f40a0 [ 151.112321] amdgpu 0000:01:00.0: fence driver on ring 10 use gpu addr 0x00000001000000b0, cpu addr 0xffff8805029f40b0 [ 151.113021] [drm] Found UVD firmware Version: 1.64 Family ID: 9 [ 151.113316] amdgpu 0000:01:00.0: fence driver on ring 11 use gpu addr 0x000000000088bd30, cpu addr 0xffffc90009a38d30 [ 151.113762] [drm] Found VCE firmware Version: 50.10 Binary ID: 2 [ 151.113815] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000001000000d0, cpu addr 0xffff8805029f40d0 [ 151.113853] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x00000001000000e0, cpu addr 0xffff8805029f40e0 [ 151.113901] [drm] PCIE gen 3 link speeds already enabled [ 151.124088] [drm] ring test on 0 succeeded in 16 usecs [ 152.323771] [drm] ring test on 1 succeeded in 675 usecs [ 152.323794] [drm] ring test on 2 succeeded in 14 usecs [ 152.323818] [drm] ring test on 3 succeeded in 15 usecs [ 152.323841] [drm] ring test on 4 succeeded in 15 usecs [ 152.323865] [drm] ring test on 5 succeeded in 15 usecs [ 152.323890] [drm] ring test on 6 succeeded in 16 usecs [ 152.323914] [drm] ring test on 7 succeeded in 15 usecs [ 152.323938] [drm] ring test on 8 succeeded in 15 usecs [ 152.428850] [drm:cik_sdma_ring_test_ring [amdgpu]] *ERROR* amdgpu: ring 9 test failed (0xCAFEDEAD) [ 152.428869] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block <cik_sdma> failed -22 [ 152.428872] amdgpu 0000:01:00.0: amdgpu_init failed [ 153.481236] [TTM] Finalizing pool allocator [ 153.481239] [TTM] Finalizing DMA pool allocator [ 153.481316] [TTM] Zone kernel: Used memory at exit: 0 kiB [ 153.481318] [TTM] Zone dma32: Used memory at exit: 0 kiB [ 153.481320] [drm] amdgpu: ttm finalized [ 153.481328] amdgpu 0000:01:00.0: Fatal error during GPU init [ 153.481333] [drm] amdgpu: finishing device. [ 153.481334] [TTM] Memory type 2 has not been initialized [ 153.494261] amdgpu: probe of 0000:01:00.0 failed with error -22 A subsequent attempt to load the module produced similar results, except the ring test failed on ring 1 as well as 9, so I suppose it's intermittent. Maybe someone with access to the hardware interface specifications can figure out why. But at least it unloads now. -- John Brooks (Frogging101)

3 5

[Bug 99762] black mesa not launching
by bugzilla-daemon＠freedesktop.org 02 Jul '17

02 Jul '17

https://bugs.freedesktop.org/show_bug.cgi?id=99762 Bug ID: 99762 Summary: black mesa not launching Product: Mesa Version: 13.0 Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/radeonsi Assignee: dri-devel(a)lists.freedesktop.org Reporter: bronsonmathews(a)gmail.com QA Contact: dri-devel(a)lists.freedesktop.org I see not command line output, so can only assume a recent driver update has caused this game to stop running. Using mesa 13.0.3 on a radeon 6970 under kde neon. Running the game from steam gives no error in the console, and does nothing. I had it working fine previously with an older version. -- You are receiving this mail because: You are the assignee for the bug.

1 7

[PATCH] drm: armada: Constify drm_prop_enum_list structures.
by Arvind Yadav 01 Jul '17

01 Jul '17

1 0

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dri-devel July 2017