dri-devel December 2019

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[PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
by Sharat Masetty 03 Dec '19

03 Dec '19

This patch adds the required dt nodes and properties to enabled A618 GPU. Change-Id: I7491c4de654c4b84d03dbcf703532448b27d4147 Signed-off-by: Sharat Masetty <smasetty(a)codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c3db2e5..31223d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -18,6 +18,8 @@ #include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> +#include <dt-bindings/clock/qcom,gpucc-sc7180.h> +#include <dt-bindings/power/qcom-rpmpd.h> / { interrupt-parent = <&intc>; @@ -733,6 +735,120 @@ #power-domain-cells = <1>; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>, + <0 0x5061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc 35 &mc_virt 512>; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x5040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu"; + + reg = <0 0x506a000 0 0x31000>, + <0 0xb290000 0 0x10000>, + <0 0xb490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc CX_GDSC>; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; -- 1.9.1

1 0

[PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration
by Sharat Masetty 03 Dec '19

03 Dec '19

Fix the cx debugbus related register configuration, to collect accurate bus data during gpu snapshot. This helps with complete snapshot dump and also complete proper GPU recovery. Change-Id: I4f0ae3eb2dd5d24a88d805277fad212dda2d735e Signed-off-by: Sharat Masetty <smasetty(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 99b5a41..d6023ba 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -353,26 +353,26 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu, cxdbg = ioremap(res->start, resource_size(res)); if (cxdbg) { - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT, A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf)); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM, A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf)); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0); - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2, 0); + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0); } nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) + -- 1.9.1

1 0

[PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list
by Sharat Masetty 03 Dec '19

03 Dec '19

This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Change-Id: Ie14ba09f32513ba6a6c882fda0d98ee1742b46d5 Signed-off-by: Sharat Masetty <smasetty(a)codeaurora.org> --- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 0888e0d..e728ea5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -152,6 +152,17 @@ .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", }, { + .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .revn = 618, + .name = "A618", + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, .name = "A630", -- 1.9.1

1 0

[PATCH 0/5] Add support for A618 GPU
by Sharat Masetty 03 Dec '19

03 Dec '19

This series and support to enable A618 GPU revision. Please review. Sharat Masetty (5): drm: msm: Add 618 gpu to the adreno gpu list drm: msm: a6xx: Add support for A618 drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state drm: msm: a6xx: fix debug bus register configuration arm: dts: sc7180: Add A618 gpu dt blob arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 ++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx.xml.h | 52 ++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 24 +++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 76 ++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 16 +++- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++- 9 files changed, 348 insertions(+), 38 deletions(-) -- 1.9.1

1 0

[PATCH libdrm v3] modetest: Use floating vrefresh while dumping mode
by Devarsh Thakkar 03 Dec '19

03 Dec '19

Add function to derive floating value of vertical refresh rate from drm mode using pixel clock, horizontal total size and vertical total size. Use this function to find suitable mode having vrefresh value which is matching with user provided vrefresh value. If user doesn't provide any vrefresh value in args then update vertical refresh rate value in pipe args using this function. Also use this function for printing floating vrefresh while dumping all available modes. This will give more accurate picture to user for available modes differentiated by floating vertical refresh rate and help user select more appropriate mode using suitable refresh rate value. V3: Change name of function used to derive refresh rate. V2: 1) Don't use inline function for deriving refresh rate from mode. 2) If requested mode not found, print refresh rate only if user had provided it in args. Signed-off-by: Devarsh Thakkar <devarsh.thakkar(a)xilinx.com> --- tests/modetest/modetest.c | 40 +++++++++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index b4edfcb..19ce20f 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -133,6 +133,12 @@ static inline int64_t U642I64(uint64_t val) return (int64_t)*((int64_t *)&val); } +static float mode_vrefresh(drmModeModeInfo *mode) +{ + return mode->clock * 1000.00 + / (mode->htotal * mode->vtotal); +} + #define bit_name_fn(res) \ const char * res##_str(int type) { \ unsigned int i; \ @@ -210,9 +216,9 @@ static void dump_encoders(struct device *dev) static void dump_mode(drmModeModeInfo *mode) { - printf(" %s %d %d %d %d %d %d %d %d %d %d", + printf(" %s %.2f %d %d %d %d %d %d %d %d %d", mode->name, - mode->vrefresh, + mode_vrefresh(mode), mode->hdisplay, mode->hsync_start, mode->hsync_end, @@ -823,12 +829,11 @@ struct plane_arg { static drmModeModeInfo * connector_find_mode(struct device *dev, uint32_t con_id, const char *mode_str, - const float vrefresh) + float *vrefresh) { drmModeConnector *connector; drmModeModeInfo *mode; int i; - float mode_vrefresh; connector = get_connector_by_id(dev, con_id); if (!connector || !connector->count_modes) @@ -837,16 +842,19 @@ connector_find_mode(struct device *dev, uint32_t con_id, const char *mode_str, for (i = 0; i < connector->count_modes; i++) { mode = &connector->modes[i]; if (!strcmp(mode->name, mode_str)) { - /* If the vertical refresh frequency is not specified then return the - * first mode that match with the name. Else, return the mode that match - * the name and the specified vertical refresh frequency. + /* If the vertical refresh frequency is not specified + * then return the first mode that match with the name + * and update corresponding vrefresh in pipe_arg. + * Else, return the mode that match the name and + * the specified vertical refresh frequency. */ - mode_vrefresh = mode->clock * 1000.00 - / (mode->htotal * mode->vtotal); - if (vrefresh == 0) + if (*vrefresh == 0) { + *vrefresh = mode_vrefresh(mode); return mode; - else if (fabs(mode_vrefresh - vrefresh) < 0.005) + } else if (fabs(mode_vrefresh(mode) + - *vrefresh) < 0.005) { return mode; + } } } @@ -909,9 +917,15 @@ static int pipe_find_crtc_and_mode(struct device *dev, struct pipe_arg *pipe) for (i = 0; i < (int)pipe->num_cons; i++) { mode = connector_find_mode(dev, pipe->con_ids[i], - pipe->mode_str, pipe->vrefresh); + pipe->mode_str, &pipe->vrefresh); if (mode == NULL) { - fprintf(stderr, + if (pipe->vrefresh) + fprintf(stderr, + "failed to find mode " + "\"%s-%.2fHz\" for connector %s\n", + pipe->mode_str, pipe->vrefresh, pipe->cons[i]); + else + fprintf(stderr, "failed to find mode \"%s\" for connector %s\n", pipe->mode_str, pipe->cons[i]); return -EINVAL; -- 2.7.4

4 5

[PATCH 0/7] drm/udl: Convert to simple-pipe helpers and clean up
by Thomas Zimmermann 03 Dec '19

03 Dec '19

With only a single display pipeline and primary plane, udl is perfect for simple-pipe helpers. Patches 1 to 3 do the convertion. This enables atomic modesetting for udl devices. Patches 4 to 7 clean up handling of color depth and framebuffers. With universal planes that come with simple pipe, display updates can be implemented with DRM's damage handlers. The primary plane's formats array allows to export the correct preferred color depth. The original value was choosen for maximum compatibility, but did not represent the device's capability. The patchset has been tested by running the fb console, X11 and Weston on a DisplayLink adapter. Thomas Zimmermann (7): drm/udl: Init connector before encoder and CRTC drm/udl: Convert to struct drm_simple_display_pipe drm/udl: Remove unused encoder and CRTC code drm/udl: Set preferred color depth to 16 bpp drm/udl: Convert to drm_atomic_helper_dirtyfb() drm/udl: Remove struct udl_device.active_fb_16 drm/udl: Move udl_handle_damage() into udl_modeset.c drivers/gpu/drm/udl/Makefile | 2 +- drivers/gpu/drm/udl/udl_connector.c | 19 +- drivers/gpu/drm/udl/udl_drv.c | 11 +- drivers/gpu/drm/udl/udl_drv.h | 19 +- drivers/gpu/drm/udl/udl_encoder.c | 70 ------- drivers/gpu/drm/udl/udl_fb.c | 216 ---------------------- drivers/gpu/drm/udl/udl_main.c | 3 - drivers/gpu/drm/udl/udl_modeset.c | 276 +++++++++++++++++----------- 8 files changed, 187 insertions(+), 429 deletions(-) delete mode 100644 drivers/gpu/drm/udl/udl_encoder.c delete mode 100644 drivers/gpu/drm/udl/udl_fb.c -- 2.23.0

3 17

[PATCH] drm: remove no longer used .master_{create, destroy} callbacks
by Emil Velikov 03 Dec '19

03 Dec '19

From: Emil Velikov <emil.velikov(a)collabora.com> Up-to recently the only driver which required these was vmwgfx. With commit 9c84aeba67cc ("drm/vmwgfx: Kill unneeded legacy security features") the driver no longer sets them, so we can drop the unused infra. Cc: Thomas Hellstrom <thellstrom(a)vmware.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Signed-off-by: Emil Velikov <emil.velikov(a)collabora.com> --- drivers/gpu/drm/drm_auth.c | 8 -------- include/drm/drm_drv.h | 14 -------------- 2 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index cc9acd986c68..531b876d0ed8 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -153,11 +153,6 @@ static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv) return -ENOMEM; } - if (dev->driver->master_create) { - ret = dev->driver->master_create(dev, fpriv->master); - if (ret) - goto out_err; - } fpriv->is_master = 1; fpriv->authenticated = 1; @@ -332,9 +327,6 @@ static void drm_master_destroy(struct kref *kref) if (drm_core_check_feature(dev, DRIVER_MODESET)) drm_lease_destroy(master); - if (dev->driver->master_destroy) - dev->driver->master_destroy(dev, master); - drm_legacy_master_rmmaps(dev, master); idr_destroy(&master->magic_map); diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h index cf13470810a5..4300e85db457 100644 --- a/include/drm/drm_drv.h +++ b/include/drm/drm_drv.h @@ -457,20 +457,6 @@ struct drm_driver { */ void (*irq_uninstall) (struct drm_device *dev); - /** - * @master_create: - * - * Called whenever a new master is created. Only used by vmwgfx. - */ - int (*master_create)(struct drm_device *dev, struct drm_master *master); - - /** - * @master_destroy: - * - * Called whenever a master is destroyed. Only used by vmwgfx. - */ - void (*master_destroy)(struct drm_device *dev, struct drm_master *master); - /** * @master_set: * -- 2.23.0

2 1

[PATCH 0/9] drm/tegra: Miscellaneous fixes
by Thierry Reding 03 Dec '19

03 Dec '19

From: Thierry Reding <treding(a)nvidia.com> Here's a random assortment of fixes for issues that I ran into as I've been testing suspend/resume and other things recently. Thierry Thierry Reding (9): drm/tegra: hub: Remove bogus connection mutex check drm/tegra: gem: Properly pin imported buffers drm/tegra: gem: Remove premature import restrictions drm/tegra: Use proper IOVA address for cursor image drm/tegra: sor: Implement system suspend/resume drm/tegra: vic: Export module device table drm/tegra: Silence expected errors on IOMMU attach drm/tegra: dpaux: Add missing runtime PM references drm/tegra: sor: Make the +5V HDMI supply optional drivers/gpu/drm/tegra/dc.c | 18 ++++++------- drivers/gpu/drm/tegra/dpaux.c | 16 +++++++++-- drivers/gpu/drm/tegra/drm.c | 4 +-- drivers/gpu/drm/tegra/gem.c | 50 ++++++++++++++++++++++++++++++----- drivers/gpu/drm/tegra/hub.c | 3 --- drivers/gpu/drm/tegra/sor.c | 38 ++++++++++++++++++++++---- drivers/gpu/drm/tegra/vic.c | 7 ++--- 7 files changed, 104 insertions(+), 32 deletions(-) -- 2.23.0

2 25

[PATCH v3 0/5] Replace hibmc code with generic implmentation
by Thomas Zimmermann 03 Dec '19

03 Dec '19

The patch set replaces code in hibmc with generic implementation. Version 3 of the patchset only adds fixes. I'm reposting the whole thing for possible testers. Patches 1 to 4 replace fbdev emuation, framebuffer and creation of dumb buffers with respective code from DRM helpers. Patch 5 adds an additional interface to debugfs that displays the allocated and free areas in video memory. The patches have only been compile-tested. Further testing is appreciated. v3: * only do power-of-2 test if pitch_align is given * update mgag200 for changes to drm_gem_vram_fill_create_dumb() v2: * split [3/4] into vram and hibmc changes * verify that pitch_align is power of two Thomas Zimmermann (5): drm/hisilicon/hibmc: Switch to generic fbdev emulation drm/hisilicon/hibmc: Replace struct hibmc_framebuffer with generic code drm/vram: Support scanline alignment for dumb buffers drm/hisilicon/hibmc: Implement hibmc_dumb_create() with generic helpers drm/hisilicon/hibmc: Export VRAM MM information to debugfs drivers/gpu/drm/drm_gem_vram_helper.c | 13 +- drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +- .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 4 +- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 6 +- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 26 -- .../gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 240 ------------------ drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 117 +-------- drivers/gpu/drm/mgag200/mgag200_drv.c | 2 +- include/drm/drm_gem_vram_helper.h | 1 + 9 files changed, 21 insertions(+), 390 deletions(-) delete mode 100644 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c -- 2.23.0

1 5

[PATCH] drm/dp_mst: Remove VCPI while disabling topology mgr
by Wayne Lin 03 Dec '19

03 Dec '19

[Why] While disabling mst topology manager in drm_dp_mst_topology_mgr_set_mst(), now just reset the mgr->payloads but doesn't handle the mgr->proposed_vcpis. [How] Remove mgr->proposed_vcpis to NULL. Signed-off-by: Wayne Lin <Wayne.Lin(a)amd.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index ae5809a1f19a..81e92b260d7a 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3386,6 +3386,7 @@ static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count) int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state) { int ret = 0; + int i = 0; struct drm_dp_mst_branch *mstb = NULL; mutex_lock(&mgr->lock); @@ -3446,10 +3447,21 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms /* this can fail if the device is gone */ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0); ret = 0; + mutex_lock(&mgr->payload_lock); memset(mgr->payloads, 0, mgr->max_payloads * sizeof(struct drm_dp_payload)); mgr->payload_mask = 0; set_bit(0, &mgr->payload_mask); + for (i = 0; i < mgr->max_payloads; i++) { + struct drm_dp_vcpi *tmp_vcpi = mgr->proposed_vcpis[i]; + + if (tmp_vcpi) { + tmp_vcpi->vcpi = 0; + tmp_vcpi->num_slots = 0; + } + mgr->proposed_vcpis[i] = NULL; + } mgr->vcpi_mask = 0; + mutex_unlock(&mgr->payload_lock); } out_unlock: -- 2.17.1

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dri-devel December 2019