https://bugs.freedesktop.org/show_bug.cgi?id=107748
Bug ID: 107748
Summary: [Intel GFX CI] couldn't schedule ib on ring <uvd>
Product: DRI
Version: XOrg git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: DRM/AMDgpu
Assignee: dri-devel(a)lists.freedesktop.org
Reporter: martin.peres(a)free.fr
When executing the test igt@…
[View More]pm_rpm@system-suspend-execbuf on a KBLg system, we
hit the following bug:
[ 106.635764] amdgpu 0000:01:00.0: couldn't schedule ib on ring <uvd>
[ 106.635901] [drm:amdgpu_uvd_ring_test_ib [amdgpu]] *ERROR* amdgpu: (0)failed
to get destroy ib (-22).
[ 106.635935] [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* amdgpu: failed
testing IB on ring 12 (-22).
[ 106.742994] [drm:process_one_work] *ERROR* ib ring test failed (-22).
Full logs:
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_83/fi-kbl-8809g/igt@pm_rpm@…
The reproduction rate is so far very low (happened once), but I will use this
bug as a tracker for this issue.
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The saturation bit was being set at bit 9 in the second 32-bit word
of the TPMEM CSC. This isn't correct, the saturation bit is bit 42,
which is bit 10 of the second word.
Fixes: 1aa8ea0d2bd5d ("gpu: ipu-v3: Add Image Converter unit")
Signed-off-by: Steve Longerbeam <slongerbeam(a)gmail.com>
Cc: stable(a)vger.kernel.org
---
drivers/gpu/ipu-v3/ipu-ic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
index …
[View More]594c3cbc8291..18816ccf600e 100644
--- a/drivers/gpu/ipu-v3/ipu-ic.c
+++ b/drivers/gpu/ipu-v3/ipu-ic.c
@@ -257,7 +257,7 @@ static int init_csc(struct ipu_ic *ic,
writel(param, base++);
param = ((a[0] & 0x1fe0) >> 5) | (params->scale << 8) |
- (params->sat << 9);
+ (params->sat << 10);
writel(param, base++);
param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
--
2.17.1
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https://bugs.freedesktop.org/show_bug.cgi?id=109940
Bug ID: 109940
Summary: Brother Printer Customer Service
Product: Mesa
Version: unspecified
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/i915
Assignee: dri-devel(a)lists.freedesktop.org
Reporter: bemji4444(a)gmail.com
QA Contact: dri-devel(a)lists.…
[View More]freedesktop.org
Do you want to Download Brother Printer Drivers For your Windows 10? Here we
Describe 2 Way to download brother printer driver.Choose any one way which is
suitable for you.If Still Facing problem call our Brother printer Customer
Service 1800-436-0509.
For More Information
Visit:https://www.printertollfreenumber.com/brother-printer-support
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https://bugs.freedesktop.org/show_bug.cgi?id=109937
Bug ID: 109937
Summary: HOME BUTTON NOT WORKING
Product: DRI
Version: XOrg git
Hardware: x86-64 (AMD64)
OS: Windows (All)
Status: NEW
Severity: critical
Priority: medium
Component: DRM/Radeon
Assignee: dri-devel(a)lists.freedesktop.org
Reporter: imranali30077(a)gmail.com
1. TYPE IN URL
2.TYPE USER NAME AND …
[View More]PASSWORD AND CLICK LOGIN LINK
3.CLICK HOME BUTTON
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https://bugs.freedesktop.org/show_bug.cgi?id=106175
Bug ID: 106175
Summary: amdgpu.dc=1 shows performance issues with Xorg
compositors when moving windows
Product: DRI
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: normal
Priority: medium
Component: DRM/AMDgpu
Assignee: dri-devel(a)lists.freedesktop.org
…
[View More]Reporter: tempel.julian(a)gmail.com
Created attachment 138987
--> https://bugs.freedesktop.org/attachment.cgi?id=138987&action=edit
dmesg
When amdgpu.dc=1 and an Xorg compositor are enabled at the same time, there is
stuttering when moving windows.
It's most visible with Compton (which is completely stutter-free when
amdgpu.dc=0), but also KWin and to a lesser extent also Gnome-Mutter.
It happens also with GPU clocks forced to maximum, so it doesn't seem to be a
powersaving issue.
In the recent past, there was an issue with performance degrading when
amdgpu.dc=1 and an Xorg compositor are enabled and the hardware mouse cursor
was used, maybe it's still related (just guessing though)?
Tested with Linux 4.17 RC1 and drm-next-4.18-wip (4.16.1.52132fd03)
xorg-server 1.19.6+13+gd0d1a694f (amdgpu DDX & modesetting)
RX 560
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Fixing some of the low hanging fruits by moving the hw resource
parsing and assignment to encoder modeset. This series
prepares DPU resource management to switch to state based
resource tracking which is implemented in the next incoming
changes.
Thanks.
Jeykumar Sankaran (7):
drm/msm/dpu: move hw_inf encoder baseclass
drm/msm/dpu: remove phys_vid subclass
drm/msm/dpu: release resources on modeset failure
drm/msm/dpu: dont use encoder->crtc in atomic path
drm/msm/dpu: map mixer/…
[View More]ctl hw blocks in encoder modeset
drm/msm/dpu: assign intf to encoder in mode_set
drm/msm/dpu: check split role for single flush
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 64 +-------
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 73 +++++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 15 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 177 ++++++---------------
4 files changed, 118 insertions(+), 211 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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dpu_mdss_destroy() can get called not just from
msm_drm_uninit() but also from msm_drm_bind() in case
of any failures.
dpu_mdss_destroy() removes the icc voting by calling
icc_put. This could accidentally remove the voting
done by pm_runtime_enable.
To make the voting balanced add a minimum vote in
dpu_mdss_init() to avoid any unclocked access.
This change depends on the following patch which
introduces interconnect binding to MDSS driver:
https://patchwork.codeaurora.org/patch/708155/…
[View More]Signed-off-by: Abhinav Kumar <abhinavk(a)codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 38daf8a..bfabb9e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -44,6 +44,16 @@ static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
return 0;
}
+static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss)
+{
+ struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
+ int i;
+ u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
+
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
+}
+
static irqreturn_t dpu_mdss_irq(int irq, void *arg)
{
struct dpu_mdss *dpu_mdss = arg;
@@ -153,11 +163,9 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = &dpu_mdss->mp;
- int ret, i;
- u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
+ int ret;
- for (i = 0; i < dpu_mdss->num_paths; i++)
- icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
+ dpu_mdss_icc_request_bw(mdss);
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
@@ -266,6 +274,8 @@ int dpu_mdss_init(struct drm_device *dev)
pm_runtime_enable(dev->dev);
+ dpu_mdss_icc_request_bw(priv->mdss);
+
pm_runtime_get_sync(dev->dev);
dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
pm_runtime_put_sync(dev->dev);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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This adds initial support for the Mixel IP based mipi dphy as found on i.MX8
processors. It has support for the i.MX8MQ, support for other variants can be
added - once the platform specific parts are in - via the provided devdata.
The driver is somewhat based on what's found in NXPs BSP.
Public documentation on the DPHY's registers is currently thin in the i.MX8
reference manuals (even on the i.MX8QXP form 11/18) so most of the values were
taken from existing drivers. Newer NXP drivers have a …
[View More]bit more details so where
possible the timings are calculated and validated.
This is based on linux-next as of 2019-02-28 (which already has Maxime Ripard's
dphy configuration helpers).
I'll also send out an initial version of a NWL mipi dsi host controller
driver using this. A 4.18 based tree using this driver, nwl and dcss
(the later from NXPs BSP) can be found here:
https://source.puri.sm/guido.gunther/linux-imx8/commits/imx8-4.18-wip-nwl-d…
Changes form v3
* Check correct variable after devm_ioremap_resource
* Add Robert Chiras as Co-authored-by since he's the author
of the driver in NXPs BSP.
Changes from v2
* As per review comments from Fabio Estevam
* KConfig: select REGMAP_MMIO
* Drop phy_read
* Don't make phy_write inline
* Remove duplicate debugging output
* Comment style and typo fixes
* Add #defines's for PLL lock timing values
* Return correct error value when PLL fails to lock
* Check error when enabling clock
* Use devm_ioremap_resource
* As per review comments from Robert Chiras
* Deassert PD_DPHY after PLL lock (as per mixel ref manual)
* Assert PD_{DPHY,PLL} before power on (as per mixel ref manual)manual
* Add exit phy_op to reset CN/CM/CO
Changes from v1
* As per review comments from Fabio Estevam
* Kconfig: tristate mixel dphy support.
* Drop unused 'ret' in mixel_dphy_ref_power_off.
* Match values of DPHY_RXL{PRP,DRP} to those of
https://source.codeaurora.org/external/imx/linux-imx/log/?h=imx_4.14.78_1.0…
The previous values were based on 4.9.
* Use resource size on devm_ioremap, we have that in dt already.
* Use regmap so it's simple to dump the registers.
* Use regmap_read_poll_timeout instead of open coded loop.
* Add undocumented rxhs_settle register
* As per review comments from Sam Ravnborg
* Move driver to d/phy/freescale/
* Move SPDX-License-Identifier to top of file.
* Drop '/* #define DEBUG 1 */'.
* Use GPL-2.0+ since the vendor driver uses that as well.
* Drop the mutex, register access is now protected by regmap.
* Fix various style / indentation issues.
* Check for register read, write and ioremap errors
* Improve phy timing calculations
* Use LP clock rate where sensible, check for errors
* Use ad hoc forumulas for timings involving hs clock
* Switch from dphy_ops to devdata. Other i.MX8 variants
differ in register layout too
* Add Mixel Inc to vendor-prefixes.txt
Guido Günther (3):
dt-bindings: Add vendor prefix for Mixel Inc
dt-bindings: phy: Add documentation for mixel dphy
phy: Add driver for mixel dphy found on imx8
.../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
drivers/phy/freescale/Kconfig | 10 +
drivers/phy/freescale/Makefile | 1 +
.../phy/freescale/phy-fsl-imx8-mipi-dphy.c | 499 ++++++++++++++++++
5 files changed, 540 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
--
2.20.1
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