dri-devel April 2019

dri-devel@lists.freedesktop.org

307 participants
2114 discussions

[PATCH libdrm 1/8] new syncobj extension v3
by Chunming Zhou 09 Apr '19

09 Apr '19

v2: drop not implemented IOCTLs and flags v3: add transfer/signal ioctls Signed-off-by: Chunming Zhou <david1.zhou(a)amd.com> Signed-off-by: Christian König <christian.koenig(a)amd.com> --- include/drm/drm.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/drm/drm.h b/include/drm/drm.h index 85c685a2..26f51bca 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -729,8 +729,18 @@ struct drm_syncobj_handle { __u32 pad; }; +struct drm_syncobj_transfer { + __u32 src_handle; + __u32 dst_handle; + __u64 src_point; + __u64 dst_point; + __u32 flags; + __u32 pad; +}; + #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) struct drm_syncobj_wait { __u64 handles; /* absolute timeout */ @@ -741,12 +751,31 @@ struct drm_syncobj_wait { __u32 pad; }; +struct drm_syncobj_timeline_wait { + __u64 handles; + /* wait on specific timeline point for every handles*/ + __u64 points; + /* absolute timeout */ + __s64 timeout_nsec; + __u32 count_handles; + __u32 flags; + __u32 first_signaled; /* only valid when not waiting all */ + __u32 pad; +}; + struct drm_syncobj_array { __u64 handles; __u32 count_handles; __u32 pad; }; +struct drm_syncobj_timeline_array { + __u64 handles; + __u64 points; + __u32 count_handles; + __u32 pad; +}; + /* Query current scanout sequence number */ struct drm_crtc_get_sequence { __u32 crtc_id; /* requested crtc_id */ @@ -903,6 +932,12 @@ extern "C" { #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) +#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) +#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) + + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. -- 2.17.1

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[PATCH] drm/qxl: drop prime import/export callbacks
by Gerd Hoffmann 09 Apr '19

09 Apr '19

Also set prime_handle_to_fd and prime_fd_to_handle to NULL, so drm will not advertive DRM_PRIME_CAP_{IMPORT,EXPORT} to userspace. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- drivers/gpu/drm/qxl/qxl_drv.c | 4 ---- drivers/gpu/drm/qxl/qxl_prime.c | 14 -------------- 2 files changed, 18 deletions(-) diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index 13c8a662f9..ccb090f3ab 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -250,14 +250,10 @@ static struct drm_driver qxl_driver = { #if defined(CONFIG_DEBUG_FS) .debugfs_init = qxl_debugfs_init, #endif - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = drm_gem_prime_export, .gem_prime_import = drm_gem_prime_import, .gem_prime_pin = qxl_gem_prime_pin, .gem_prime_unpin = qxl_gem_prime_unpin, - .gem_prime_get_sg_table = qxl_gem_prime_get_sg_table, - .gem_prime_import_sg_table = qxl_gem_prime_import_sg_table, .gem_prime_vmap = qxl_gem_prime_vmap, .gem_prime_vunmap = qxl_gem_prime_vunmap, .gem_prime_mmap = qxl_gem_prime_mmap, diff --git a/drivers/gpu/drm/qxl/qxl_prime.c b/drivers/gpu/drm/qxl/qxl_prime.c index a55dece118..df65d3c1a7 100644 --- a/drivers/gpu/drm/qxl/qxl_prime.c +++ b/drivers/gpu/drm/qxl/qxl_prime.c @@ -38,20 +38,6 @@ void qxl_gem_prime_unpin(struct drm_gem_object *obj) WARN_ONCE(1, "not implemented"); } -struct sg_table *qxl_gem_prime_get_sg_table(struct drm_gem_object *obj) -{ - WARN_ONCE(1, "not implemented"); - return ERR_PTR(-ENOSYS); -} - -struct drm_gem_object *qxl_gem_prime_import_sg_table( - struct drm_device *dev, struct dma_buf_attachment *attach, - struct sg_table *table) -{ - WARN_ONCE(1, "not implemented"); - return ERR_PTR(-ENOSYS); -} - void *qxl_gem_prime_vmap(struct drm_gem_object *obj) { WARN_ONCE(1, "not implemented"); -- 2.9.3

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Re: [PATCH v2 05/13] pinctrl: sunxi: Prepare for alternative bias voltage setting methods
by Maxime Ripard 09 Apr '19

09 Apr '19

Hi, On Tue, Apr 09, 2019 at 02:24:44AM +0200, megous(a)megous.com wrote: > From: Ondrej Jirman <megous(a)megous.com> > > H6 has a different I/O voltage bias setting method than A80. Prepare > existing code for using alternative bias voltage setting methods. > > Signed-off-by: Ondrej Jirman <megous(a)megous.com> > --- > drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 41 +++++++++++++---------- > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 5 ++- > 3 files changed, 28 insertions(+), 20 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c > index da37d594a13d..3aa210079b18 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c > @@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { > .npins = ARRAY_SIZE(sun9i_a80_pins), > .irq_banks = 5, > .disable_strict_mode = true, > - .has_io_bias_cfg = true, > + .io_bias_cfg_variant = IO_BIAS_CFG_V1, > }; > > static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 8dd25caea2cf..b8dd58ef33b7 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -610,7 +610,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, > u32 val, reg; > int uV; > > - if (!pctl->desc->has_io_bias_cfg) > + if (!pctl->desc->io_bias_cfg_variant) > return 0; > > uV = regulator_get_voltage(supply); > @@ -621,23 +621,28 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, > if (uV == 0) > return 0; > > - /* Configured value must be equal or greater to actual voltage */ > - if (uV <= 1800000) > - val = 0x0; /* 1.8V */ > - else if (uV <= 2500000) > - val = 0x6; /* 2.5V */ > - else if (uV <= 2800000) > - val = 0x9; /* 2.8V */ > - else if (uV <= 3000000) > - val = 0xA; /* 3.0V */ > - else > - val = 0xD; /* 3.3V */ > - > - pin -= pctl->desc->pin_base; > - > - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); > - reg &= ~IO_BIAS_MASK; > - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); > + if (pctl->desc->io_bias_cfg_variant == IO_BIAS_CFG_V1) { > + /* > + * Configured value must be equal or greater to actual > + * voltage. > + */ > + if (uV <= 1800000) > + val = 0x0; /* 1.8V */ > + else if (uV <= 2500000) > + val = 0x6; /* 2.5V */ > + else if (uV <= 2800000) > + val = 0x9; /* 2.8V */ > + else if (uV <= 3000000) > + val = 0xA; /* 3.0V */ > + else > + val = 0xD; /* 3.3V */ > + > + pin -= pctl->desc->pin_base; > + > + reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); > + reg &= ~IO_BIAS_MASK; > + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); > + } > > return 0; > } > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > index ee15ab067b5f..642f667e99d2 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > @@ -95,6 +95,9 @@ > #define PINCTRL_SUN7I_A20 BIT(7) > #define PINCTRL_SUN8I_R40 BIT(8) > > +/* Bias voltage configuration done via Pn_GRP_CONFIG registers. */ > +#define IO_BIAS_CFG_V1 1 > + Can we turn this into an enum, and give them proper name? Mentionning an example in the commit would be great too. Something like: enum sunxi_desc_bias_voltage { /* Bias Voltage configuration is done through Pn_GRP_CONFIG registers, as seen on the A83t */ BIAS_VOLTAGE_GRP_CONFIG, }; etc. Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com

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Re: [linux-sunxi] [PATCH v2 02/13] arm64: dts: allwinner: h6: Add Orange Pi 3 DTS
by Jagan Teki 09 Apr '19

09 Apr '19

Based on the conversation about using common dtsi from this thread[1], I'm commenting here to make show the diff directly on the nodes, giving comments on each node so-that we can see the diff globally. On Tue, Apr 9, 2019 at 5:55 AM megous via linux-sunxi <linux-sunxi(a)googlegroups.com> wrote: > > From: Ondrej Jirman <megous(a)megous.com> > > Orange Pi 3 is a H6 based SBC made by Xulong, released in January 2019. It > has the following features: > > - Allwinner H6 quad-core 64-bit ARM Cortex-A53 > - GPU Mali-T720 > - 1GB or 2GB LPDDR3 RAM > - AXP805 PMIC > - AP6256 Wifi/BT 5.0 > - USB 2.0 host port (A) > - USB 2.0 micro usb, OTG > - USB 3.0 Host + 4 port USB hub (GL3510) > - Gigabit Ethernet (Realtek RTL8211E phy) > - HDMI 2.0 port > - soldered eMMC (optional) > - 3x LED (one is on the bottom) > - microphone > - audio jack > - PCIe > > Add basic support for the board. > > Signed-off-by: Ondrej Jirman <megous(a)megous.com> > --- > arch/arm64/boot/dts/allwinner/Makefile | 1 + > .../dts/allwinner/sun50i-h6-orangepi-3.dts | 216 ++++++++++++++++++ > 2 files changed, 217 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts > > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile > index e4dce2f6fa3a..285a7cb5135b 100644 > --- a/arch/arm64/boot/dts/allwinner/Makefile > +++ b/arch/arm64/boot/dts/allwinner/Makefile > @@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts > new file mode 100644 > index 000000000000..5fbc5e410883 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2019 Ondřej Jirman <megous(a)megous.com> > + */ > + > +/dts-v1/; > + > +#include "sun50i-h6.dtsi" > + > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + model = "OrangePi 3"; > + compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + power { > + label = "orangepi:red:power"; > + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ > + default-state = "on"; > + }; > + > + status { > + label = "orangepi:green:status"; > + gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ > + }; > + }; > + > + reg_vcc5v: vcc5v { > + /* board wide 5V supply directly from the DC jack */ > + compatible = "regulator-fixed"; > + regulator-name = "vcc-5v"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + }; > +}; all above nodes are common to all h6 opi boards. > + > +&cpu0 { > + cpu-supply = <&reg_dcdca>; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ehci3 { > + status = "okay"; > +}; common to all h6 opi boards. > + > +&mmc0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc0_pins>; > + vmmc-supply = <&reg_cldo1>; > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ > + bus-width = <4>; > + status = "okay"; > +}; common to all h6 opi boards. > + > +&ohci0 { > + status = "okay"; > +}; > + > +&ohci3 { > + status = "okay"; > +}; common to all h6 opi boards. > + > +&pio { > + vcc-pc-supply = <&reg_bldo2>; > + vcc-pd-supply = <&reg_cldo1>; > +}; > + > +&r_i2c { > + status = "okay"; > + > + axp805: pmic@36 { > + compatible = "x-powers,axp805", "x-powers,axp806"; > + reg = <0x36>; > + interrupt-parent = <&r_intc>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + interrupt-controller; > + #interrupt-cells = <1>; > + x-powers,self-working-mode; > + vina-supply = <&reg_vcc5v>; > + vinb-supply = <&reg_vcc5v>; > + vinc-supply = <&reg_vcc5v>; > + vind-supply = <&reg_vcc5v>; > + vine-supply = <&reg_vcc5v>; > + aldoin-supply = <&reg_vcc5v>; > + bldoin-supply = <&reg_vcc5v>; > + cldoin-supply = <&reg_vcc5v>; all these supply voltage regulators are common to h6 opi boards. > + > + regulators { > + reg_aldo1: aldo1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-pl-led-ir"; > + }; same like other h6 boards. > + > + reg_aldo2: aldo2 { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc33-audio-tv-ephy-mac"; > + }; rest of h6 opi boards used it for vcc-ac200, we may append ac200 and make it common since the voltage is same. > + > + /* ALDO3 is shorted to CLDO1 */ > + reg_aldo3: aldo3 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; > + }; same like above regulator. > + > + reg_bldo1: bldo1 { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "vcc18-dram-bias-pll"; same like other h6 boards. > + }; > + > + reg_bldo2: bldo2 { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "vcc-efuse-pcie-hdmi-pc"; > + }; same like other h6 boards. > + > + bldo3 { > + /* unused */ > + }; This is used in other h6 opi boards so we may attach status or re-enable it on board dts file. > + > + bldo4 { > + /* unused */ > + }; same like other h6 boards. > + > + reg_cldo1: cldo1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; > + }; same like other h6 boards. > + > + cldo2 { > + /* unused */ > + }; > + > + cldo3 { > + /* unused */ > + }; These two used for wifi, so we may define on board dts or attach status property. > + > + reg_dcdca: dcdca { > + regulator-always-on; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1160000>; > + regulator-name = "vdd-cpu"; > + }; > + > + reg_dcdcc: dcdcc { > + regulator-min-microvolt = <810000>; > + regulator-max-microvolt = <1080000>; > + regulator-name = "vdd-gpu"; > + }; > + > + reg_dcdcd: dcdcd { > + regulator-always-on; > + regulator-min-microvolt = <960000>; > + regulator-max-microvolt = <960000>; > + regulator-name = "vdd-sys"; > + }; > + > + reg_dcdce: dcdce { > + regulator-always-on; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-name = "vcc-dram"; > + }; > + > + sw { > + /* unused */ > + }; all above regulators are common to h6 boards. > + }; > + }; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_ph_pins>; > + status = "okay"; > +}; > + > +&usb2otg { > + /* > + * Beware that this board will not automatically disconnect > + * VBUS from DCIN, when self-powered and used as a peripheral. > + */ > + dr_mode = "otg"; > + status = "okay"; > +}; above nodes uart0, usb2otg are common to h6 opi boards. > + > +&usb2phy { > + usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ > + usb0_vbus-supply = <&reg_vcc5v>; > + usb3_vbus-supply = <&reg_vcc5v>; > + status = "okay"; > +}; > -- id detect pin can be differ, so we may move this on board specific dts. Note: the emac node is also common between h6 opi boards. [1] https://lkml.org/lkml/2019/4/5/857

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linux-next: build failure after merge of the drm-misc tree
by Stephen Rothwell 09 Apr '19

09 Apr '19

Hi all, After merging the drm-misc tree, today's linux-next build (powerpc allyesconfig) failed like this: drivers/gpu/drm/cirrus/cirrus.c: In function 'cirrus_fb_blit_rect': drivers/gpu/drm/cirrus/cirrus.c:310:25: error: implicit declaration of function '__io_virt'; did you mean '__do_irq'? [-Werror=implicit-function-declaration] drm_fb_memcpy_dstclip(__io_virt(cirrus->vram), ^~~~~~~~~ __do_irq drivers/gpu/drm/cirrus/cirrus.c:310:25: warning: passing argument 1 of 'drm_fb_memcpy_dstclip' makes pointer from integer without a cast [-Wint-conversion] drm_fb_memcpy_dstclip(__io_virt(cirrus->vram), ^~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/cirrus/cirrus.c:33: include/drm/drm_format_helper.h:18:34: note: expected 'void *' but argument is of type 'int' void drm_fb_memcpy_dstclip(void *dst, void *vaddr, struct drm_framebuffer *fb, ~~~~~~^~~ drivers/gpu/drm/cirrus/cirrus.c:314:37: warning: passing argument 1 of 'drm_fb_xrgb8888_to_rgb565_dstclip' makes pointer from integer without a cast [-Wint-conversion] drm_fb_xrgb8888_to_rgb565_dstclip(__io_virt(cirrus->vram), ^~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/cirrus/cirrus.c:33: include/drm/drm_format_helper.h:25:46: note: expected 'void *' but argument is of type 'int' void drm_fb_xrgb8888_to_rgb565_dstclip(void *dst, unsigned int dst_pitch, ~~~~~~^~~ drivers/gpu/drm/cirrus/cirrus.c:319:37: warning: passing argument 1 of 'drm_fb_xrgb8888_to_rgb888_dstclip' makes pointer from integer without a cast [-Wint-conversion] drm_fb_xrgb8888_to_rgb888_dstclip(__io_virt(cirrus->vram), ^~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/cirrus/cirrus.c:33: include/drm/drm_format_helper.h:28:46: note: expected 'void *' but argument is of type 'int' void drm_fb_xrgb8888_to_rgb888_dstclip(void *dst, unsigned int dst_pitch, ~~~~~~^~~ Caused by commit ab3e023b1b4c ("drm/cirrus: rewrite and modernize driver.") I have marked that driver BROKEN for today. -- Cheers, Stephen Rothwell

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[PATCH v4] dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU
by Neil Armstrong 09 Apr '19

09 Apr '19

Add the bindings for the Bifrost family of ARM Mali GPUs. The Bifrost GPU architecture is similar to the Midgard family, but with a different Shader Core & Execution Engine structures. Bindings are based on the Midgard family bindings, but the inner architectural changes makes it a separate family needing separate bindings. The Bifrost GPUs are present in a number of recent SoCs, like the Amlogic G12A Family, and many other vendors. The Amlogic vendor specific compatible is added to handle the specific IP integration differences and dependencies. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- .../bindings/gpu/arm,mali-bifrost.txt | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt Changes since v3: - Added note about discoverable model/revision - Enforced fixed defined irq order - Fixed typo in accommodate Changes since v2: - moved to a single compatible since HW is fully discoverable diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt new file mode 100644 index 000000000000..711c9ead17a2 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt @@ -0,0 +1,92 @@ +ARM Mali Bifrost GPU +==================== + +Required properties: + +- compatible : + * Since Mali Bifrost GPU model/revision if fully discoverable by reading + some determined registers, must contain the following: + + "arm,mali-bifrost" + * which must be preceded by one of the following vendor specifics: + + "amlogic,meson-g12a-mali" + +- reg : Physical base address of the device and length of the register area. + +- interrupts : Contains the three IRQ lines required by Mali Bifrost devices, + in the following defined order. + +- interrupt-names : Contains the names of IRQ resources in this exact defined + order: "job", "mmu", "gpu". + +Optional properties: + +- clocks : Phandle to clock for the Mali Bifrost device. + +- mali-supply : Phandle to regulator for the Mali device. Refer to + Documentation/devicetree/bindings/regulator/regulator.txt for details. + +- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt + for details. + +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accommodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-g12a-mali" + Required properties: + - resets : Should contain phandles of : + + GPU reset line + + GPU APB glue reset line + +Example for a Mali-G31: + +gpu@ffa30000 { + compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; + reg = <0xffe40000 0x10000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&clk CLKID_MALI>; + mali-supply = <&vdd_gpu>; + operating-points-v2 = <&gpu_opp_table>; + resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; +}; + +gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1250000>; + }; + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <1150000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1125000>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <1075000>; + }; + opp@266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <1025000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <925000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <912500>; + }; +}; -- 2.21.0

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Re: [PATCH v2 02/13] arm64: dts: allwinner: h6: Add Orange Pi 3 DTS
by Maxime Ripard 09 Apr '19

09 Apr '19

Hi, On Tue, Apr 09, 2019 at 02:24:41AM +0200, megous(a)megous.com wrote: > +&mmc0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc0_pins>; Since 5 minutes ago, that's now the default. > +&usb2otg { > + /* > + * Beware that this board will not automatically disconnect > + * VBUS from DCIN, when self-powered and used as a peripheral. > + */ > + dr_mode = "otg"; > + status = "okay"; > +}; As we were discussing, I guess leaving it as host is the safest option. I can fix both issues while applying if that's ok for you. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com

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[PATCH v2 01/13] dt-bindings: sunxi: Add compatible for OrangePi 3 board
by megous＠megous.com 09 Apr '19

09 Apr '19

From: Ondrej Jirman <megous(a)megous.com> Add new Xunlong Orange Pi 3 board compatible string to the bindings documentation. Signed-off-by: Ondrej Jirman <megous(a)megous.com> --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 11563d3f7c65..b82db740125b 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -711,6 +711,11 @@ properties: - const: xunlong,orangepi-2 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi 3 + items: + - const: xunlong,orangepi-3 + - const: allwinner,sun50i-h6 + - description: Xunlong OrangePi Lite items: - const: xunlong,orangepi-lite -- 2.21.0

2 1

linux-next: manual merge of the drm-misc tree with the drm tree
by Stephen Rothwell 09 Apr '19

09 Apr '19

Hi all, Today's linux-next merge of the drm-misc tree got conflicts in: drivers/gpu/drm/cirrus/cirrus_drv.h drivers/gpu/drm/cirrus/cirrus_ttm.c between commits: aa8e2435b3d4 ("drm/ttm: Define a single DRM_FILE_PAGE_OFFSET constant") 7d1500f9fbfc ("drm/ttm: Remove file_page_offset parameter from ttm_bo_device_init()") bed2dd84212e ("drm/ttm: Quick-test mmap offset in ttm_bo_mmap()") from the drm tree and commit: ab3e023b1b4c ("drm/cirrus: rewrite and modernize driver.") from the drm-misc tree. I fixed it up (I just removed the files) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell

2 1

[Bug 110363] done
by bugzilla-daemon＠freedesktop.org 09 Apr '19

09 Apr '19

https://bugs.freedesktop.org/show_bug.cgi?id=110363 rj <rohanjhaveri007(a)gmail.com> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rohanjhaveri007(a)gmail.com Assignee|dri-devel(a)lists.freedesktop |rohanjhaveri007(a)gmail.com |.org | --- Comment #1 from rj <rohanjhaveri007(a)gmail.com> --- Created attachment 143907 --> https://bugs.freedesktop.org/attachment.cgi?id=143907&action=edit voucher validation not work -- You are receiving this mail because: You are the assignee for the bug.

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dri-devel April 2019