dri-devel September 2019

dri-devel@lists.freedesktop.org

315 participants
2278 discussions

[PULL] drm-intel-next-fixes
by Rodrigo Vivi 27 Sep '19

27 Sep '19

Hi Dave and Daniel, This should've gone out yesterday, but apparently I had some issue with my mutt here. Anyway, nothing that couldn't wait for rc2 Here goes drm-intel-next-fixes-2019-09-26: - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. Thanks, Rodrigo. The following changes since commit 6e5c5272ca00809aae20817efb6f25881268b50b: drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap (2019-09-06 09:53:15 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2019-09-26 for you to fetch changes up to 458863e08e13ecf22b9ba1ee6d4baba0ce9990ea: drm/i915: Mark contents as dirty on a write fault (2019-09-24 09:57:28 -0700) ---------------------------------------------------------------- - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. ---------------------------------------------------------------- Chris Wilson (8): drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ drm/i915/execlists: Remove incorrect BUG_ON for schedule-out drm/i915: Perform GGTT restore much earlier during resume drm/i915: Don't mix srcu tag and negative error codes drm/i915: Extend Haswell GT1 PSMI workaround to all drm/i915: Verify the engine after acquiring the active.lock drm/i915: Prevent bonded requests from overtaking each other on preemption drm/i915: Mark contents as dirty on a write fault Kenneth Graunke (1): drm/i915: Whitelist COMMON_SLICE_CHICKEN2 Ville Syrjälä (1): drm/i915: Bump skl+ max plane width to 5k for linear/x-tiled drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++++- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +++++++----- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 3 --- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++--------- drivers/gpu/drm/i915/gt/intel_reset.c | 8 +++----- drivers/gpu/drm/i915/gt/intel_reset.h | 2 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++----- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_request.c | 25 ++++++++++++++++++++++--- drivers/gpu/drm/i915/selftests/i915_gem.c | 6 ++++++ 11 files changed, 74 insertions(+), 33 deletions(-)

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[PATCH V3 1/3] drm/panel: simple: Add Logic PD Type 28 display support
by Adam Ford 27 Sep '19

27 Sep '19

Previously, there was an omap panel-dpi driver that would read generic timings from the device tree and set the display timing accordingly. This driver was removed so the screen no longer functions. This patch modifies the panel-simple file to setup the timings to the same values previously used. Fixes: 8bf4b1621178 ("drm/omap: Remove panel-dpi driver") Signed-off-by: Adam Ford <aford173(a)gmail.com> Reviewed-by: Sam Ravnborg <sam(a)ravnborg.org> --- V3: No change V2: No change diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 28fa6ba7b767..8abb31f83ffc 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2048,6 +2048,40 @@ static const struct drm_display_mode mitsubishi_aa070mc01_mode = { .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, }; +static const struct drm_display_mode logicpd_type_28_mode = { + .clock = 9000, + .hdisplay = 480, + .hsync_start = 480 + 3, + .hsync_end = 480 + 3 + 42, + .htotal = 480 + 3 + 42 + 2, + + .vdisplay = 272, + .vsync_start = 272 + 2, + .vsync_end = 272 + 2 + 11, + .vtotal = 272 + 2 + 11 + 3, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, +}; + +static const struct panel_desc logicpd_type_28 = { + .modes = &logicpd_type_28_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 105, + .height = 67, + }, + .delay = { + .prepare = 200, + .enable = 200, + .unprepare = 200, + .disable = 200, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | + DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, +}; + static const struct panel_desc mitsubishi_aa070mc01 = { .modes = &mitsubishi_aa070mc01_mode, .num_modes = 1, @@ -3264,6 +3298,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "lg,lp129qe", .data = &lg_lp129qe, + }, { + .compatible = "logicpd,type28", + .data = &logicpd_type_28, }, { .compatible = "mitsubishi,aa070mc01-ca1", .data = &mitsubishi_aa070mc01, -- 2.17.1

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[git pull] drm fixes for 5.4-rc1
by Dave Airlie 27 Sep '19

27 Sep '19

Hey Linus, Fixes built up over the past 1.5 weeks or so, it's two weeks of amdgpu, some core cleanups and some panfrost fixes. I also finally figured out why my desktop was slow to do a bunch of stuff (someone gave it an IPv6 address which can't reach anything!). Dave. drm-next-2019-09-27: drm fixes for 5.4-rc1 core: - Some cleanups and fixes in the self-refresh helpers - Some cleanups and fixes in the atomic helpers amdgpu: - Fix a 64 bit divide - Prevent a memory leak in a failure case in dc - Load proper gfx firmware on navi14 variants - Add more navi12 and navi14 PCI ids - Misc fixes for renoir - Fix bandwidth issues with multiple displays on vega20 - Support for Dali - Fix a possible oops with KFD on hawaii - Fix for backlight level after resume on some APUs - Other misc fixes panfrost: - Multiple panfrost fixes for regulator support and page fault handling The following changes since commit 945b584c94f8c665b2df3834a8a6a8faf256cd5f: Merge branch 'linux-5.4' of git://github.com/skeggsb/linux into drm-next (2019-09-17 16:31:34 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-next-2019-09-27 for you to fetch changes up to 3e2cb6d89325dc36a03937a2b82fc7eb902c96b0: Merge tag 'drm-fixes-5.4-2019-09-25' of git://people.freedesktop.org/~agd5f/linux into drm-next (2019-09-26 11:59:40 +1000) ---------------------------------------------------------------- drm fixes for 5.4-rc1 core: - Some cleanups and fixes in the self-refresh helpers - Some cleanups and fixes in the atomic helpers amdgpu: - Fix a 64 bit divide - Prevent a memory leak in a failure case in dc - Load proper gfx firmware on navi14 variants - Add more navi12 and navi14 PCI ids - Misc fixes for renoir - Fix bandwidth issues with multiple displays on vega20 - Support for Dali - Fix a possible oops with KFD on hawaii - Fix for backlight level after resume on some APUs - Other misc fixes panfrost: - Multiple panfrost fixes for regulator support and page fault handling ---------------------------------------------------------------- Aaron Liu (3): drm/amdgpu: disable stutter mode for renoir drm/amd/display: update renoir_ip_offset.h drm/amdgpu: remove program of lbpw for renoir Alex Deucher (3): drm/amdgpu: flag navi12 and 14 as experimental for 5.4 drm/amdgpu/display: fix 64 bit divide drm/amdgpu/display: include slab.h in dcn21_resource.c Andrey Grodzovsky (2): drm/amdgpu: Add smu lock around in pp_smu_i2c_bus_access drm/amdgpu: Remove clock gating restore. Bhawanpreet Lakha (2): drm/amd/display: add Asic ID for Dali drm/amd/display: Implement voltage limitation for dali Charlene Liu (1): drm/amd/display: dce11.x /dce12 update formula input Daniel Vetter (4): drm/kms: Duct-tape for mode object lifetime checks drm/atomic: Take the atomic toys away from X drm/atomic: Reject FLIP_ASYNC unconditionally drm/atomic: Rename crtc_state->pageflip_flags to async_flip Dave Airlie (2): Merge tag 'drm-misc-next-fixes-2019-09-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Merge tag 'drm-fixes-5.4-2019-09-25' of git://people.freedesktop.org/~agd5f/linux into drm-next Felix Kuehling (1): drm/amdgpu: Fix KFD-related kernel oops on Hawaii Hans de Goede (1): drm/radeon: Bail earlier when radeon.cik_/si_support=0 is passed Jay Cornwall (1): drm/amdkfd: Swap trap temporary registers in gfx10 trap handler Kai-Heng Feng (1): drm/amd/display: Restore backlight brightness after system resume Mark Brown (1): drm/panfrost: Fix regulator_get_optional() misuse Navid Emamdoost (1): drm/amd/display: prevent memory leak Prike Liang (2): drm/amd/amdgpu: power up sdma engine when S3 resume back drm/amd/powerplay: implement sysfs for getting dpm clock Rob Clark (1): Revert "drm/bridge: adv7511: Attach to DSI host at probe time" Roman Li (1): drm/amd/display: Add stereo mux and dig programming calls for dcn21 Sean Paul (2): drm: Fix kerneldoc and remove unused struct member in self_refresh helper drm: Measure Self Refresh Entry/Exit times to avoid thrashing Steven Price (2): drm/panfrost: Remove NULL checks for regulator drm/panfrost: Prevent race when handling page fault Tianci.Yin (3): drm/amdgpu: add navi14 PCI ID for work station SKU drm/amdgpu: add navi12 pci id drm/amdgpu/gfx10: add support for wks firmware loading Trek (1): drm/amdgpu: Check for valid number of registers to read Zhan Liu (1): drm/amd/display: Add missing HBM support and raise Vega20's uclk. drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 +++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 - drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +-- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 10 ++- drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 6 +- .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 10 +-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++ .../amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 27 ++++++-- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 1 + .../drm/amd/display/dc/dce110/dce110_resource.c | 1 + .../drm/amd/display/dc/dce112/dce112_resource.c | 17 +++-- .../drm/amd/display/dc/dce120/dce120_resource.c | 12 +++- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 + .../amd/display/dc/gpio/dcn21/hw_factory_dcn21.c | 38 ++++++++++- .../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 3 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++- drivers/gpu/drm/amd/include/renoir_ip_offset.h | 2 +- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 ++- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 + drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 70 +++++++++++++++++++++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 25 ++++++++ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 12 +--- drivers/gpu/drm/drm_atomic_helper.c | 22 ++++++- drivers/gpu/drm/drm_atomic_state_helper.c | 2 +- drivers/gpu/drm/drm_atomic_uapi.c | 3 +- drivers/gpu/drm/drm_drv.c | 4 +- drivers/gpu/drm/drm_ioctl.c | 7 ++- drivers/gpu/drm/drm_mode_object.c | 4 +- drivers/gpu/drm/drm_self_refresh_helper.c | 73 +++++++++++++++++++--- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 +- drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 ++- drivers/gpu/drm/panfrost/panfrost_device.c | 8 +-- drivers/gpu/drm/panfrost/panfrost_mmu.c | 55 ++++++++++------ drivers/gpu/drm/radeon/radeon_drv.c | 31 +++++++++ drivers/gpu/drm/radeon/radeon_kms.c | 25 -------- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +- include/drm/drm_crtc.h | 10 +-- include/drm/drm_self_refresh_helper.h | 6 +- 46 files changed, 444 insertions(+), 146 deletions(-)

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Re: [Nouveau] Is Nouveau really using the io_reserve_lru?
by Koenig, Christian 27 Sep '19

27 Sep '19

Am 27.09.2019 20:07 schrieb Ilia Mirkin <imirkin(a)alum.mit.edu>: On Thu, Sep 26, 2019 at 5:44 PM Ben Skeggs <skeggsb(a)gmail.com> wrote: > > On Tue, 24 Sep 2019 at 22:19, Christian König > <ckoenig.leichtzumerken(a)gmail.com> wrote: > > > > Hi guys, > > > > while working through more old TTM functionality I stumbled over the > > io_reserve_lru. > > > > Basic idea is that when this flag is set the driver->io_mem_reserve() > > callback can return -EAGAIN resulting in unmapping of other BOs. > > > > But Nouveau doesn't seem to return -EAGAIN in the call path of > > io_mem_reserve anywhere. > I believe this is a bug in Nouveau. We *should* be returning -EAGAIN > if we fail to find space in BAR1 to map the BO into. Could this lead to SIGBUS in userspace, esp related to resume and similar situations? Yes, I would say that's exactly what would happen. Christian. A user has been experiencing this in a tricky-to-reproduce scenario with a ton of vram dedicated to framebuffers and so on (3x 4K), and the nouveau ddx falls back to memcpy in certain cases. -ilia

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Is Nouveau really using the io_reserve_lru?
by Christian König 27 Sep '19

27 Sep '19

Hi guys, while working through more old TTM functionality I stumbled over the io_reserve_lru. Basic idea is that when this flag is set the driver->io_mem_reserve() callback can return -EAGAIN resulting in unmapping of other BOs. But Nouveau doesn't seem to return -EAGAIN in the call path of io_mem_reserve anywhere. So is this unused or am I missing something? Regards, Christian.

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[PATCH] drm/komeda: Fix typos in komeda_splitter_validate
by Mihail Atanassov 27 Sep '19

27 Sep '19

Fix both the string and the struct member being printed. Fixes: 264b9436d23b ("drm/komeda: Enable writeback split support") Signed-off-by: Mihail Atanassov <mihail.atanassov(a)arm.com> --- drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 950235af1e79..de64a6a9964e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -564,8 +564,8 @@ komeda_splitter_validate(struct komeda_splitter *splitter, } if (!in_range(&splitter->vsize, dflow->in_h)) { - DRM_DEBUG_ATOMIC("split in_in: %d exceed the acceptable range.\n", - dflow->in_w); + DRM_DEBUG_ATOMIC("split in_h: %d exceed the acceptable range.\n", + dflow->in_h); return -EINVAL; } -- 2.23.0

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[Bug 111747] [CI][DRMTIP] igt@ - incomplete - Jenkins gives up
by bugzilla-daemon＠freedesktop.org 27 Sep '19

27 Sep '19

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[PATCH] drm/komeda: prevent memory leak in komeda_wb_connector_add
by Navid Emamdoost 27 Sep '19

27 Sep '19

In komeda_wb_connector_add if drm_writeback_connector_init fails the allocated memory for kwb_conn should be released. Signed-off-by: Navid Emamdoost <navid.emamdoost(a)gmail.com> --- drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c index 2851cac94d86..75133f967fdb 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c @@ -166,8 +166,10 @@ static int komeda_wb_connector_add(struct komeda_kms_dev *kms, &komeda_wb_encoder_helper_funcs, formats, n_formats); komeda_put_fourcc_list(formats); - if (err) + if (err) { + kfree(kwb_conn); return err; + } drm_connector_helper_add(&wb_conn->base, &komeda_wb_conn_helper_funcs); -- 2.17.1

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[PATCH] drm/komeda: SW workaround for D71 doesn't flush shadow registers
by Lowry Li (Arm Technology China) 27 Sep '19

27 Sep '19

This is a SW workaround for shadow un-flushed when together with the DOU Timing-disable. D71 HW doesn't update shadow registers when display output is turned off. So when we disable all pipeline components together with display output disabling by one flush or one operation, the disable operation updated registers will not be flushed or valid in HW, which may lead problem. To workaround this problem, introduce a two phase disable for pipeline disable. Phase1: Disable components with display is on and flush it, this phase for flushing or validating the shadow registers. Phase2: Turn-off display output. Signed-off-by: Lowry Li (Arm Technology China) <lowry.li(a)arm.com> --- .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 16 ++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 73 ++++++++++++------- .../drm/arm/display/komeda/komeda_pipeline.h | 14 +++- .../display/komeda/komeda_pipeline_state.c | 30 +++++++- 4 files changed, 103 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c index 2151cb3f9e68..e74069ef3b7b 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -487,6 +487,22 @@ static int d71_enum_resources(struct komeda_dev *mdev) err = PTR_ERR(pipe); goto err_cleanup; } + + /* D71 HW doesn't update shadow registers when display output + * is turning off, so when we disable all pipeline components + * together with display output disable by one flush or one + * operation, the disable operation updated registers will not + * be flush to or valid in HW, which may leads problem. + * To workaround this problem, introduce a two phase disable. + * Phase1: Disabling components with display is on to make sure + * the disable can be flushed to HW. + * Phase2: Only turn-off display output. + */ + value = KOMEDA_PIPELINE_IMPROCS | + BIT(KOMEDA_COMPONENT_TIMING_CTRLR); + + pipe->standalone_disabled_comps = value; + d71->pipes[i] = to_d71_pipeline(pipe); } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 3155bb17ea1b..c0c803d56d5c 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -280,20 +280,53 @@ komeda_crtc_atomic_enable(struct drm_crtc *crtc, komeda_crtc_do_flush(crtc, old); } +static void +komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, + struct completion *input_flip_done) +{ + struct drm_device *drm = kcrtc->base.dev; + struct komeda_dev *mdev = kcrtc->master->mdev; + struct completion *flip_done; + struct completion temp; + int timeout; + + /* if caller doesn't send a flip_done, use a private flip_done */ + if (input_flip_done) { + flip_done = input_flip_done; + } else { + init_completion(&temp); + kcrtc->disable_done = &temp; + flip_done = &temp; + } + + mdev->funcs->flush(mdev, kcrtc->master->id, 0); + + /* wait the flip take affect.*/ + timeout = wait_for_completion_timeout(flip_done, HZ); + if (timeout == 0) { + DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id); + if (!input_flip_done) { + unsigned long flags; + + spin_lock_irqsave(&drm->event_lock, flags); + kcrtc->disable_done = NULL; + spin_unlock_irqrestore(&drm->event_lock, flags); + } + } +} + static void komeda_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old) { struct komeda_crtc *kcrtc = to_kcrtc(crtc); struct komeda_crtc_state *old_st = to_kcrtc_st(old); - struct komeda_dev *mdev = crtc->dev->dev_private; struct komeda_pipeline *master = kcrtc->master; struct komeda_pipeline *slave = kcrtc->slave; struct completion *disable_done = &crtc->state->commit->flip_done; - struct completion temp; - int timeout; + bool needs_phase2 = false; - DRM_DEBUG_ATOMIC("CRTC%d_DISABLE: active_pipes: 0x%x, affected: 0x%x.\n", + DRM_DEBUG_ATOMIC("CRTC%d_DISABLE: active_pipes: 0x%x, affected: 0x%x\n", drm_crtc_index(crtc), old_st->active_pipes, old_st->affected_pipes); @@ -301,7 +334,7 @@ komeda_crtc_atomic_disable(struct drm_crtc *crtc, komeda_pipeline_disable(slave, old->state); if (has_bit(master->id, old_st->active_pipes)) - komeda_pipeline_disable(master, old->state); + needs_phase2 = komeda_pipeline_disable(master, old->state); /* crtc_disable has two scenarios according to the state->active switch. * 1. active -> inactive @@ -320,30 +353,20 @@ komeda_crtc_atomic_disable(struct drm_crtc *crtc, * That's also the reason why skip modeset commit in * komeda_crtc_atomic_flush() */ - if (crtc->state->active) { - struct komeda_pipeline_state *pipe_st; - /* clear the old active_comps to zero */ - pipe_st = komeda_pipeline_get_old_state(master, old->state); - pipe_st->active_comps = 0; + disable_done = (needs_phase2 || crtc->state->active) ? + NULL : &crtc->state->commit->flip_done; - init_completion(&temp); - kcrtc->disable_done = &temp; - disable_done = &temp; - } + /* wait phase 1 disable done */ + komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done); - mdev->funcs->flush(mdev, master->id, 0); + /* phase 2 */ + if (needs_phase2) { + komeda_pipeline_disable(kcrtc->master, old->state); - /* wait the disable take affect.*/ - timeout = wait_for_completion_timeout(disable_done, HZ); - if (timeout == 0) { - DRM_ERROR("disable pipeline%d timeout.\n", kcrtc->master->id); - if (crtc->state->active) { - unsigned long flags; + disable_done = crtc->state->active ? + NULL : &crtc->state->commit->flip_done; - spin_lock_irqsave(&crtc->dev->event_lock, flags); - kcrtc->disable_done = NULL; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - } + komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done); } drm_crtc_vblank_off(crtc); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index 4eac23ef56c1..2afd07579138 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -496,6 +496,18 @@ struct komeda_pipeline { int id; /** @avail_comps: available components mask of pipeline */ u32 avail_comps; + /** + * @standalone_disabled_comps: + * + * When disable the pipeline, some components can not be disabled + * together with others, but need a sparated and standalone disable. + * The standalone_disabled_comps are the components which need to be + * disabled standalone, and this concept also introduce concept of + * two phase. + * phase 1: for disabling the common components. + * phase 2: for disabling the standalong_disabled_comps. + */ + u32 standalone_disabled_comps; /** @n_layers: the number of layer on @layers */ int n_layers; /** @layers: the pipeline layers */ @@ -674,7 +686,7 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_pipeline_state * komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, struct drm_atomic_state *state); -void komeda_pipeline_disable(struct komeda_pipeline *pipe, +bool komeda_pipeline_disable(struct komeda_pipeline *pipe, struct drm_atomic_state *old_state); void komeda_pipeline_update(struct komeda_pipeline *pipe, struct drm_atomic_state *old_state); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index f2c5d6c8f508..7699322949bb 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -1899,7 +1899,17 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, return 0; } -void komeda_pipeline_disable(struct komeda_pipeline *pipe, +/* Since standalong disabled components must be disabled separately and in the + * last, So a complete disable operation may needs to call pipeline_disable + * twice (two phase disabling). + * Phase 1: disable the common components, flush it. + * Phase 2: disable the standalone disabled components, flush it. + * + * RETURNS: + * true: disable is not complete, needs a phase 2 disable. + * false: disable is complete. + */ +bool komeda_pipeline_disable(struct komeda_pipeline *pipe, struct drm_atomic_state *old_state) { struct komeda_pipeline_state *old; @@ -1909,9 +1919,14 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe, old = komeda_pipeline_get_old_state(pipe, old_state); - disabling_comps = old->active_comps; - DRM_DEBUG_ATOMIC("PIPE%d: disabling_comps: 0x%x.\n", - pipe->id, disabling_comps); + disabling_comps = old->active_comps & + (~pipe->standalone_disabled_comps); + if (!disabling_comps) + disabling_comps = old->active_comps & + pipe->standalone_disabled_comps; + + DRM_DEBUG_ATOMIC("PIPE%d: active_comps: 0x%x, disabling_comps: 0x%x.\n", + pipe->id, old->active_comps, disabling_comps); dp_for_each_set_bit(id, disabling_comps) { c = komeda_pipeline_get_component(pipe, id); @@ -1929,6 +1944,13 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe, c->funcs->disable(c); } + + /* Update the pipeline state, if there are components that are still + * active, return true for calling the phase 2 disable. + */ + old->active_comps &= ~disabling_comps; + + return old->active_comps ? true : false; } void komeda_pipeline_update(struct komeda_pipeline *pipe, -- 2.17.1

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[Bug 111747] [CI][DRMTIP] igt@ - incomplete - Jenkins gives up
by bugzilla-daemon＠freedesktop.org 27 Sep '19

27 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=111747 --- Comment #8 from CI Bug Log <cibuglog(a)gmail.com> --- A CI Bug Log filter associated to this bug has been updated: {- TGL: igt@* -incomplete - Abort requested by .* terminating children -} {+ TGL: igt@* -incomplete - Abort requested by .* terminating children +} No new failures caught with the new filter -- You are receiving this mail because: You are the assignee for the bug.

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dri-devel September 2019