dri-devel September 2019

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2278 discussions

[PATCH] drm/rockchip: Add AFBC support
by Andrzej Pietrasiewicz 25 Sep '19

25 Sep '19

From: Ezequiel Garcia <ezequiel(a)collabora.com> AFBC is a proprietary lossless image compression protocol and format. It helps reduce memory bandwidth of the graphics pipeline operations. This, in turn, improves power efficiency. Signed-off-by: Ezequiel Garcia <ezequiel(a)collabora.com> [locking improvements] Signed-off-by: Tomeu Vizoso <tomeu.vizoso(a)collabora.com> [squashing the above, commit message and Rockchip AFBC modifier] Signed-off-by: Andrzej Pietrasiewicz <andrzej.p(a)collabora.com> --- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 27 ++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 94 ++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 12 +++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 18 ++++ include/uapi/drm/drm_fourcc.h | 3 + 5 files changed, 151 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 64ca87cf6d50..5178939a9c29 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -24,6 +24,27 @@ static const struct drm_framebuffer_funcs rockchip_drm_fb_funcs = { .dirty = drm_atomic_helper_dirtyfb, }; +static int +rockchip_verify_afbc_mod(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + if (mode_cmd->modifier[0] & + ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_ROCKCHIP)) { + DRM_DEV_ERROR(dev->dev, + "Unsupported format modifier 0x%llx\n", + mode_cmd->modifier[0]); + return -EINVAL; + } + + if (mode_cmd->width > 2560) { + DRM_DEV_ERROR(dev->dev, + "Unsupported width %d\n", mode_cmd->width); + return -EINVAL; + } + + return 0; +} + static struct drm_framebuffer * rockchip_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **obj, unsigned int num_planes) @@ -32,6 +53,12 @@ rockchip_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cm int ret; int i; + if (mode_cmd->modifier[0]) { + ret = rockchip_verify_afbc_mod(dev, mode_cmd); + if (ret) + return ERR_PTR(ret); + } + fb = kzalloc(sizeof(*fb), GFP_KERNEL); if (!fb) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 21b68eea46cc..50bf214d21da 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -46,6 +46,13 @@ vop_reg_set(vop, &win->phy->scl->ext->name, \ win->base, ~0, v, #name) +#define VOP_AFBC_SET(x, name, v) \ + do { \ + if (vop->data->afbc) \ + vop_reg_set(vop, &vop->data->afbc->name, \ + 0, ~0, v, #name); \ + } while (0) + #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ do { \ if (win_yuv2yuv && win_yuv2yuv->name.mask) \ @@ -123,6 +130,8 @@ struct vop { struct drm_device *drm_dev; bool is_enabled; + struct vop_win *afbc_win; + struct completion dsp_hold_completion; /* protected by dev->event_lock */ @@ -245,6 +254,30 @@ static bool has_rb_swapped(uint32_t format) } } +#define AFBC_FMT_RGB565 0x0 +#define AFBC_FMT_U8U8U8U8 0x5 +#define AFBC_FMT_U8U8U8 0x4 + +static int vop_convert_afbc_format(uint32_t format) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + return AFBC_FMT_U8U8U8U8; + case DRM_FORMAT_RGB888: + case DRM_FORMAT_BGR888: + return AFBC_FMT_U8U8U8; + case DRM_FORMAT_RGB565: + case DRM_FORMAT_BGR565: + return AFBC_FMT_RGB565; + default: + DRM_ERROR("unsupported afbc format[%08x]\n", format); + return -EINVAL; + } +} + static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { @@ -587,10 +620,16 @@ static int vop_enable(struct drm_crtc *crtc) vop_win_disable(vop, win); } - spin_unlock(&vop->reg_lock); + + if (vop->data->afbc) { + VOP_AFBC_SET(vop, enable, 0); + vop->afbc_win = NULL; + } vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); + /* * At here, vop clock & iommu is enable, R/W vop regs would be safe. */ @@ -719,6 +758,32 @@ static int vop_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } + if (fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_ROCKCHIP)) { + struct vop *vop = to_vop(crtc); + + if (!vop->data->afbc) { + DRM_ERROR("VOP does not support AFBC\n"); + return -EINVAL; + } + + ret = vop_convert_afbc_format(fb->format->format); + if (ret < 0) + return ret; + + if (state->src.x1 || state->src.y1) { + DRM_ERROR("AFBC does not support offset display\n"); + DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n", + state->src.x1, state->src.y1, fb->offsets[0]); + return -EINVAL; + } + + if (state->rotation && state->rotation != DRM_MODE_ROTATE_0) { + DRM_ERROR("AFBC does not support rotation\n"); + DRM_ERROR("rotation=%d\n", state->rotation); + return -EINVAL; + } + } + return 0; } @@ -732,6 +797,9 @@ static void vop_plane_atomic_disable(struct drm_plane *plane, if (!old_state->crtc) return; + if (vop->afbc_win == vop_win) + vop->afbc_win = NULL; + spin_lock(&vop->reg_lock); vop_win_disable(vop, win); @@ -774,6 +842,9 @@ static void vop_plane_atomic_update(struct drm_plane *plane, if (WARN_ON(!vop->is_enabled)) return; + if (vop->afbc_win == vop_win) + vop->afbc_win = NULL; + if (!state->visible) { vop_plane_atomic_disable(plane, old_state); return; @@ -808,6 +879,20 @@ static void vop_plane_atomic_update(struct drm_plane *plane, spin_lock(&vop->reg_lock); + if (fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_ROCKCHIP)) { + int afbc_format = vop_convert_afbc_format(fb->format->format); + + VOP_AFBC_SET(vop, format, afbc_format | 1 << 4); + VOP_AFBC_SET(vop, hreg_block_split, 0); + VOP_AFBC_SET(vop, win_sel, win_index); + VOP_AFBC_SET(vop, hdr_ptr, dma_addr); + VOP_AFBC_SET(vop, pic_size, act_info); + + vop->afbc_win = vop_win; + + pr_info("AFBC on plane %s\n", plane->name); + } + VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); @@ -1163,6 +1248,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, spin_lock(&vop->reg_lock); + VOP_AFBC_SET(vop, enable, vop->afbc_win ? 0x1 : 0); vop_cfg_done(vop); spin_unlock(&vop->reg_lock); @@ -1471,7 +1557,8 @@ static int vop_create_crtc(struct vop *vop) 0, &vop_plane_funcs, win_data->phy->data_formats, win_data->phy->nformats, - NULL, win_data->type, NULL); + win_data->phy->format_modifiers, + win_data->type, NULL); if (ret) { DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", ret); @@ -1511,7 +1598,8 @@ static int vop_create_crtc(struct vop *vop) &vop_plane_funcs, win_data->phy->data_formats, win_data->phy->nformats, - NULL, win_data->type, NULL); + win_data->phy->format_modifiers, + win_data->type, NULL); if (ret) { DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", ret); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 2149a889c29d..dc8b12025269 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -77,6 +77,16 @@ struct vop_misc { struct vop_reg global_regdone_en; }; +struct vop_afbc { + struct vop_reg enable; + struct vop_reg win_sel; + struct vop_reg format; + struct vop_reg hreg_block_split; + struct vop_reg pic_size; + struct vop_reg hdr_ptr; + struct vop_reg rstn; +}; + struct vop_intr { const int *intrs; uint32_t nintrs; @@ -128,6 +138,7 @@ struct vop_win_phy { const struct vop_scl_regs *scl; const uint32_t *data_formats; uint32_t nformats; + const uint64_t *format_modifiers; struct vop_reg enable; struct vop_reg gate; @@ -169,6 +180,7 @@ struct vop_data { const struct vop_output *output; const struct vop_win_yuv2yuv_data *win_yuv2yuv; const struct vop_win_data *win; + const struct vop_afbc *afbc; unsigned int win_size; #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 7b9c74750f6d..e9ff0c43c396 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -30,6 +30,12 @@ #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ _VOP_REG(off, _mask, _shift, true, false) +static const uint64_t format_modifiers_afbc[] = { + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_ROCKCHIP), + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -667,6 +673,7 @@ static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, .data_formats = formats_win_full, .nformats = ARRAY_SIZE(formats_win_full), + .format_modifiers = format_modifiers_afbc, .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), @@ -758,6 +765,16 @@ static const struct vop_data rk3366_vop = { .win_size = ARRAY_SIZE(rk3368_vop_win_data), }; +static const struct vop_afbc rk3399_afbc = { + .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3), + .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0), + .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1), + .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16), + .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21), + .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0), + .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0), +}; + static const struct vop_output rk3399_output = { .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), @@ -808,6 +825,7 @@ static const struct vop_data rk3399_vop_big = { .modeset = &rk3288_modeset, .output = &rk3399_output, .misc = &rk3368_misc, + .afbc = &rk3399_afbc, .win = rk3368_vop_win_data, .win_size = ARRAY_SIZE(rk3368_vop_win_data), .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a..ba6caf06c824 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -742,6 +742,9 @@ extern "C" { */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +#define AFBC_FORMAT_MOD_ROCKCHIP \ + (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE) + /* * Allwinner tiled modifier * -- 2.17.1

5 7

[Bug 111815] hwjhjhra
by bugzilla-daemon＠freedesktop.org 25 Sep '19

25 Sep '19

1 0

[Bug 111814] hello hello hello
by bugzilla-daemon＠freedesktop.org 25 Sep '19

25 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=111814 Bug ID: 111814 Summary: hello hello hello Product: DRI Version: XOrg git Hardware: x86-64 (AMD64) OS: All Status: NEW Severity: critical Priority: not set Component: General Assignee: dri-devel(a)lists.freedesktop.org Reporter: vineethaprakash97(a)gmail.com hello world -- You are receiving this mail because: You are the assignee for the bug.

1 1

[PATCH v2] drm/panfrost: Reduce the amount of logs on deferred probe
by Krzysztof Kozlowski 25 Sep '19

25 Sep '19

There is no point to print deferred probe (and its failures to get resources) as an error. Also there is no need to print regulator errors twice. In case of multiple probe tries this would pollute the dmesg. Signed-off-by: Krzysztof Kozlowski <krzk(a)kernel.org> --- Changes since v1: 1. Remove second error message from calling panfrost_regulator_init(). --- drivers/gpu/drm/panfrost/panfrost_device.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c index 46b0b02e4289..287c6ba314d9 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -95,7 +95,9 @@ static int panfrost_regulator_init(struct panfrost_device *pfdev) pfdev->regulator = NULL; if (ret == -ENODEV) return 0; - dev_err(pfdev->dev, "failed to get regulator: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_err(pfdev->dev, "failed to get regulator: %d\n", + ret); return ret; } @@ -133,10 +135,8 @@ int panfrost_device_init(struct panfrost_device *pfdev) } err = panfrost_regulator_init(pfdev); - if (err) { - dev_err(pfdev->dev, "regulator init failed %d\n", err); + if (err) goto err_out0; - } err = panfrost_reset_init(pfdev); if (err) { -- 2.17.1

2 1

[PATCH 1/2] drm/amdgpu: Fix memory leaks at amdgpu_init() error path
by Takashi Iwai 25 Sep '19

25 Sep '19

amdgpu driver checks vgacon_text_force() after some initializations but without cleaning up. This will result in leaks. Move the check of vgacon_text_force() to the beginning of amdgpu_init() for fixing it and also for optimization. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 50afcf65181a..e55792d3cd12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -905,6 +905,11 @@ static int __init amdgpu_init(void) { int r; + if (vgacon_text_force()) { + DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); + return -EINVAL; + } + r = amdgpu_sync_init(); if (r) goto error_sync; @@ -913,10 +918,6 @@ static int __init amdgpu_init(void) if (r) goto error_fence; - if (vgacon_text_force()) { - DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); - return -EINVAL; - } DRM_INFO("amdgpu kernel modesetting enabled.\n"); driver = &kms_driver; pdriver = &amdgpu_kms_pci_driver; -- 2.16.2

10 26

[PATCH 0/5] DRM/MSM: Add support for MSM8956 and Adreno 510
by kholk11＠gmail.com 25 Sep '19

25 Sep '19

From: AngeloGioacchino Del Regno <kholk11(a)gmail.com> This patch series enables support for MSM8956/76 and its Adreno 510 GPU on the current DRM driver. The personal aim is to upstream MSM8956 as much as possible. This code has been tested on two Sony phones featuring the Qualcomm MSM8956 SoC. Angelo G. Del Regno (5): drm/msm/mdp5: Add optional TBU and TBU_RT clocks drm/msm/mdp5: Add configuration for msm8x56 drm/msm/dsi: Add configuration for 28nm PLL on family B drm/msm/dsi: Add configuration for 8x56 drm/msm/adreno: Add support for Adreno 510 GPU .../devicetree/bindings/display/msm/dsi.txt | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 87 +++++++++++++--- drivers/gpu/drm/msm/adreno/a5xx_power.c | 7 ++ drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 99 +++++++++++++++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 10 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 22 +++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ++++ 13 files changed, 258 insertions(+), 12 deletions(-) -- 2.21.0

5 12

[Bug 111808] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout cause process into Disk sleep state
by bugzilla-daemon＠freedesktop.org 25 Sep '19

25 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=111808 Bug ID: 111808 Summary: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout cause process into Disk sleep state Product: DRI Version: DRI git Hardware: ARM OS: Linux (All) Status: NEW Severity: major Priority: not set Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: liansz(a)fzcyjh.com Created attachment 145507 --> https://bugs.freedesktop.org/attachment.cgi?id=145507&action=edit timeoutlog We ran into some gfx timeout problems. Currently, we use the kernel of 4.19.36. We merged some patches regarding GPU from the community. There are multiple GPUs on each server, and each GPU is running some rendering programs. Now, there are 2 different cases of failures. The first one is that one graphics card of a server fails, rendering program does not have a D state, and it shows error code 110 tested by /sys/kernel/debug/dri/1/amdgpu_test_ib, then shows pass after a second test. See tmp-618-2.zip for details. The second one is that one graphics card of a server fails, the whole rendering program running on the server fails and has D state. It fails at drm_release. See tmp-619.zip for details. Could you please help us out? -- You are receiving this mail because: You are the assignee for the bug.

1 1

[PATCH] drm/bridge/synopsys: dsi: Use devm_platform_ioremap_resource() in __dw_mipi_dsi_probe()
by Markus Elfring 25 Sep '19

25 Sep '19

From: Markus Elfring <elfring(a)users.sourceforge.net> Date: Sat, 21 Sep 2019 20:04:08 +0200 Simplify this function implementation by using a known wrapper function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring(a)users.sourceforge.net> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 675442bfc1bd..6ada149af9ef 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -981,7 +981,6 @@ __dw_mipi_dsi_probe(struct platform_device *pdev, struct device *dev = &pdev->dev; struct reset_control *apb_rst; struct dw_mipi_dsi *dsi; - struct resource *res; int ret; dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); @@ -997,11 +996,7 @@ __dw_mipi_dsi_probe(struct platform_device *pdev, } if (!plat_data->base) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return ERR_PTR(-ENODEV); - - dsi->base = devm_ioremap_resource(dev, res); + dsi->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dsi->base)) return ERR_PTR(-ENODEV); -- 2.23.0

3 2

[PATCH 0/5] Add support for iMX8MQ Display Controller Subsystem
by Laurentiu Palcu 25 Sep '19

25 Sep '19

Hi, This patchset adds initial DCSS support for iMX8MQ chip. Initial support includes only graphics plane support (no video planes), no HDR10 capabilities, no graphics decompression (only linear, tiled and super-tiled buffers allowed). Support for the rest of the features will be added incrementally, in subsequent patches. The patchset was tested with both HDP driver (not yet upstreamed) and MIPI-DSI (drivers already on the dri-devel ML). Thanks, Laurentiu Laurentiu Palcu (5): clk: imx8mq: Add VIDEO2_PLL clock drm/imx: compile imx directory by default drm/imx: Add initial support for DCSS on iMX8MQ dt-bindings: display: imx: add bindings for DCSS arm64: dts: imx8mq: add DCSS node .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 86 +++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 25 + drivers/clk/imx/clk-imx8mq.c | 4 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/imx/Kconfig | 2 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dcss/Kconfig | 7 + drivers/gpu/drm/imx/dcss/Makefile | 6 + drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 75 ++ drivers/gpu/drm/imx/dcss/dcss-crtc.c | 223 ++++++ drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 447 +++++++++++ drivers/gpu/drm/imx/dcss/dcss-dev.c | 286 +++++++ drivers/gpu/drm/imx/dcss/dcss-dev.h | 195 +++++ drivers/gpu/drm/imx/dcss/dcss-dpr.c | 552 ++++++++++++++ drivers/gpu/drm/imx/dcss/dcss-drv.c | 182 +++++ drivers/gpu/drm/imx/dcss/dcss-dtg.c | 438 +++++++++++ drivers/gpu/drm/imx/dcss/dcss-kms.c | 321 ++++++++ drivers/gpu/drm/imx/dcss/dcss-kms.h | 52 ++ drivers/gpu/drm/imx/dcss/dcss-plane.c | 418 +++++++++++ drivers/gpu/drm/imx/dcss/dcss-scaler.c | 830 +++++++++++++++++++++ drivers/gpu/drm/imx/dcss/dcss-ss.c | 179 +++++ include/dt-bindings/clock/imx8mq-clock.h | 4 +- 22 files changed, 4333 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig create mode 100644 drivers/gpu/drm/imx/dcss/Makefile create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c -- 2.7.4

4 9

[PATCH v1 0/2] Add initial support for slimport anx7625
by Xin Ji 25 Sep '19

25 Sep '19

Hi all, The following series add initial support for the Slimport ANX7625 transmitter, a ultra-low power Full-HD 4K MIPI to DP transmitter designed for portable device. This is the first version upload, any mistakes, please let me know, I will fix it in the next series. Thanks, Xin Xin Ji (2): dt-bindings: drm/bridge: anx7625: MIPI to DP transmitter binding drm/bridge: anx7625: Add anx7625 MIPI to DP bridge driver .../bindings/display/bridge/anx7625.yaml | 84 + drivers/gpu/drm/bridge/Makefile | 2 +- drivers/gpu/drm/bridge/analogix/Kconfig | 6 + drivers/gpu/drm/bridge/analogix/Makefile | 1 + drivers/gpu/drm/bridge/analogix/anx7625.c | 2085 ++++++++++++++++++++ drivers/gpu/drm/bridge/analogix/anx7625.h | 397 ++++ 6 files changed, 2574 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/anx7625.yaml create mode 100644 drivers/gpu/drm/bridge/analogix/anx7625.c create mode 100644 drivers/gpu/drm/bridge/analogix/anx7625.h -- 2.7.4

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dri-devel September 2019