dri-devel September 2019

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[Bug 111747] [CI][DRMTIP] igt@ - incomplete - Jenkins gives up
by bugzilla-daemon＠freedesktop.org 24 Sep '19

24 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=111747 --- Comment #5 from CI Bug Log <cibuglog(a)gmail.com> --- A CI Bug Log filter associated to this bug has been updated: {- TGL: igt@* -incomplete - Abort requested by .* terminating children -} {+ TGL: igt@* -incomplete - Abort requested by .* terminating children +} No new failures caught with the new filter -- You are receiving this mail because: You are the assignee for the bug.

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[Bug 111747] [CI][DRMTIP] igt@ - incomplete - Jenkins gives up
by bugzilla-daemon＠freedesktop.org 24 Sep '19

24 Sep '19

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[PATCH 00/11] drm/nouveau: Enable GP10B by default
by Thierry Reding 24 Sep '19

24 Sep '19

From: Thierry Reding <treding(a)nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate operation and then again in the driver) causes the GPU to go into a bad state on some devices. Conditionally doing the reset in the driver only if it isn't already done by the power domain code fixes this issue. Another issue is that the clock may be running at a rate of 0 Hz. This is unlikely to happen because it internally actually can't run that slow, but explicitly setting the clock rate at probe time does seem to help in some cases. Patch three in this series unifies reading the WPR configuration by getting it from GPU register rather than reaching into the memory controller's register space. This is slightly better because it better separates the two drivers and doesn't require an update everytime the memory controller moves to another register aperture. Patch 4 ensures the L2 cache makes memory requests with the proper stream ID, which is required when the GPU is behind an IOMMU. Patch 5 changes the GP10B device initialization to use the correct copy engine. GP10B is a Pascal generation GPU and the way that engines are described changes how the copy engines are enumerated compared to earlier generations. Patches 6 through 9 allow Nouveau to work on Tegra GPUs if the DMA API is backed by an IOMMU. This is different from current assumptions because mappings for all buffers mapped through the DMA API will need to have the special IOMMU bit set in their page tables. Note that this technically makes it possible to support big pages on Tegra because from the GPU's point of view all memory is now contiguous. However, these patches only make sure that buffers are mapped properly and don't try to enable big pages. Also note that mapping through the IOMMU comes at a slight cost, so this may not always be desirable. However, with Tegra186 and later it's currently not possible (from a DMA API point of view) to map only a subset of buffers through the IOMMU, so any such optimization is deferred. Furthermore, the ARM SMMU driver currently enforces the use of the SMMU by default, so there not much of a choice at the moment. Finally patches 10 and 11 enable the GPU on Jetson TX2 and make it use the SMMU. I can pick up patches 10 and 11 into the Tegra tree once the other patches have been merged into Nouveau. Thierry Alexandre Courbot (1): arm64: tegra: Enable GPU on Jetson TX2 Thierry Reding (10): drm/nouveau: tegra: Avoid pulsing reset twice drm/nouveau: tegra: Set clock rate if not set drm/nouveau: secboot: Read WPR configuration from GPU registers drm/nouveau: gp10b: Add custom L2 cache implementation drm/nouveau: gp10b: Use correct copy engine drm/nouveau: gk20a: Set IOMMU bit for DMA API if appropriate drm/nouveau: gk20a: Implement custom MMU class drm/nouveau: tegra: Skip IOMMU initialization if already attached drm/nouveau: tegra: Fall back to 32-bit DMA mask without IOMMU arm64: tegra: Enable SMMU for GPU on Tegra186 .../boot/dts/nvidia/tegra186-p2771-0000.dts | 4 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + .../gpu/drm/nouveau/nvkm/engine/device/base.c | 4 +- .../drm/nouveau/nvkm/engine/device/tegra.c | 152 +++++++++++------- .../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 35 ++-- .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 ++++++++ .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 + .../gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c | 50 +++++- .../gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h | 44 +++++ .../gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c | 6 +- .../gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 1 + .../drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c | 22 ++- .../drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c | 4 +- .../drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c | 20 ++- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- .../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ++++++---- .../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +- 20 files changed, 394 insertions(+), 113 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h -- 2.23.0

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[PATCH v2 00/12] drm/ast/mgag200: Place cursor BOs at VRAM high-end
by Thomas Zimmermann 24 Sep '19

24 Sep '19

(was: drm/vram: Add VRAM buffers for HW cursors) This patchset cleans up the memory management of HW cursors in ast and mgag200. It further moves the allocated cursor BOs to the of the video RAM to reduce memory fragmentation. The ast and mgag200 drivers support HW cursors of uncommon pixel formats. Both drivers manage cursor memory in dedicated GEM VRAM buffer objects with a double buffering scheme; either by alternating between two GEM BOs, or by alternating between offsets within the same GEM BO. The code is convoluted and can lead to memory fragmentation if the BO is stored the middle of VRAM. This is especially a problem on devices with only a small amount of video memory. With this patchset, the cursor handling in ast and mgag200 is first split up into separate functions for copying cursor images, managing buffer objects, setting scanout addresses, and moving and hiding the cursor. Furthermore, each driver dedicates a few KiB at the high end of each device's video memory to storing the cursor's buffer objects. This reduces memory fragmentation, which may prevent displaying the framebuffer on low-memory devices. The patchset has been tested on ast and mgag200 hardware. v2: * remove VRAM buffers in favor of GEM BOs * manage BO placement with pin flag Thomas Zimmermann (12): drm/vram: Support top-down placement flag drm/ast: Don't call ast_show_cursor() from ast_cursor_move() drm/ast: Move cursor update code to ast_show_cursor() drm/ast: Move cursor offset swapping into ast_show_cursor() drm/ast: Allocate cursor BOs at high end of video memory drm/mgag200: Rename cursor functions to use mgag200_ prefix drm/mgag200: Add init and fini functions for cursor handling drm/mgag200: Add separate move-cursor function drm/mgag200: Move cursor-image update to mgag200_show_cursor() drm/mgag200: Move cursor BO swapping into mgag200_show_cursor() drm/mgag200: Reserve video memory for cursor plane drm/mgag200: Allocate cursor BOs at high end of video memory drivers/gpu/drm/ast/ast_drv.h | 43 +-- drivers/gpu/drm/ast/ast_mode.c | 235 +++++++++-------- drivers/gpu/drm/drm_gem_vram_helper.c | 14 +- drivers/gpu/drm/mgag200/mgag200_cursor.c | 316 ++++++++++++++--------- drivers/gpu/drm/mgag200/mgag200_drv.h | 22 +- drivers/gpu/drm/mgag200/mgag200_main.c | 20 +- drivers/gpu/drm/mgag200/mgag200_mode.c | 6 +- drivers/gpu/drm/mgag200/mgag200_ttm.c | 4 + include/drm/drm_gem_vram_helper.h | 1 + 9 files changed, 387 insertions(+), 274 deletions(-) -- 2.23.0

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[Bug 111797] farseena
by bugzilla-daemon＠freedesktop.org 24 Sep '19

24 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=111797 Bug ID: 111797 Summary: farseena Product: DRI Version: unspecified Hardware: All OS: Windows (All) Status: NEW Severity: normal Priority: not set Component: General Assignee: dri-devel(a)lists.freedesktop.org Reporter: farseena1410(a)gmail.com kerala -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH v2 0/2] drm/komeda: Add layer line size support
by Lowry Li (Arm Technology China) 24 Sep '19

24 Sep '19

Hi, >From D32 every component have a line size register to indicate internal fifo size, instead of using the global line_sz. This serie aims at adding the layer line size support and check accordingly on both D71 and D32 or newer. Depends on: https://patchwork.freedesktop.org/series/62377/ https://patchwork.freedesktop.org/series/62181/ Changes since v1: Rebases to drm-misc-next branch. Lowry Li (Arm Technology China) (2): drm/komeda: Add line size support drm/komeda: Adds layer horizontal input size limitation check for D71 .../arm/display/komeda/d71/d71_component.c | 106 ++++++++++++++++-- .../gpu/drm/arm/display/komeda/d71/d71_regs.h | 9 +- .../drm/arm/display/komeda/komeda_pipeline.h | 2 + .../display/komeda/komeda_pipeline_state.c | 17 +++ 4 files changed, 119 insertions(+), 15 deletions(-) -- 2.17.1

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i.MX6Q Etnaviv errors
by Adam Ford 23 Sep '19

23 Sep '19

I tired to run some tests on 5.4 and I was getting errors. I went all the way back to 5.0 and I get errors. 4.19 seems to work just fine. I was curious to know if anyone is seeing errors. I'll bisect tomorrow, but I thought I'd ask before I got too far. # LIBGL_DEBUG=verbose glmark2-es2-drm drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 3, (OK) drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 3, (OK) drmOpenDevice: node name is /dev/dri/card1 drmOpenDevice: open result is 3, (OK) drmOpenDevice: node name is /dev/dri/card2 drmOpenDevice: node name is /dev/dri/card3 drmOpenDevice: node name is /dev/dri/card4 drmOpenDevice: node name is /dev/dri/card5 drmOpenDevice: node name is /dev/dri/card6 drmOpenDevice: node name is /dev/dri/card7 drmOpenDevice: node name is /dev/dri/card8 drmOpenDevice: node name is /dev/dri/card9 drmOpenDevice: node name is /dev/dri/card10 drmOpenDevice: node name is /dev/dri/card11 drmOpenDevice: node name is /dev/dri/card12 drmOpenDevice: node name is /dev/dri/card13 drmOpenDevice: node name is /dev/dri/card14 drmOpenDevice: node name is /dev/dri/card15 drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 3, (OK) drmOpenDevice: node name is /dev/dri/card0 drmOpenDevice: open result is 3, (OK) drmGetBusid returned '' libGL: Can't open configuration file /etc/drirc: No such file or directory. libGL: Can't open configuration file /root/.drirc: No such file or directory. MESA-LOADER: failed to open imx-drm (search paths /usr/lib/dri) failed to load driver: imx-drm libGL: Can't open configuration file /etc/drirc: No such file or directory. libGL: Can't open configuration file /root/.drirc: No such file or directory. libGL: Can't open configuration file /etc/drirc: No such file or directory. libGL: Can't open configuration file /root/.drirc: No such file or directory. Error: eglCreateWindowSurface failed with error: 0x3009 Error: eglCreateWindowSurface failed with error: 0x3009 Error: CanvasGeneric: Invalid EGL state Error: main: Could not initialize canvas

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[Bug 110457] System resumes failed and hits [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout on Acer Squirtle_SR laptop
by bugzilla-daemon＠freedesktop.org 23 Sep '19

23 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=110457 Bug ID: 110457 Summary: System resumes failed and hits [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout on Acer Squirtle_SR laptop Product: DRI Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: major Priority: medium Component: DRM/AMDgpu Assignee: dri-devel(a)lists.freedesktop.org Reporter: jian-hong(a)endlessm.com Created attachment 144006 --> https://bugs.freedesktop.org/attachment.cgi?id=144006&action=edit dmesg with amdgpu.dc=1 drm.debug=7 in boot command We have an Acer Squirtle_SR laptop equipped with AMD A9-9420e RADEON R5, 5 COMPUTE CORES 2C+3G and [AMD/ATI] Topaz XT [Radeon R7 M260/M265 / M340/M360 / M440/M445] [1002:6900]. We test it with Linux kernel 5.1.0-rc5+. The kernel includes the patch [1] mentioned in comment 110360#c9 [2]. System keeps screen black after system resumes from suspending. The error keeps showing on dmesg: [ 177.401716] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout, signaled seq=290, emitted seq=294 [ 177.401848] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process Xorg pid 569 thread Xorg:cs0 pid 571 [ 177.401855] [drm] IP block:gfx_v8_0 is hung! [ 177.401932] [drm] GPU recovery disabled. 01:00.0 Display controller [0380]: Advanced Micro Devices, Inc. [AMD/ATI] Topaz XT [Radeon R7 M260/M265 / M340/M360 / M440/M445] [1002:6900] (rev c3) Subsystem: Acer Incorporated [ALI] Topaz XT [Radeon R7 M260/M265 / M340/M360 / M440/M445] [1025:1217] Flags: bus master, fast devsel, latency 0, IRQ 40 Memory at c0000000 (64-bit, prefetchable) [size=256M] Memory at d0000000 (64-bit, prefetchable) [size=2M] I/O ports at 3000 [size=256] Memory at d1400000 (32-bit, non-prefetchable) [size=256K] Expansion ROM at d1440000 [disabled] [size=128K] Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Capabilities: [58] Express Legacy Endpoint, MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150] Advanced Error Reporting Capabilities: [270] #19 Capabilities: [2b0] Address Translation Service (ATS) Capabilities: [2c0] Page Request Interface (PRI) Capabilities: [2d0] Process Address Space ID (PASID) Kernel driver in use: amdgpu Kernel modules: amdgpu [1] https://patchwork.kernel.org/patch/10889269/ [2] https://bugzilla.freedesktop.org/show_bug.cgi?id=110360#c9 -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH 1/2] MAINTAINERS: Update Allwinner DRM drivers entry
by Maxime Ripard 23 Sep '19

23 Sep '19

The DRM drivers are more than about the A10 now, so let's make the entry name a bit more generic. Also, Chen-Yu has been a de-facto maintainer for the DRM driver for a while, is a maintainer of the Allwinner platform for an even longer time, and has drm-misc commit access. Let's make it formal and add him as a maintainer. Signed-off-by: Maxime Ripard <mripard(a)kernel.org> --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b2326dece28e..54e222e1d0d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5352,8 +5352,9 @@ F: include/drm/drm* F: include/uapi/drm/drm* F: include/linux/vga* -DRM DRIVERS FOR ALLWINNER A10 +DRM DRIVERS FOR ALLWINNER SOCS M: Maxime Ripard <mripard(a)kernel.org> +M: Chen-Yu Tsai <wens(a)csie.org> L: dri-devel(a)lists.freedesktop.org S: Supported F: drivers/gpu/drm/sun4i/ -- 2.21.0

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[PATCH 21/36] drm/vc4: use bpp instead of cpp for drm_format_info
by Sandy Huang 23 Sep '19

23 Sep '19

cpp[BytePerPlane] can't describe the 10bit data format correctly, So we use bpp[BitPerPlane] to instead cpp. Signed-off-by: Sandy Huang <hjc(a)rock-chips.com> --- drivers/gpu/drm/vc4/vc4_plane.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index 5e5f908..ad2b0ec 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -531,7 +531,7 @@ static void vc4_plane_calc_load(struct drm_plane_state *state) vc4_state->crtc_h); vc4_state->membus_load += vc4_state->src_w[i] * vc4_state->src_h[i] * vscale_factor * - fb->format->cpp[i]; + fb->format->bpp[i] / 8; vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; } @@ -646,7 +646,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, vc4_state->offsets[i] += vc4_state->src_x / (i ? h_subsample : 1) * - fb->format->cpp[i]; + fb->format->bpp[i] / 8; } break; @@ -654,7 +654,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { u32 tile_size_shift = 12; /* T tiles are 4kb */ /* Whole-tile offsets, mostly for setting the pitch. */ - u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5; + u32 tile_w_shift = fb->format->bpp[0] == 16 ? 6 : 5; u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ u32 tile_w_mask = (1 << tile_w_shift) - 1; /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice @@ -749,7 +749,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, return -EINVAL; } - pix_per_tile = tile_w / fb->format->cpp[0]; + pix_per_tile = tile_w / (fb->format->bpp[0] / 8); tile = vc4_state->src_x / pix_per_tile; x_off = vc4_state->src_x % pix_per_tile; @@ -763,7 +763,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, tile_w; vc4_state->offsets[i] += x_off / (i ? h_subsample : 1) * - fb->format->cpp[i]; + fb->format->bpp[i] / 8; } pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); -- 2.7.4

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dri-devel September 2019