dri-devel September 2019

dri-devel@lists.freedesktop.org

315 participants
2278 discussions

Re: [PATCH v2 1/4] x86/mm: Export force_dma_unencrypted
by Thomas Hellström (VMware) 03 Sep '19

03 Sep '19

On 9/3/19 6:22 PM, Christoph Hellwig wrote: > On Tue, Sep 03, 2019 at 04:32:45PM +0200, Thomas Hellström (VMware) wrote: >> Is this a layer violation concern, that is, would you be ok with a similar >> helper for TTM, or is it that you want to force the graphics drivers into >> adhering strictly to the DMA api, even when it from an engineering >> perspective makes no sense? > >From looking at DRM I strongly believe that making DRM use the DMA > mapping properly makes a lot of sense from the engineering perspective, > and this series is a good argument for that positions. What I mean with "from an engineering perspective" is that drivers would end up with a non-trivial amount of code supporting purely academic cases: Setups where software rendering would be faster than gpu accelerated, and setups on platforms where the driver would never run anyway because the device would never be supported on that platform... > If DRM was using > the DMA properl we would not need this series to start with, all the > SEV handling is hidden behind the DMA API. While we had occasional > bugs in that support fixing it meant that it covered all drivers > properly using that API. That is not really true. The dma API can't handle faulting of coherent pages which is what this series is really all about supporting also with SEV active. To handle the case where we move graphics buffers or send them to swap space while user-space have them mapped. To do that and still be fully dma-api compliant we would ideally need, for example, an exported dma_pgprot(). (dma_pgprot() by the way is still suffering from one of the bugs that you mention above). Still, I need a way forward and my questions weren't really answered by this. /Thomas

2 1

[PATCH 00/10] drm/msm: async commit support (v2)
by Rob Clark 03 Sep '19

03 Sep '19

From: Rob Clark <robdclark(a)chromium.org> Currently the dpu backend attempts to handle async commits. But it is racey and could result in flushing multiple times in a frame, or modifying hw state (such as scanout address or cursor position) after the previous flush, but before vblank, causing underflows (which manifest as brief black flashes). This patchset removes the previous dpu async commit handling, and reworks the internal kms backend API to decouple flushing. And in the end introduces an hrtimer to flush async updates. The overall approach is: 1) Move flushing various hw state out of encoder/crtc atomic commit (which is anyways an improvement over the current state, where we either flush from crtc or encoder, depending on whether it is a full modeset) 2) Switch to crtc_mask for anything that completes after atomic _commit_tail(), so we do not need to keep the atomic state around. Ie. from drm core's perspective, an async commit completes immediately. This avoids fighting with drm core about the lifecycle of an atomic state object. 3) Track a bitmask of crtcs w/ pending async flush, and setup an hrtimer with expiration 1ms before vblank, to trigger the flush. For async commits, we push the state down to the double buffered hw registers immediately, and only defer writing the flush registers. Current patchset only includes the dpu backend support for async commits.. mdp4 and mdp5 should be relatively trivial (less layers of indirection involved). But I won't have access to any mdp4 hw for a few more weeks, so at least that part I might punt on for now. v2: couple small cosmetic updates, re-work locking to avoid stalls, add some tracepoints Rob Clark (10): drm/msm/dpu: unwind async commit handling drm/msm/dpu: add real wait_for_commit_done() drm/msm/dpu: handle_frame_done() from vblank irq drm/msm: add kms->wait_flush() drm/msm: convert kms->complete_commit() to crtc_mask drm/msm: add kms->flush_commit() drm/msm: split power control from prepare/complete_commit drm/msm: async commit support drm/msm/dpu: async commit support drm/msm: add atomic traces drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 48 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 46 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 8 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 39 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 99 +++++--- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 48 ++-- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 47 ++-- drivers/gpu/drm/msm/msm_atomic.c | 233 +++++++++++++++--- drivers/gpu/drm/msm/msm_atomic_trace.h | 110 +++++++++ drivers/gpu/drm/msm/msm_atomic_tracepoints.c | 3 + drivers/gpu/drm/msm/msm_drv.c | 1 + drivers/gpu/drm/msm/msm_drv.h | 4 + drivers/gpu/drm/msm/msm_gpu_trace.h | 2 +- drivers/gpu/drm/msm/msm_kms.h | 108 +++++++- 16 files changed, 603 insertions(+), 201 deletions(-) create mode 100644 drivers/gpu/drm/msm/msm_atomic_trace.h create mode 100644 drivers/gpu/drm/msm/msm_atomic_tracepoints.c -- 2.21.0

2 16

[Bug 110659] pageflipping seems to cause jittering on mouse input when running Hitman 2 in Wine/DXVK with amdgpu.dc=1
by bugzilla-daemon＠freedesktop.org 03 Sep '19

03 Sep '19

https://bugs.freedesktop.org/show_bug.cgi?id=110659 --- Comment #64 from tempel.julian(a)gmail.com --- I can try that. But I really wonder why there are differences between systems showing the issue or not. -- You are receiving this mail because: You are the assignee for the bug.

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[PATCH 1/3] drm/atomic: Reject FLIP_ASYNC unconditionally
by Daniel Vetter 03 Sep '19

03 Sep '19

It's never been wired up. Only userspace that tried to use it (and didn't actually check whether anything works, but hey it builds) is the -modesetting atomic implementation. And we just shut that up. If there's anyone else then we need to silently accept this flag no matter what, and find a new one. Because once a flag is tainted, it's lost. Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Michel Dänzer <michel(a)daenzer.net> Cc: Alex Deucher <alexdeucher(a)gmail.com> Cc: Adam Jackson <ajax(a)redhat.com> Cc: Sean Paul <sean(a)poorly.run> Cc: David Airlie <airlied(a)linux.ie> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> --- drivers/gpu/drm/drm_atomic_uapi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 5a5b42db6f2a..7a26bfb5329c 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -1305,8 +1305,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, if (arg->reserved) return -EINVAL; - if ((arg->flags & DRM_MODE_PAGE_FLIP_ASYNC) && - !dev->mode_config.async_page_flip) + if (arg->flags & DRM_MODE_PAGE_FLIP_ASYNC) return -EINVAL; /* can't test and expect an event at the same time. */ -- 2.23.0

1 2

[PATCH v2 1/2] dt-bindings: Add binding for IT6505.
by allen 03 Sep '19

03 Sep '19

From: Allen Chen <allen.chen(a)ite.com.tw> Add a DT binding documentation for IT6505. Signed-off-by: Allen Chen <allen.chen(a)ite.com.tw> --- Comments in v1 would be addressed later in v3. --- .../bindings/display/bridge/ite,it6505.txt | 30 ++++++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it6505.txt diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6505.txt b/Documentation/devicetree/bindings/display/bridge/ite,it6505.txt new file mode 100644 index 0000000..c3506ac --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6505.txt @@ -0,0 +1,30 @@ +iTE it6505 DP bridge bindings + +Required properties: + - compatible: "ite,it6505" + - reg: i2c address of the bridge + - ovdd-supply: I/O voltage + - pwr18-supply: Core voltage + - interrupts: interrupt specifier of INT pin + - reset-gpios: gpio specifier of RESET pin + +Example: + it6505dptx: it6505dptx@5c { + compatible = "ite,it6505"; + status = "okay"; + interrupt-parent = <&pio>; + interrupts = <152 IRQ_TYPE_EDGE_RISING 152 0>; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&it6505_pins>; + ovdd-supply = <&mt6358_vsim1_reg>; + pwr18-supply = <&it6505_pp18_reg>; + reset-gpios = <&pio 179 1>; + hpd-gpios = <&pio 9 0>; + extcon = <&usbc_extcon>; + port { + it6505_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 2c3fc51..c088646 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -184,6 +184,7 @@ iom Iomega Corporation isee ISEE 2007 S.L. isil Intersil issi Integrated Silicon Solutions Inc. +ite iTE Tech. Inc. itead ITEAD Intelligent Systems Co.Ltd iwave iWave Systems Technologies Pvt. Ltd. jdi Japan Display Inc. -- 1.9.1

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[PATCH v4] drm/mcde: Fix DSI transfers
by Linus Walleij 03 Sep '19

03 Sep '19

There were bugs in the DSI transfer (read and write) function as it was only tested with displays ever needing a single byte to be written. Fixed it up and tested so we can now write messages of up to 16 bytes and read up to 4 bytes from the display. Tested with a Sony ACX424AKP display: this display now self- identifies and can control backlight in command mode. Reported-by: kbuild test robot <lkp(a)intel.com> Fixes: 5fc537bfd000 ("drm/mcde: Add new driver for ST-Ericsson MCDE") Reviewed-by: Stephan Gerhold <stephan(a)gerhold.net> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v3->v4: - Fix further message bugs caused when fixing bugs in messages. - Considering not coding while I have fever ... nah it's too much fun. ChangeLog v2->v3: - Fix an error message to indicate reading error rather than writing error. - Use the local variable for underflow print. - Collected Stephan's reviewed-by. ChangeLog v1->v2: - Fix a print modifier for dev_err() found by the build robot. --- drivers/gpu/drm/mcde/mcde_dsi.c | 70 ++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c index 07f7090d08b3..f9c9e32b299c 100644 --- a/drivers/gpu/drm/mcde/mcde_dsi.c +++ b/drivers/gpu/drm/mcde/mcde_dsi.c @@ -178,22 +178,26 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, const u32 loop_delay_us = 10; /* us */ const u8 *tx = msg->tx_buf; u32 loop_counter; - size_t txlen; + size_t txlen = msg->tx_len; + size_t rxlen = msg->rx_len; u32 val; int ret; int i; - txlen = msg->tx_len; - if (txlen > 12) { + if (txlen > 16) { dev_err(d->dev, - "dunno how to write more than 12 bytes yet\n"); + "dunno how to write more than 16 bytes yet\n"); + return -EIO; + } + if (rxlen > 4) { + dev_err(d->dev, + "dunno how to read more than 4 bytes yet\n"); return -EIO; } dev_dbg(d->dev, - "message to channel %d, %zd bytes", - msg->channel, - txlen); + "message to channel %d, write %zd bytes read %zd bytes\n", + msg->channel, txlen, rxlen); /* Command "nature" */ if (MCDE_DSI_HOST_IS_READ(msg->type)) @@ -210,9 +214,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, if (mipi_dsi_packet_format_is_long(msg->type)) val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; - /* Add one to the length for the MIPI DCS command */ - val |= txlen - << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; + val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); @@ -249,17 +251,36 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, writel(1, d->regs + DSI_DIRECT_CMD_SEND); loop_counter = 1000 * 1000 / loop_delay_us; - while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & - DSI_DIRECT_CMD_STS_WRITE_COMPLETED) - && --loop_counter) - usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); - - if (!loop_counter) { - dev_err(d->dev, "DSI write timeout!\n"); - return -ETIME; + if (MCDE_DSI_HOST_IS_READ(msg->type)) { + /* Read command */ + while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & + (DSI_DIRECT_CMD_STS_READ_COMPLETED | + DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)) + && --loop_counter) + usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); + if (!loop_counter) { + dev_err(d->dev, "DSI read timeout!\n"); + return -ETIME; + } + } else { + /* Writing only */ + while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & + DSI_DIRECT_CMD_STS_WRITE_COMPLETED) + && --loop_counter) + usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); + + if (!loop_counter) { + dev_err(d->dev, "DSI write timeout!\n"); + return -ETIME; + } } val = readl(d->regs + DSI_DIRECT_CMD_STS); + if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { + dev_err(d->dev, "read completed with error\n"); + writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT); + return -EIO; + } if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; dev_err(d->dev, "error during transmission: %04x\n", @@ -269,10 +290,7 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, if (!MCDE_DSI_HOST_IS_READ(msg->type)) { /* Return number of bytes written */ - if (mipi_dsi_packet_format_is_long(msg->type)) - ret = 4 + txlen; - else - ret = 4; + ret = txlen; } else { /* OK this is a read command, get the response */ u32 rdsz; @@ -282,7 +300,13 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY); rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK; rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT); - for (i = 0; i < 4 && i < rdsz; i++) + if (rdsz < rxlen) { + dev_err(d->dev, "read error, requested %zd got %d\n", + rxlen, rdsz); + return -EIO; + } + /* FIXME: read more than 4 bytes */ + for (i = 0; i < 4 && i < rxlen; i++) rx[i] = (rddat >> (i * 8)) & 0xff; ret = rdsz; } -- 2.21.0

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[PATCH] drm/virtio: add worker for object release
by Gerd Hoffmann 03 Sep '19

03 Sep '19

Move object release into a separate worker. Releasing objects requires sending commands to the host. Doing that in the dequeue worker will cause deadlocks in case the command queue gets filled up, because the dequeue worker is also the one which will free up slots in the command queue. Reported-by: Chia-I Wu <olvaffe(a)gmail.com> Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- drivers/gpu/drm/virtio/virtgpu_drv.h | 8 ++++++++ drivers/gpu/drm/virtio/virtgpu_gem.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/virtio/virtgpu_kms.c | 6 ++++++ drivers/gpu/drm/virtio/virtgpu_vq.c | 2 +- 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index fb35831ed351..314e02f94d9c 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -78,6 +78,7 @@ struct virtio_gpu_object { struct virtio_gpu_object_array { struct ww_acquire_ctx ticket; + struct list_head next; u32 nents, total; struct drm_gem_object *objs[]; }; @@ -197,6 +198,10 @@ struct virtio_gpu_device { struct work_struct config_changed_work; + struct work_struct obj_free_work; + spinlock_t obj_free_lock; + struct list_head obj_free_list; + struct virtio_gpu_drv_capset *capsets; uint32_t num_capsets; struct list_head cap_cache; @@ -246,6 +251,9 @@ void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs); void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs, struct dma_fence *fence); void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs); +void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object_array *objs); +void virtio_gpu_array_put_free_work(struct work_struct *work); /* virtio vg */ int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev); diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c index b812094ae916..4c1f579edfb3 100644 --- a/drivers/gpu/drm/virtio/virtgpu_gem.c +++ b/drivers/gpu/drm/virtio/virtgpu_gem.c @@ -239,3 +239,30 @@ void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs) drm_gem_object_put_unlocked(objs->objs[i]); virtio_gpu_array_free(objs); } + +void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object_array *objs) +{ + spin_lock(&vgdev->obj_free_lock); + list_add_tail(&objs->next, &vgdev->obj_free_list); + spin_unlock(&vgdev->obj_free_lock); + schedule_work(&vgdev->obj_free_work); +} + +void virtio_gpu_array_put_free_work(struct work_struct *work) +{ + struct virtio_gpu_device *vgdev = + container_of(work, struct virtio_gpu_device, obj_free_work); + struct virtio_gpu_object_array *objs; + + spin_lock(&vgdev->obj_free_lock); + while (!list_empty(&vgdev->obj_free_list)) { + objs = list_first_entry(&vgdev->obj_free_list, + struct virtio_gpu_object_array, next); + list_del(&objs->next); + spin_unlock(&vgdev->obj_free_lock); + virtio_gpu_array_put_free(objs); + spin_lock(&vgdev->obj_free_lock); + } + spin_unlock(&vgdev->obj_free_lock); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c index 231c4e27b3b3..0b3cdb0d83b0 100644 --- a/drivers/gpu/drm/virtio/virtgpu_kms.c +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -147,6 +147,11 @@ int virtio_gpu_init(struct drm_device *dev) INIT_WORK(&vgdev->config_changed_work, virtio_gpu_config_changed_work_func); + INIT_WORK(&vgdev->obj_free_work, + virtio_gpu_array_put_free_work); + INIT_LIST_HEAD(&vgdev->obj_free_list); + spin_lock_init(&vgdev->obj_free_lock); + #ifdef __LITTLE_ENDIAN if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_VIRGL)) vgdev->has_virgl_3d = true; @@ -226,6 +231,7 @@ void virtio_gpu_deinit(struct drm_device *dev) { struct virtio_gpu_device *vgdev = dev->dev_private; + flush_work(&vgdev->obj_free_work); vgdev->vqs_ready = false; flush_work(&vgdev->ctrlq.dequeue_work); flush_work(&vgdev->cursorq.dequeue_work); diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index ecf57df965b0..595fa6ec2d58 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -227,7 +227,7 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct *work) list_for_each_entry_safe(entry, tmp, &reclaim_list, list) { if (entry->objs) - virtio_gpu_array_put_free(entry->objs); + virtio_gpu_array_put_free_delayed(vgdev, entry->objs); list_del(&entry->list); free_vbuf(vgdev, entry); } -- 2.18.1

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[PATCH AUTOSEL 5.2 23/23] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
by Sasha Levin 03 Sep '19

03 Sep '19

From: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> [ Upstream commit cf8f9aa1eda7d916bd23f6b8c226404deb11690c ] The same tests failing on CFL+ platforms are also failing on ICL. Documentation doesn't list the WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but applying it fixes the same tests as CFL. v2: Use only one whitelist entry (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> Tested-by: Anuj Phogat <anuj.phogat(a)gmail.com> Cc: stable(a)vger.kernel.org # 6883eab27481: drm/i915: Support flags in whitlist WAs Cc: stable(a)vger.kernel.org Acked-by: Chris Wilson <chris(a)chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190628120720.21682-4-lionel… (cherry picked from commit 3fe0107e45ab396342497e06b8924cdd485cde3b) Signed-off-by: Jani Nikula <jani.nikula(a)intel.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/i915/intel_workarounds.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index efea5a18fa6db..edd57a5e0495f 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -1107,6 +1107,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* WaEnableStateCacheRedirectToCS:icl */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + + /* + * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl + * + * This covers 4 register which are next to one another : + * - PS_INVOCATION_COUNT + * - PS_INVOCATION_COUNT_UDW + * - PS_DEPTH_COUNT + * - PS_DEPTH_COUNT_UDW + */ + whitelist_reg_ext(w, PS_INVOCATION_COUNT, + RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); break; case VIDEO_DECODE_CLASS: -- 2.20.1

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[PATCH AUTOSEL 5.2 22/23] drm/i915: Add whitelist workarounds for ICL
by Sasha Levin 03 Sep '19

03 Sep '19

From: John Harrison <John.C.Harrison(a)Intel.com> [ Upstream commit 7b3d406310983a89ed7a1ecdd115efbe12b0ded5 ] Updated whitelist table for ICL. v2: Reduce changes to just those required for media driver until the selftest can be updated to support the new features of the other entries. Signed-off-by: John Harrison <John.C.Harrison(a)Intel.com> Signed-off-by: Robert M. Fosha <robert.m.fosha(a)intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: Chris Wilson <chris(a)chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190618010108.27499-4-John.C… Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/i915/intel_workarounds.c | 38 +++++++++++++++++------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index be3688908f0ce..efea5a18fa6db 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -1097,17 +1097,33 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; - if (engine->class != RENDER_CLASS) - return; - - /* WaAllowUMDToModifyHalfSliceChicken7:icl */ - whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); - - /* WaAllowUMDToModifySamplerMode:icl */ - whitelist_reg(w, GEN10_SAMPLER_MODE); - - /* WaEnableStateCacheRedirectToCS:icl */ - whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + switch (engine->class) { + case RENDER_CLASS: + /* WaAllowUMDToModifyHalfSliceChicken7:icl */ + whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); + + /* WaAllowUMDToModifySamplerMode:icl */ + whitelist_reg(w, GEN10_SAMPLER_MODE); + + /* WaEnableStateCacheRedirectToCS:icl */ + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + break; + + case VIDEO_DECODE_CLASS: + /* hucStatusRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucUKernelHdrInfoRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucStatus2RegOffset */ + whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + break; + + default: + break; + } } void intel_engine_init_whitelist(struct intel_engine_cs *engine) -- 2.20.1

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[PATCH AUTOSEL 5.2 21/23] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
by Sasha Levin 03 Sep '19

03 Sep '19

From: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> [ Upstream commit 6ce5bfe936ac31d5c52c4b1328d0bfda5f97e7ca ] CFL:C0+ changed the status of those registers which are now blacklisted by default. This is breaking a number of CTS tests on GL & Vulkan : KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL) dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan) v2: Only use one whitelist entry (Lionel) Bspec: 14091 Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> Cc: stable(a)vger.kernel.org # 6883eab27481: drm/i915: Support flags in whitlist WAs Cc: stable(a)vger.kernel.org Acked-by: Chris Wilson <chris(a)chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190628120720.21682-3-lionel… (cherry picked from commit 2c903da50f5a9522b134e488bd0f92646c46f3c0) Signed-off-by: Jani Nikula <jani.nikula(a)intel.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/i915/intel_workarounds.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 0b80fde927899..be3688908f0ce 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -1061,10 +1061,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine) static void cfl_whitelist_build(struct intel_engine_cs *engine) { + struct i915_wa_list *w = &engine->whitelist; + if (engine->class != RENDER_CLASS) return; - gen9_whitelist_build(&engine->whitelist); + gen9_whitelist_build(w); + + /* + * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml + * + * This covers 4 register which are next to one another : + * - PS_INVOCATION_COUNT + * - PS_INVOCATION_COUNT_UDW + * - PS_DEPTH_COUNT + * - PS_DEPTH_COUNT_UDW + */ + whitelist_reg_ext(w, PS_INVOCATION_COUNT, + RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); } static void cnl_whitelist_build(struct intel_engine_cs *engine) -- 2.20.1

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dri-devel September 2019