dri-devel January 2020

dri-devel@lists.freedesktop.org

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841 discussions

[PATCH for 5.5] phy/rockchip: inno-hdmi: round clock rate down to closest 1000 Hz
by Jonas Karlman 06 Jan '20

06 Jan '20

Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") changed what rate clk_round_rate() is called with, an additional 999 Hz added to the requsted mode clock. This has caused a regression on RK3328 and presumably also on RK3228 because the inno-hdmi-phy clock requires an exact match of the requested rate in the pre pll config table. When an exact match is not found the parent clock rate (24MHz) is returned to the clk_round_rate() caller. This cause wrong pixel clock to be used and result in no-signal when configuring a mode on RK3328. Fix this by rounding the rate down to closest 1000 Hz in round_rate func, this allows an exact match to be found in pre pll config table. Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 2b97fb1185a0..9ca20c947283 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -603,6 +603,8 @@ static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, { const struct pre_pll_config *cfg = pre_pll_cfg_table; + rate = (rate / 1000) * 1000; + for (; cfg->pixclock != 0; cfg++) if (cfg->pixclock == rate && !cfg->fracdiv) break; @@ -755,6 +757,8 @@ static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, { const struct pre_pll_config *cfg = pre_pll_cfg_table; + rate = (rate / 1000) * 1000; + for (; cfg->pixclock != 0; cfg++) if (cfg->pixclock == rate) break; -- 2.17.1

2 1

[PATCH v3 0/5] iommu/arm-smmu: Split pagetable support for arm-smmu-v2
by Jordan Crouse 06 Jan '20

06 Jan '20

Another refresh to support split pagetables for Adreno GPUs as part of an incremental process to enable per-context pagetables. In order to support per-context pagetables the GPU needs to enable split tables so that we can store global buffers in the TTBR1 space leaving the GPU free to program the TTBR0 register with the address of a context specific pagetable. This patchset adds split pagetable support if requested by the domain owner via the DOMAIN_ATTR_SPLIT_TABLES attribute. If the attribute is non zero at attach time, the implementation will set up the TTBR0 and TTBR1 spaces with identical configurations and program the domain pagetable into the TTBR1 register. The TTBR0 register will be unused. The driver can determine if split pagetables were programmed by querying DOMAIN_ATTR_SPLIT_TABLES after attaching. The domain geometry will also be updated to reflect the virtual address space for the TTBR1 range. These patches are on based on top of linux-next-20191216 with [1], [2], and [3] from Robin on the iommu list. Change log: v3: Remove the implementation specific and make split pagetable support part of the generic configuration [1] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039718.html [2] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039719.html [3] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039720.html Jordan Crouse (5): iommu: Add DOMAIN_ATTR_SPLIT_TABLES iommu/arm-smmu: Add support for split pagetables drm/msm: Attach the IOMMU device during initialization drm/msm: Refactor address space initialization drm/msm/a6xx: Support split pagetables drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 16 ++++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 51 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 ++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++------- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 18 +++++------ drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 4 --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 18 +++++------ drivers/gpu/drm/msm/msm_drv.h | 8 ++--- drivers/gpu/drm/msm/msm_gem_vma.c | 37 +++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 49 ++---------------------------- drivers/gpu/drm/msm/msm_gpu.h | 4 +-- drivers/gpu/drm/msm/msm_gpummu.c | 6 ---- drivers/gpu/drm/msm/msm_iommu.c | 18 ++++++----- drivers/gpu/drm/msm/msm_mmu.h | 1 - drivers/iommu/arm-smmu.c | 40 +++++++++++++++++++++---- drivers/iommu/arm-smmu.h | 45 ++++++++++++++++++++++++---- include/linux/iommu.h | 1 + 21 files changed, 215 insertions(+), 153 deletions(-) -- 2.7.4

3 7

[PATCH 06/15] drm/rockchip: vop: limit resolution width to 3840
by Jonas Karlman 06 Jan '20

06 Jan '20

Using a destination width that is more then 3840 pixels is not supported in scl_vop_cal_scl_fac(). Work around this limitation by filtering all modes with a width above 3840 pixels. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index d04b3492bdac..f181897cbfad 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1036,6 +1036,15 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } +enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + if (mode->hdisplay > 3840) + return MODE_BAD_HVALUE; + + return MODE_OK; +} + static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -1377,6 +1386,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { + .mode_valid = vop_crtc_mode_valid, .mode_fixup = vop_crtc_mode_fixup, .atomic_check = vop_crtc_atomic_check, .atomic_begin = vop_crtc_atomic_begin, -- 2.17.1

2 2

[PATCH 15/15] phy/rockchip: inno-hdmi: Support more pre-pll configuration
by Jonas Karlman 06 Jan '20

06 Jan '20

From: Algea Cao <algea.cao(a)rock-chips.com> Adding the following freq cfg in 8-bit and 10-bit color depth: { 40000000, 65000000, 71000000, 83500000, 85750000, 88750000, 108000000, 119000000, 162000000 } New freq has been validated by quantumdata 980. For some freq which can't be got by only using integer freq div, frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual freq is different from the target freq, We must try to narrow the gap between them. RK322X only support integer freq div. The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be unlocked. Signed-off-by: Algea Cao <algea.cao(a)rock-chips.com> Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ++++++++++++------- 1 file changed, 49 insertions(+), 25 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 3719309ad0d0..bb8bdf5e3301 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data { const struct phy_config *phy_cfg_table; }; +/* + * If only using integer freq div can't get frequency we want, frac + * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk + * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different + * from the target frequency. Such as the tmds clock 110.9375 Mhz, + * the actual tmds clock we get is 110.93719 Mhz. It is important + * to note that RK322X platforms do not support frac div. + */ static const struct pre_pll_config pre_pll_cfg_table[] = { - { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, - { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, - { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, - { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, - { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, - { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, - { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, - { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, - { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, - { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, - { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, - {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, - {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, - {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, - {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, - {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, - {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, - {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, - {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, - {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, - {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, - {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, - {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, - {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, - {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, + { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, + { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, + { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, + { 40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0}, + { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, + { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, + { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, + { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, + { 65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0}, + { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0}, + { 71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0}, + { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0}, + { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, + { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, + { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, + { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, + { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0}, + { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000}, + { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0}, + { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0}, + { 88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000}, + {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0}, + {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0}, + {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0}, + {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA}, + {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, + {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, + {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, + {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, + {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0}, + {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0}, + {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, + {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, + {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, + {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, + {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, + {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, + {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, + {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, + {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, + {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, { /* sentinel */ } }; -- 2.17.1

2 1

[PATCH 14/15] drm/rockchip: dw-hdmi: remove unused plat_data on rk3228/rk3328
by Jonas Karlman 06 Jan '20

06 Jan '20

mpll_cfg/cur_ctr/phy_config is not used when phy_force_vendor is true, lets remove them. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 66c14df4a680..a813299e97a2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -443,9 +443,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { .mode_valid = dw_hdmi_rk3228_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, .phy_data = &rk3228_chip_data, .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", @@ -480,9 +477,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .mode_valid = dw_hdmi_rk3228_mode_valid, - .mpll_cfg = rockchip_mpll_cfg, - .cur_ctr = rockchip_cur_ctr, - .phy_config = rockchip_phy_config, .phy_data = &rk3328_chip_data, .phy_ops = &rk3328_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", -- 2.17.1

1 0

[PATCH 00/15] Support more HDMI modes on RK3228/RK3328
by Jonas Karlman 06 Jan '20

06 Jan '20

This series make it possible to use more HDMI modes on RK3328, and presumably also on RK3228. It also prepares for a future YUV420 and 10-bit output series. Part of this has been reworked from vendor BSP 4.4 kernel commits. Patch 1-5 fixes issues and shortcomings in the inno hdmi phy driver. Patch 6 filter out any mode having larger width then 3840 pixels, e.g 4096x2304 modes, since limitations in the scaler code trigger an error for a large console framebuffer. Patch 7 prepares for use of high TMDS bit rates used with HDMI2.0 and 10-bit output modes. Patch 8-14 changes rk3228/rk3328 to use mode_valid functions suited for the inno hdmi phy instead of the dw-hdmi phy. This Patch 15 adds support for more pixel clock rates in order to support common DMT modes in addition to CEA modes. Note: I have only been able to build test RK322x related changes as I do not have any RK322x device to test on. All modes, including fractal modes, has been tested with modetest on a RK3328 Rock64 device. modetest -M rockchip -s 39:3840x2160-29.97 Regards, Jonas Algea Cao (1): phy/rockchip: inno-hdmi: Support more pre-pll configuration Huicong Xu (1): phy/rockchip: inno-hdmi: force set_rate on power_on Jonas Karlman (12): phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328 phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rate phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write drm/rockchip: vop: limit resolution width to 3840 drm/rockchip: dw-hdmi: allow high tmds bit rates drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328 clk: rockchip: set parent rate for DCLK_VOP clock on rk3228 arm64: dts: rockchip: increase vop clock rate on rk3328 arm64: dts: rockchip: add vpll clock to hdmi node on rk3328 ARM: dts: rockchip: add vpll clock to hdmi node on rk3228 drm/rockchip: dw-hdmi: limit tmds to 340mhz on rk3228/rk3328 drm/rockchip: dw-hdmi: remove unused plat_data on rk3228/rk3328 Zheng Yang (1): phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate arch/arm/boot/dts/rk322x.dtsi | 4 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- drivers/clk/rockchip/clk-rk3228.c | 2 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 47 ++++++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 10 ++ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 110 ++++++++++++------ 6 files changed, 130 insertions(+), 49 deletions(-) -- 2.17.1

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[PATCH 12/15] ARM: dts: rockchip: add vpll clock to hdmi node on rk3228
by Jonas Karlman 06 Jan '20

06 Jan '20

Add the hdmiphy clock as the vpll in hdmi node. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- arch/arm/boot/dts/rk322x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 340ed6ccb08f..16ad240d5f7f 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -639,8 +639,8 @@ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&cru SCLK_HDMI_PHY>; assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; + clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&hdmi_phy>, <&cru SCLK_HDMI_CEC>; + clock-names = "isfr", "iahb", "vpll", "cec"; pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; resets = <&cru SRST_HDMI_P>; -- 2.17.1

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[PATCH 11/15] arm64: dts: rockchip: add vpll clock to hdmi node on rk3328
by Jonas Karlman 06 Jan '20

06 Jan '20

Add the hdmiphy clock as the vpll in hdmi node. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index ee4b6170a9e6..987c04abb387 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -703,9 +703,11 @@ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI>, <&cru SCLK_HDMI_SFC>, + <&hdmiphy>, <&cru SCLK_RTC32K>; clock-names = "iahb", "isfr", + "vpll", "cec"; phys = <&hdmiphy>; phy-names = "hdmi"; -- 2.17.1

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[PATCH 10/15] arm64: dts: rockchip: increase vop clock rate on rk3328
by Jonas Karlman 06 Jan '20

06 Jan '20

The VOP on RK3328 needs to run at higher rate in order to produce a proper 3840x2160 signal. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 91306ebed4da..ee4b6170a9e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -786,8 +786,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, + <300000000>, <100000000>, + <400000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>, -- 2.17.1

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[PATCH 08/15] drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328
by Jonas Karlman 06 Jan '20

06 Jan '20

RK3228/RK3328 can only support clock rates defined in the pre pll table. Lets validate the mode clock rate against the pre pll config and filter out any mode with a clock rate returning error from clk_round_rate(). Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fae38b323a0c..45fcdce3f27f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -245,6 +245,22 @@ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) { } +static enum drm_mode_status +dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + long rate; + + if (hdmi->vpll_clk) { + rate = clk_round_rate(hdmi->vpll_clk, mode->clock * 1000); + if (rate < 0) + return MODE_CLOCK_RANGE; + } + + return MODE_OK; +} + static bool dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, @@ -306,6 +322,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { + .mode_valid = dw_hdmi_rockchip_encoder_mode_valid, .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable, -- 2.17.1

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