dri-devel January 2020

dri-devel@lists.freedesktop.org

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841 discussions

[PATCH] drm/i915: remove boolean comparisons in conditionals.
by Wambui Karuga 02 Jan '20

02 Jan '20

Remove unnecessary comparisons to true/false in if statements. Issues found by coccinelle. Signed-off-by: Wambui Karuga <wambui.karugax(a)gmail.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9ba794cb9b4f..c065078b3be2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1812,7 +1812,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, u32 temp; temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); - if (state == true) + if (state) temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; else temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index aa515261cb9f..93140c75386a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4958,7 +4958,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) WARN_ON_ONCE(intel_dp->active_mst_links < 0); bret = intel_dp_get_sink_irq_esi(intel_dp, esi); go_again: - if (bret == true) { + if (bret) { /* check link status - esi[10] = 0x200c */ if (intel_dp->active_mst_links > 0 && diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 47f5d87a938a..cff254c52f5e 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -3292,8 +3292,8 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) goto err; - if (intel_sdvo_output_setup(intel_sdvo, - intel_sdvo->caps.output_flags) != true) { + if (!intel_sdvo_output_setup(intel_sdvo, + intel_sdvo->caps.output_flags)) { DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", SDVO_NAME(intel_sdvo)); /* Output_setup can leave behind connectors! */ -- 2.17.1

2 1

[RFC 3/4] drm/sun4i: Reimplement plane z position setting logic
by roman.stratiienko＠globallogic.com 02 Jan '20

02 Jan '20

From: Roman Stratiienko <roman.stratiienko(a)globallogic.com> To set blending channel order register software needs to know state and position of each channel, which impossible at plane commit stage. Move this procedure to atomic_flush stage, where all necessary information is available. Signed-off-by: Roman Stratiienko <roman.stratiienko(a)globallogic.com> --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 47 +++++++++++++++++++++++++- drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 ++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 42 ++++------------------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 39 +++------------------ 4 files changed, 60 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index bb9a665fd053..da84fccf7784 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -307,8 +307,47 @@ static void sun8i_atomic_begin(struct sunxi_engine *engine, static void sun8i_mixer_commit(struct sunxi_engine *engine) { - DRM_DEBUG_DRIVER("Committing changes\n"); + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); + u32 base = sun8i_blender_base(mixer); + int i, j; + int channel_by_zpos[4] = {-1, -1, -1, -1}; + u32 route = 0, pipe_ctl = 0; + + DRM_DEBUG_DRIVER("Update blender routing\n"); + for (i = 0; i < 4; i++) { + int zpos = mixer->channel_zpos[i]; + + if (zpos >= 0 && zpos < 4) + channel_by_zpos[zpos] = i; + } + + j = 0; + for (i = 0; i < 4; i++) { + int ch = channel_by_zpos[i]; + + if (ch >= 0) { + pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(j); + route |= ch << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j); + j++; + } + } + + for (i = 0; i < 4 && j < 4; i++) { + int zpos = mixer->channel_zpos[i]; + if (zpos < 0) { + route |= i << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j); + j++; + } + } + + regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, pipe_ctl); + + regmap_write(mixer->engine.regs, + SUN8I_MIXER_BLEND_ROUTE(base), route); + + DRM_DEBUG_DRIVER("Committing changes\n"); regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); } @@ -422,6 +461,12 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, mixer->engine.ops = &sun8i_engine_ops; mixer->engine.node = dev->of_node; + mixer->channel_zpos[0] = -1; + mixer->channel_zpos[1] = -1; + mixer->channel_zpos[2] = -1; + mixer->channel_zpos[3] = -1; + mixer->channel_zpos[4] = -1; + /* * While this function can fail, we shouldn't do anything * if this happens. Some early DE2 DT entries don't provide diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index 915479cc3077..9c2ff87923d8 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -178,6 +178,9 @@ struct sun8i_mixer { struct clk *bus_clk; struct clk *mod_clk; + + /* -1 means that layer is disabled */ + int channel_zpos[5]; }; static inline struct sun8i_mixer * diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 893076716070..23c2f4b68c89 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -24,12 +24,10 @@ #include "sun8i_ui_scaler.h" static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool enable, unsigned int zpos) { - u32 val, bld_base, ch_base; + u32 val, ch_base; - bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n", @@ -44,32 +42,7 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); - if (!enable || zpos != old_zpos) { - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); - } - - if (enable) { - val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - val, val); - - val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), - val); - } + mixer->channel_zpos[channel] = enable ? zpos : -1; } static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -235,11 +208,9 @@ static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0); } static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, @@ -247,12 +218,11 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, { struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); unsigned int zpos = plane->state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; if (!plane->state->visible) { sun8i_ui_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } @@ -263,7 +233,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, sun8i_ui_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + true, zpos); } static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = { diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 42d445d23773..97cbc98bf781 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -17,8 +17,7 @@ #include "sun8i_vi_scaler.h" static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, - int overlay, bool enable, unsigned int zpos, - unsigned int old_zpos) + int overlay, bool enable, unsigned int zpos) { u32 val, bld_base, ch_base; @@ -37,32 +36,7 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val); - if (!enable || zpos != old_zpos) { - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), - 0); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), - 0); - } - - if (enable) { - val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), - val, val); - - val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_ROUTE(bld_base), - SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), - val); - } + mixer->channel_zpos[channel] = enable ? zpos : -1; } static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -350,11 +324,9 @@ static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; - sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0, - old_zpos); + sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0); } static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, @@ -362,12 +334,11 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, { struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); unsigned int zpos = plane->state->normalized_zpos; - unsigned int old_zpos = old_state->normalized_zpos; struct sun8i_mixer *mixer = layer->mixer; if (!plane->state->visible) { sun8i_vi_layer_enable(mixer, layer->channel, - layer->overlay, false, 0, old_zpos); + layer->overlay, false, 0); return; } @@ -378,7 +349,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, sun8i_vi_layer_update_buffer(mixer, layer->channel, layer->overlay, plane); sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, - true, zpos, old_zpos); + true, zpos); } static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = { -- 2.17.1

4 8

[PATCH v2 0/5] drm/i915/dsi: Control panel and backlight enable GPIOs from VBT
by Hans de Goede 02 Jan '20

02 Jan '20

Hi All, Here is v2 of my patch-series to make the i915 code control the SoC panel- and backlight-enable GPIOs on Bay Trail devices when the VBT indicates that the SoC should be used for backlight control. This fixes the panel not lighting up on various devices when booted with a HDMI monitor connected, in which case the firmware skips initializing the panel as it inits the HDMI instead. This series has been tested on; and fixes this issue on; the following models: Peaq C1010 Point of View MOBII TAB-P800W Point of View MOBII TAB-P1005W Terra Pad 1061 Thundersoft TST178 Yours Y8W81 Linus the main change in v2 is the discussed fixing of the patch to export pinctrl_unregister_mappings. Can you please provide a new immutable branch with the new version (assuming the new version is ok)? Another change on the version is the use of intel_dsi_get_hw_state() to check if the panel is on instead of relying on the current_mode pointer in "[PATCH v2 3/5] drm/i915/dsi: Init panel-enable GPIO to low when the LCD is initially off (v2)". Other then that there are some small style tweaks addressing comments from Andy and Ville. Lee, I know you don't like this, but unfortunately this series introcudes some (other) changes to drivers/mfd/intel_soc_pmic_core.c. The GPIO subsys allows only one mapping-table per consumer, so in hindsight adding the code which adds the mapping for the PMIC panel-enable pin to the PMIC mfd driver was a mistake, as the PMIC code is a provider where as mapping-tables are per consumer. The 4th patch fixes this by moving the mapping-table to the i915 code, so that we can also add mappings for some of the pins on the SoC itself. Since this whole series makes change to the i915 code I plan to merge this mfd change to the drm-intel tree. Regards, Hans

4 10

[Bug 205853] New: amdgpu kernel bug: kernel null pointer dereference
by bugzilla-daemon＠bugzilla.kernel.org 02 Jan '20

02 Jan '20

https://bugzilla.kernel.org/show_bug.cgi?id=205853 Bug ID: 205853 Summary: amdgpu kernel bug: kernel null pointer dereference Product: Drivers Version: 2.5 Kernel Version: 5.4.2 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: janpieter.sollie(a)dommel.be Regression: No Created attachment 286277 --> https://bugzilla.kernel.org/attachment.cgi?id=286277&action=edit dmesg of kernel 5.4.2 possible duplicate of #204181, but as they are talking about X software, and I don't even have an xorg setup (issue happens at boot, device is only present for opencl software), I decided to file a new one: AMDGPU kernel NULL pointer dereference, address: 0000000000000d71 using fiji device lspci, dmesg and .config attached. -- You are receiving this mail because: You are watching the assignee of the bug.

1 5

[PATCH 1/3] drm/i915: use true, false for bool variable in i915_debugfs.c
by Ma Feng 02 Jan '20

02 Jan '20

Fixes coccicheck warning: drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Ma Feng <mafeng.ma(a)huawei.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d28468e..4ead86a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3075,9 +3075,9 @@ static ssize_t i915_displayport_test_active_write(struct file *file, * testing code, only accept an actual value of 1 here */ if (val == 1) - intel_dp->compliance.test_active = 1; + intel_dp->compliance.test_active = true; else - intel_dp->compliance.test_active = 0; + intel_dp->compliance.test_active = false; } } drm_connector_list_iter_end(&conn_iter); -- 2.6.2

2 1

[PATCH v6, 00/14] add drm support for MT8183
by Yongqiang Niu 02 Jan '20

02 Jan '20

This series are based on 5.5-rc1 and provid 14 patch to support mediatek SOC MT8183 Change since v5 - fix reviewed issue in v5 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Yongqiang Niu (14): arm64: dts: add display nodes for mt8183 drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in drm/mediatek: make sout select function format same with select input drm/mediatek: add mmsys private data for ddp path config drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel drm/mediatek: add connection from OVL0 to OVL_2L0 drm/mediatek: add connection from RDMA0 to COLOR0 drm/mediatek: add connection from RDMA1 to DSI0 drm/mediatek: add connection from OVL_2L0 to RDMA0 drm/mediatek: add connection from OVL_2L1 to RDMA1 drm/mediatek: add connection from DITHER0 to DSI0 drm/mediatek: add connection from RDMA0 to DSI0 drm/mediatek: add fifo_size into rdma private data drm/mediatek: add support for mediatek SOC MT8183 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 103 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 291 +++++++++++++++++++++++-------- drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 51 ++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 + 8 files changed, 434 insertions(+), 70 deletions(-) -- 1.8.1.1.dirty

2 26

[Bug 206053] New: Lock screen Black after idle with amdgpu.dc=1
by bugzilla-daemon＠bugzilla.kernel.org 01 Jan '20

01 Jan '20

https://bugzilla.kernel.org/show_bug.cgi?id=206053 Bug ID: 206053 Summary: Lock screen Black after idle with amdgpu.dc=1 Product: Drivers Version: 2.5 Kernel Version: 4.19+ Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: eutychios23(a)gmail.com Regression: No Created attachment 286565 --> https://bugzilla.kernel.org/attachment.cgi?id=286565&action=edit mydmesg I am having a system with rx 550 polaris using amdgpu kernel driver and Mesa 19.3+. when the screen gets idle locked with lightlocker,xscreensaver,xfce4-screensaver the screen cannot get signal back and i get a black screen. The screen lockers work because if i enter my passwd and press enter i can login in the desktop. Additional info: If i lock/blank the screen manually and move them mouse the screen gets the signal back like it should.Issue happens across Debian and Arch distributions.Monitor is connected with an hdmi 2.0 cable. Workaround: Adding amdgpu.dc=0 in grub resolves the issue for all screen lockers in my system, but disables amd display code. -- You are receiving this mail because: You are watching the assignee of the bug.

1 0

[PATCH] drm/panel: declare variable as __be16
by Wambui Karuga 01 Jan '20

01 Jan '20

Declare the temp variable as __be16 to address the following sparse warning: drivers/gpu/drm/panel/panel-lg-lg4573.c:45:20: warning: incorrect type in initializer (different base types) drivers/gpu/drm/panel/panel-lg-lg4573.c:45:20: expected unsigned short [unsigned] [usertype] temp drivers/gpu/drm/panel/panel-lg-lg4573.c:45:20: got restricted __be16 [usertype] <noident> Signed-off-by: Wambui Karuga <wambui.karugax(a)gmail.com> --- drivers/gpu/drm/panel/panel-lg-lg4573.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-lg-lg4573.c b/drivers/gpu/drm/panel/panel-lg-lg4573.c index 20235ff0bbc4..b262b53dbd85 100644 --- a/drivers/gpu/drm/panel/panel-lg-lg4573.c +++ b/drivers/gpu/drm/panel/panel-lg-lg4573.c @@ -42,7 +42,7 @@ static int lg4573_spi_write_u16(struct lg4573 *ctx, u16 data) struct spi_transfer xfer = { .len = 2, }; - u16 temp = cpu_to_be16(data); + __be16 temp = cpu_to_be16(data); struct spi_message msg; dev_dbg(ctx->panel.dev, "writing data: %x\n", data); -- 2.17.1

2 1

[PATCH v4 00/11] drm: Add support for bus-format negotiation
by Boris Brezillon 01 Jan '20

01 Jan '20

This patch series aims at adding support for runtime bus-format negotiation between all elements of the 'encoder -> bridges -> connector/display' section of the pipeline. In order to support that, we need drm bridges to fully take part in the atomic state validation process, which requires adding a drm_bridge_state and a new drm_bridge_funcs.atomic_check() hook. Once those basic building blocks are in place, we can add new hooks to allow bus format negotiation (those are called just before ->atomic_check()). The bus format selection is done at runtime by testing all possible combinations across the whole bridge chain until one is reported to work. No Major changes in this v4. I think I addressed all comments I got from Neil and Laurent (thanks for the detailed reviews BTW). Note that this version only contains core changes. Once those changes are merged I'll send the imx/panel/lvds-codec specific bits. A more detailed changelog is provided in each patch. This patch series is also available here [1]. Thanks, Boris [1]https://github.com/bbrezillon/linux-0day/commits/drm-bridge-busfmt-v4 Boris Brezillon (11): drm/bridge: Rename bridge helpers targeting a bridge chain drm/bridge: Introduce drm_bridge_get_next_bridge() drm: Stop accessing encoder->bridge directly drm/bridge: Make the bridge chain a double-linked list drm/bridge: Add the drm_for_each_bridge_in_chain() helper drm/bridge: Add the drm_bridge_get_prev_bridge() helper drm/bridge: Clarify the atomic enable/disable hooks semantics drm/bridge: Add a drm_bridge_state object drm/bridge: Patch atomic hooks to take a drm_bridge_state drm/bridge: Add an ->atomic_check() hook drm/bridge: Add the necessary bits to support bus format negotiation .../drm/bridge/analogix/analogix_dp_core.c | 41 +- drivers/gpu/drm/drm_atomic.c | 39 + drivers/gpu/drm/drm_atomic_helper.c | 53 +- drivers/gpu/drm/drm_bridge.c | 756 +++++++++++++++--- drivers/gpu/drm/drm_encoder.c | 15 +- drivers/gpu/drm/drm_probe_helper.c | 4 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +- drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 +- drivers/gpu/drm/msm/edp/edp_bridge.c | 10 +- drivers/gpu/drm/omapdrm/omap_drv.c | 4 +- drivers/gpu/drm/omapdrm/omap_encoder.c | 3 +- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 10 +- drivers/gpu/drm/vc4/vc4_dsi.c | 18 +- include/drm/drm_atomic.h | 3 + include/drm/drm_bridge.h | 404 +++++++++- include/drm/drm_encoder.h | 7 +- 16 files changed, 1174 insertions(+), 214 deletions(-) -- 2.23.0

6 41

[pull] amdgpu drm-fixes-5.5
by Alex Deucher 01 Jan '20

01 Jan '20

Hi Dave, Daniel, Happy New Year! Fixes for 5.5. The following changes since commit e31d941c7dd797df37ea94958638a88723325c30: Merge tag 'drm-intel-fixes-2019-12-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2019-12-27 13:13:30 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.5-2020-01-01 for you to fetch changes up to 969e11529221a6a2a787cb3b63ccf9402f8d2e37: drm/amdgpu: correct RLC firmwares loading sequence (2020-01-01 09:26:09 -0500) ---------------------------------------------------------------- amd-drm-fixes-5.5-2020-01-01: amdgpu: - ATPX regression fix - SMU metrics table locking fixes - gfxoff fix for raven - RLC firmware loading stability fix ---------------------------------------------------------------- Alex Deucher (5): Revert "drm/amdgpu: simplify ATPX detection" drm/amdgpu/smu: add metrics table lock drm/amdgpu/smu: add metrics table lock for arcturus (v2) drm/amdgpu/smu: add metrics table lock for navi (v2) drm/amdgpu/smu: add metrics table lock for vega20 (v2) Evan Quan (1): drm/amdgpu: correct RLC firmwares loading sequence changzhu (1): drm/amdgpu: enable gfxoff for raven1 refresh drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 +++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++++----------- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 + drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 +++ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 +++ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 3 +++ 9 files changed, 28 insertions(+), 14 deletions(-)

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dri-devel January 2020