dri-devel October 2020

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[PATCH v3 4/6] drm/dp: Add LTTPR helpers
by Imre Deak 08 Oct '20

08 Oct '20

Add the helpers and register definitions needed to read out the common and per-PHY LTTPR capabilities and perform link training in the LTTPR non-transparent mode. v2: - Add drm_dp_dpcd_read_phy_link_status() and DP_PHY_LTTPR() here instead of adding these to i915. (Ville) v3: - Use memmove() to convert LTTPR to DPRX link status format. (Ville) Cc: dri-devel(a)lists.freedesktop.org Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Imre Deak <imre.deak(a)intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 232 +++++++++++++++++++++++++++++++- include/drm/drm_dp_helper.h | 62 +++++++++ 2 files changed, 290 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 478dd51f738d..79732402336d 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -150,11 +150,8 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) } EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) { - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & - DP_TRAINING_AUX_RD_MASK; - if (rd_interval > 4) DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", rd_interval); @@ -166,8 +163,35 @@ void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) usleep_range(rd_interval, rd_interval * 2); } + +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK); +} EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); +void drm_dp_lttpr_link_train_clock_recovery_delay(void) +{ + usleep_range(100, 200); +} +EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); + +static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) +{ + return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; +} + +void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) +{ + u8 interval = dp_lttpr_phy_cap(phy_cap, + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & + DP_TRAINING_AUX_RD_MASK; + + __drm_dp_link_train_channel_eq_delay(interval); +} +EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); + u8 drm_dp_link_rate_to_bw_code(int link_rate) { /* Spec says link_bw = link_rate / 0.27Gbps */ @@ -363,6 +387,59 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); +/** + * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY + * @aux: DisplayPort AUX channel + * @dp_phy: the DP PHY to get the link status for + * @link_status: buffer to return the status in + * + * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The + * layout of the returned @link_status matches the DPCD register layout of the + * DPRX PHY link status. + * + * Returns 0 if the information was read successfully or a negative error code + * on failure. + */ +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int ret; + + if (dp_phy == DP_PHY_DPRX) { + ret = drm_dp_dpcd_read(aux, + DP_LANE0_1_STATUS, + link_status, + DP_LINK_STATUS_SIZE); + + if (ret < 0) + return ret; + + WARN_ON(ret != DP_LINK_STATUS_SIZE); + + return 0; + } + + ret = drm_dp_dpcd_read(aux, + DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), + link_status, + DP_LINK_STATUS_SIZE - 1); + + if (ret < 0) + return ret; + + WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); + + /* Convert the LTTPR to the sink PHY link status layout */ + memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], + &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], + DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); + link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; + + return 0; +} +EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); + static bool is_edid_digital_input_dp(const struct edid *edid) { return edid && edid->revision >= 4 && @@ -2098,6 +2175,153 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S } EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); +/** + * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities + * @aux: DisplayPort AUX channel + * @caps: buffer to return the capability info in + * + * Read capabilities common to all LTTPRs. + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) +{ + int ret; + + ret = drm_dp_dpcd_read(aux, + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, + caps, DP_LTTPR_COMMON_CAP_SIZE); + if (ret < 0) + return ret; + + WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE); + + return 0; +} +EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); + +/** + * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY + * @aux: DisplayPort AUX channel + * @dp_phy: LTTPR PHY to read the capabilities for + * @caps: buffer to return the capability info in + * + * Read the capabilities for the given LTTPR PHY. + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 caps[DP_LTTPR_PHY_CAP_SIZE]) +{ + int ret; + + ret = drm_dp_dpcd_read(aux, + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), + caps, DP_LTTPR_PHY_CAP_SIZE); + if (ret < 0) + return ret; + + WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE); + + return 0; +} +EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); + +static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) +{ + return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; +} + +/** + * drm_dp_lttpr_count - get the number of detected LTTPRs + * @caps: LTTPR common capabilities + * + * Get the number of detected LTTPRs from the LTTPR common capabilities info. + * + * Returns: + * -ERANGE if more than supported number (8) of LTTPRs are detected + * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value + * otherwise the number of detected LTTPRs + */ +int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) +{ + u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); + + switch (hweight8(count)) { + case 0: + return 0; + case 1: + return 8 - ilog2(count); + case 8: + return -ERANGE; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_dp_lttpr_count); + +/** + * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs + * @caps: LTTPR common capabilities + * + * Returns the maximum link rate supported by all detected LTTPRs. + */ +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) +{ + u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); + + return drm_dp_bw_code_to_link_rate(rate); +} +EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); + +/** + * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs + * @caps: LTTPR common capabilities + * + * Returns the maximum lane count supported by all detected LTTPRs. + */ +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) +{ + u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); + + return max_lanes & DP_MAX_LANE_COUNT_MASK; +} +EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); + +/** + * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support + * @caps: LTTPR PHY capabilities + * + * Returns true if the @caps for an LTTPR TX PHY indicate support for + * voltage swing level 3. + */ +bool +drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) +{ + u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); + + return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; +} +EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); + +/** + * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support + * @caps: LTTPR PHY capabilities + * + * Returns true if the @caps for an LTTPR TX PHY indicate support for + * pre-emphasis level 3. + */ +bool +drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) +{ + u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); + + return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; +} +EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); + /** * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. * @aux: DisplayPort AUX channel diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 159191c1ae75..f55a9d1320ca 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1118,15 +1118,58 @@ struct drm_device; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ + +enum drm_dp_phy { + DP_PHY_DPRX, + + DP_PHY_LTTPR1, + DP_PHY_LTTPR2, + DP_PHY_LTTPR3, + DP_PHY_LTTPR4, + DP_PHY_LTTPR5, + DP_PHY_LTTPR6, + DP_PHY_LTTPR7, + DP_PHY_LTTPR8, + + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, +}; + +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) + +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ +#define DP_LTTPR_BASE(dp_phy) \ + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1)) + +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) + #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) + #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1) + #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) + #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0) +# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1) + #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1) + #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ + #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ @@ -1237,9 +1280,13 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ #define DP_DSC_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 +#define DP_LTTPR_COMMON_CAP_SIZE 8 +#define DP_LTTPR_PHY_CAP_SIZE 3 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_lttpr_link_train_clock_recovery_delay(void); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); u8 drm_dp_link_rate_to_bw_code(int link_rate); int drm_dp_bw_code_to_link_rate(u8 link_bw); @@ -1698,6 +1745,10 @@ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, u8 status[DP_LINK_STATUS_SIZE]); +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 link_status[DP_LINK_STATUS_SIZE]); + bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, u8 real_edid_checksum); @@ -1747,6 +1798,17 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector, const struct drm_dp_desc *desc); int drm_dp_read_sink_count(struct drm_dp_aux *aux); +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); + void drm_dp_remote_aux_init(struct drm_dp_aux *aux); void drm_dp_aux_init(struct drm_dp_aux *aux); int drm_dp_aux_register(struct drm_dp_aux *aux); -- 2.25.1

2 2

[PATCH 00/14] drm/amd/pm: Replace one-element arrays with flexible-array members
by Gustavo A. R. Silva 08 Oct '20

08 Oct '20

Hi all, This series aims to replace one-element arrays with flexible-array members. There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Refactor the code according to the use of flexible-array members, instead of one-element arrays, and use the struct_size() helper to calculate the size for the dynamic memory allocation. Also, save some heap space in the process. More on this on each individual patch. This series also addresses multiple of the following sorts of warnings: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.c:1515:37: warning: array subscript 1 is above array bounds of ‘const struct phm_clock_voltage_dependency_record[1]’ [-Warray-bounds] which, in this case, they are false positives, but nervertheless should be fixed in order to enable -Warray-bounds[3][4]. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-lengt… [3] https://git.kernel.org/linus/44720996e2d79e47d508b0abe99b931a726a3197 [4] https://github.com/KSPP/linux/issues/109 Gustavo A. R. Silva (14): drm/amd/pm: Replace one-element array with flexible-array member drm/amd/pm: Replace one-element array with flexible-array member in struct vi_dpm_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_clock_array drm/amd/pm: Replace one-element array with flexible-array in struct phm_uvd_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_acp_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_phase_shedding_limits_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_vce_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_cac_leakage_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_samu_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_ppt_v1_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_ppt_v1_mm_clock_voltage_dependency_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_ppt_v1_voltage_lookup_table drm/amd/pm: Replace one-element array with flexible-array in struct phm_ppt_v1_pcie_table drm/amd/pm: Replace one-element array with flexible-array in struct ATOM_Vega10_GFXCLK_Dependency_Table drivers/gpu/drm/amd/pm/inc/hwmgr.h | 20 ++--- .../drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h | 8 +- .../powerplay/hwmgr/process_pptables_v1_0.c | 85 +++++++----------- .../amd/pm/powerplay/hwmgr/processpptables.c | 85 +++++++----------- .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 2 +- .../drm/amd/pm/powerplay/hwmgr/smu_helper.c | 5 +- .../amd/pm/powerplay/hwmgr/vega10_pptable.h | 2 +- .../powerplay/hwmgr/vega10_processpptables.c | 88 ++++++------------- 8 files changed, 107 insertions(+), 188 deletions(-) -- 2.27.0

3 18

[PATCH 0/5] ttm make move callback compulsory
by Dave Airlie 08 Oct '20

08 Oct '20

I've just pulled out the few bits for making the move callback compulsory from my previous series. The vmwgfx ones need acks/r-bs, I've booted them in vmplayer and they seem to work fine. Dave.

4 10

[PATCH] dma-buf: use struct_size macro
by Christian König 08 Oct '20

08 Oct '20

Instead of manually calculating the structure size. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 1c8f2581cb09..bb5a42b10c29 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -63,7 +63,7 @@ static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max) { struct dma_resv_list *list; - list = kmalloc(offsetof(typeof(*list), shared[shared_max]), GFP_KERNEL); + list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL); if (!list) return NULL; -- 2.17.1

3 3

[PATCH v5 00/80] drm/vc4: Support BCM2711 Display Pipeline
by Maxime Ripard 08 Oct '20

08 Oct '20

Hi everyone, Here's a (pretty long) series to introduce support in the VC4 DRM driver for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4). The main differences are that there's two HDMI controllers and that there's more pixelvalve now. Those pixelvalve come with a mux in the HVS that still have only 3 FIFOs. Both of those differences are breaking a bunch of expectations in the driver, so we first need a good bunch of cleanup and reworks to introduce support for the new controllers. Similarly, the HDMI controller has all its registers shuffled and split in multiple controllers now, so we need a bunch of changes to support this as well. Only the HDMI support is enabled for now (even though the DPI and DSI outputs have been tested too). Let me know if you have any comments Maxime Cc: bcm-kernel-feedback-list(a)broadcom.com Cc: devicetree(a)vger.kernel.org Cc: Kamal Dasu <kdasu.kdev(a)gmail.com> Cc: Philipp Zabel <p.zabel(a)pengutronix.de> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Stephen Boyd <sboyd(a)kernel.org> Changes from v4: - Rebased on top of next-20200828 - Collected the various tags - Fixed some issues with 4k support and dual output (thanks Hoegeun!) - Fixed typos in commit logs (thanks Dave!) - Split the csc setup hook into its own patch again - Added the CEC clock to the DT binding - Fixed the DT binding example - Reduced the number of calls to of_device_is_compatible in vc4_kms_load - Added back the check for the state commit in our commit hook Changes from v3: - Rebased on top of next-20200708 - Added a name to the HDMI audio codec component - Only disable the BCM2711 HDMI pixelvalves at boot - Fixed an error in the HVS binding - Fix a framebuffer size condition that was inverted - Changed the channel allocation algorithm using Eric's suggestion - Always write the muxing values instead of updating if needed - Improved a bit the hvs_available_channels comment in the structure - Change atomic_complete_commit code to use for_each_new_crtc_in_state - Change the muxing code to take into account disparities between the BCM2711 and previous SoCs. - Only change the clock rate on BCM2711 during a modeset - Fix a crash at atomic_disable - Use clk_set_min_rate for the core clock too - Add a few defines, and simplify the FIFO level stuff - Reordered the patches according to Eric's reviews - Fixed a regression with VID_CTL setting on RPI3 Changes from v2: - Rebased on top of next-20200526 - Split the firmware clock series away - Removed the stuck pixel (with all the subsequent pixels being shifted by one - Fixed the writeback issue too. - Fix the dual output - Fixed the return value of phy_get_cp_current - Enhanced the comment on the reset delay - Increase the max width and height - Made a proper Kconfig option for the DVP clock driver - Fixed the alsa card name collision Changes from v1: - Rebased on top of 5.7-rc1 - Run checkpatch - Added audio support - Fixed some HDMI timeouts - Swiched to clk_hw_register_gate_parent_data - Reorder Kconfig symbols in drivers/i2c/busses - Make the firmware clocks a child of the firmware node - Switch DVP clock driver to clk_hw interface - constify raspberrypi_clk_data in raspberrypi_clock_property - Don't mark firmware clocks as IGNORE_UNUSED - Change from reset_ms to reset_us in reset-simple, and add a bit more comments - Remove generic clk patch to test if a NULL pointer is returned - Removed misleading message in the is_prepared renaming patch commit message - Constify HDMI controller variants - Fix a bug in the allocation size of the clk data array - Added a mention in the DT binding conversion patches about the breakage - Merged a few fixes from kbuild - Fixed a few bisection and CEC build issues - Collected Acked-by and Reviewed-by - Change Dave email address to raspberrypi.com Dave Stevenson (7): drm/vc4: Add support for the BCM2711 HVS5 drm/vc4: plane: Change LBM alignment constraint on LBM drm/vc4: plane: Optimize the LBM allocation size drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default. drm/vc4: hdmi: Add audio-related callbacks Hoegeun Kwon (1): drm/vc4: hdmi: Add pixel BVB clock control Maxime Ripard (72): dt-bindings: display: Add support for the BCM2711 HVS drm/vc4: hvs: Boost the core clock during modeset drm/vc4: plane: Create more planes drm/vc4: crtc: Deal with different number of pixel per clock drm/vc4: crtc: Use a shared interrupt drm/vc4: crtc: Move the cob allocation outside of bind drm/vc4: crtc: Rename HVS channel to output drm/vc4: crtc: Use local chan variable drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable drm/vc4: kms: Convert to for_each_new_crtc_state drm/vc4: crtc: Assign output to channel automatically drm/vc4: crtc: Add FIFO depth to vc4_crtc_data drm/vc4: crtc: Add function to compute FIFO level bits drm/vc4: crtc: Rename HDMI encoder type to HDMI0 drm/vc4: crtc: Add HDMI1 encoder type drm/vc4: crtc: Disable color management for HVS5 drm/vc4: crtc: Turn pixelvalve reset into a function drm/vc4: crtc: Move PV dump to config_pv drm/vc4: crtc: Move HVS init and close to a function drm/vc4: crtc: Move the HVS gamma LUT setup to our init function drm/vc4: hvs: Make sure our channel is reset drm/vc4: crtc: Remove mode_set_nofb drm/vc4: crtc: Remove redundant pixelvalve reset drm/vc4: crtc: Move HVS channel init before the PV initialisation drm/vc4: encoder: Add finer-grained encoder callbacks drm/vc4: crtc: Add a delay after disabling the PixelValve output drm/vc4: crtc: Clear the PixelValve FIFO on disable drm/vc4: crtc: Clear the PixelValve FIFO during configuration drm/vc4: hvs: Make the stop_channel function public drm/vc4: hvs: Introduce a function to get the assigned FIFO drm/vc4: crtc: Move the CRTC disable out drm/vc4: drv: Disable the CRTC at boot time dt-bindings: display: vc4: pv: Add BCM2711 pixel valves drm/vc4: crtc: Add BCM2711 pixelvalves drm/vc4: hdmi: Use debugfs private field drm/vc4: hdmi: Move structure to header drm/vc4: hdmi: rework connectors and encoders drm/vc4: hdmi: Remove DDC argument to connector_init drm/vc4: hdmi: Rename hdmi to vc4_hdmi drm/vc4: hdmi: Move accessors to vc4_hdmi drm/vc4: hdmi: Use local vc4_hdmi directly drm/vc4: hdmi: Add container_of macros for encoders and connectors drm/vc4: hdmi: Pass vc4_hdmi to CEC code drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device drm/vc4: hdmi: Remove vc4_dev hdmi pointer drm/vc4: hdmi: Remove vc4_hdmi_connector drm/vc4: hdmi: Introduce resource init and variant drm/vc4: hdmi: Implement a register layout abstraction drm/vc4: hdmi: Add reset callback drm/vc4: hdmi: Add PHY init and disable function drm/vc4: hdmi: Add PHY RNG enable / disable function drm/vc4: hdmi: Add a CSC setup callback drm/vc4: hdmi: Add a set_timings callback drm/vc4: hdmi: Store the encoder type in the variant structure drm/vc4: hdmi: Deal with multiple debugfs files drm/vc4: hdmi: Move CEC init to its own function drm/vc4: hdmi: Add CEC support flag drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate drm/vc4: hdmi: Use clk_set_min_rate instead drm/vc4: hdmi: Deal with multiple ALSA cards drm/vc4: hdmi: Remove register dumps in enable drm/vc4: hdmi: Always recenter the HDMI FIFO drm/vc4: hdmi: Implement finer-grained hooks drm/vc4: hdmi: Do the VID_CTL configuration at once drm/vc4: hdmi: Switch to blank pixels when disabled drm/vc4: hdmi: Support the BCM2711 HDMI controllers dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings dt-bindings: display: vc4: Document BCM2711 VC5 drm/vc4: drv: Support BCM2711 ARM: dts: bcm2711: Enable the display pipeline Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 117 +++++- Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 +- Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5 +- Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 48 ++- arch/arm/boot/dts/bcm2711.dtsi | 122 ++++- drivers/gpu/drm/vc4/Makefile | 1 +- drivers/gpu/drm/vc4/vc4_crtc.c | 354 +++++++++++---- drivers/gpu/drm/vc4/vc4_drv.c | 5 +- drivers/gpu/drm/vc4/vc4_drv.h | 43 +- drivers/gpu/drm/vc4/vc4_hdmi.c | 1650 +++++++++++++++++++++++++++++++++++++++++++----------------------------- drivers/gpu/drm/vc4/vc4_hdmi.h | 184 ++++++++- drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 520 +++++++++++++++++++++++- drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 442 +++++++++++++++++++- drivers/gpu/drm/vc4/vc4_hvs.c | 269 +++++++----- drivers/gpu/drm/vc4/vc4_kms.c | 229 +++++++++- drivers/gpu/drm/vc4/vc4_plane.c | 222 +++++++--- drivers/gpu/drm/vc4/vc4_regs.h | 177 +++----- drivers/gpu/drm/vc4/vc4_txp.c | 4 +- 19 files changed, 3406 insertions(+), 1005 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h base-commit: 20c0f70ad7bf5aaf2e22ef974867d0708373fe93 -- git-series 0.9.1

7 113

[PATCH v3] drm/panfrost: Fix job timeout handling
by Boris Brezillon 08 Oct '20

08 Oct '20

If more than two jobs end up timeout-ing concurrently, only one of them (the one attached to the scheduler acquiring the lock) is fully handled. The other one remains in a dangling state where it's no longer part of the scheduling queue, but still blocks something in scheduler, leading to repetitive timeouts when new jobs are queued. Let's make sure all bad jobs are properly handled by the thread acquiring the lock. v3: - Add Steven's R-b - Don't take the sched_lock when stopping the schedulers v2: - Fix the subject prefix - Stop the scheduler before returning from panfrost_job_timedout() - Call cancel_delayed_work_sync() after drm_sched_stop() to make sure no timeout handlers are in flight when we reset the GPU (Steven Price) - Make sure we release the reset lock before restarting the schedulers (Steven Price) Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver") Cc: <stable(a)vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon(a)collabora.com> Reviewed-by: Steven Price <steven.price(a)arm.com> --- drivers/gpu/drm/panfrost/panfrost_job.c | 62 +++++++++++++++++++++---- 1 file changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index 30e7b7196dab..d0469e944143 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -25,7 +25,8 @@ struct panfrost_queue_state { struct drm_gpu_scheduler sched; - + bool stopped; + struct mutex lock; u64 fence_context; u64 emit_seqno; }; @@ -369,6 +370,24 @@ void panfrost_job_enable_interrupts(struct panfrost_device *pfdev) job_write(pfdev, JOB_INT_MASK, irq_mask); } +static bool panfrost_scheduler_stop(struct panfrost_queue_state *queue, + struct drm_sched_job *bad) +{ + bool stopped = false; + + mutex_lock(&queue->lock); + if (!queue->stopped) { + drm_sched_stop(&queue->sched, bad); + if (bad) + drm_sched_increase_karma(bad); + queue->stopped = true; + stopped = true; + } + mutex_unlock(&queue->lock); + + return stopped; +} + static void panfrost_job_timedout(struct drm_sched_job *sched_job) { struct panfrost_job *job = to_panfrost_job(sched_job); @@ -392,19 +411,39 @@ static void panfrost_job_timedout(struct drm_sched_job *sched_job) job_read(pfdev, JS_TAIL_LO(js)), sched_job); + /* Scheduler is already stopped, nothing to do. */ + if (!panfrost_scheduler_stop(&pfdev->js->queue[js], sched_job)) + return; + if (!mutex_trylock(&pfdev->reset_lock)) return; for (i = 0; i < NUM_JOB_SLOTS; i++) { struct drm_gpu_scheduler *sched = &pfdev->js->queue[i].sched; - drm_sched_stop(sched, sched_job); - if (js != i) - /* Ensure any timeouts on other slots have finished */ + /* + * If the queue is still active, make sure we wait for any + * pending timeouts. + */ + if (!pfdev->js->queue[i].stopped) cancel_delayed_work_sync(&sched->work_tdr); - } - drm_sched_increase_karma(sched_job); + /* + * If the scheduler was not already stopped, there's a tiny + * chance a timeout has expired just before we stopped it, and + * drm_sched_stop() does not flush pending works. Let's flush + * them now so the timeout handler doesn't get called in the + * middle of a reset. + */ + if (panfrost_scheduler_stop(&pfdev->js->queue[i], NULL)) + cancel_delayed_work_sync(&sched->work_tdr); + + /* + * Now that we cancelled the pending timeouts, we can safely + * reset the stopped state. + */ + pfdev->js->queue[i].stopped = false; + } spin_lock_irqsave(&pfdev->js->job_lock, flags); for (i = 0; i < NUM_JOB_SLOTS; i++) { @@ -421,11 +460,11 @@ static void panfrost_job_timedout(struct drm_sched_job *sched_job) for (i = 0; i < NUM_JOB_SLOTS; i++) drm_sched_resubmit_jobs(&pfdev->js->queue[i].sched); + mutex_unlock(&pfdev->reset_lock); + /* restart scheduler after GPU is usable again */ for (i = 0; i < NUM_JOB_SLOTS; i++) drm_sched_start(&pfdev->js->queue[i].sched, true); - - mutex_unlock(&pfdev->reset_lock); } static const struct drm_sched_backend_ops panfrost_sched_ops = { @@ -558,6 +597,7 @@ int panfrost_job_open(struct panfrost_file_priv *panfrost_priv) int ret, i; for (i = 0; i < NUM_JOB_SLOTS; i++) { + mutex_init(&js->queue[i].lock); sched = &js->queue[i].sched; ret = drm_sched_entity_init(&panfrost_priv->sched_entity[i], DRM_SCHED_PRIORITY_NORMAL, &sched, @@ -570,10 +610,14 @@ int panfrost_job_open(struct panfrost_file_priv *panfrost_priv) void panfrost_job_close(struct panfrost_file_priv *panfrost_priv) { + struct panfrost_device *pfdev = panfrost_priv->pfdev; + struct panfrost_job_slot *js = pfdev->js; int i; - for (i = 0; i < NUM_JOB_SLOTS; i++) + for (i = 0; i < NUM_JOB_SLOTS; i++) { drm_sched_entity_destroy(&panfrost_priv->sched_entity[i]); + mutex_destroy(&js->queue[i].lock); + } } int panfrost_job_is_idle(struct panfrost_device *pfdev) -- 2.26.2

2 1

[PATCH v3 0/7] Support GEM object mappings from I/O memory
by Thomas Zimmermann 08 Oct '20

08 Oct '20

DRM's fbdev console uses regular load and store operations to update framebuffer memory. The bochs driver on sparc64 requires the use of I/O-specific load and store operations. We have a workaround, but need a long-term solution to the problem. This patchset changes GEM's vmap/vunmap interfaces to forward pointers of type struct dma_buf_map and updates the generic fbdev emulation to use them correctly. This enables I/O-memory operations on all framebuffers that require and support them. Patches #1 and #2 prepare VRAM helpers and TTM for the changes in patch #3. Patch #3 updates GEM's vmap/vunmap callback to forward instances of type struct dma_buf_map. While the patch touches many files throughout the DRM modules, the applied changes are mostly trivial interface fixes. Patch #4 updates GEM's internal vmap/vunmap functions to forward struct dma_buf_map. Patches #5 and #6 convert DRM clients and generic fbdev emulation to use struct dma_buf_map. Updating the fbdev framebuffer will select the correct functions, either for system or I/O memory. The patch set is just enough to fix the bochs issue on sparc64 and a correct way. Patch #7 updates the TODO list with ideas for further improvements v3: * recreate the whole patchset on top of struct dma_buf_map v2: * RFC patchset Thomas Zimmermann (7): drm/vram-helper: Remove invariant parameters from internal kmap function drm/ttm: Add ttm_kmap_obj_to_dma_buf_map() for type conversion drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends drm/gem: Update internal GEM vmap/vunmap interfaces to use struct dma_buf_map drm/gem: Store client buffer mappings as struct dma_buf_map drm/fb_helper: Support framebuffers in I/O memory drm/todo: Update entries around struct dma_buf_map Documentation/gpu/todo.rst | 24 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 4 +- drivers/gpu/drm/ast/ast_cursor.c | 29 ++- drivers/gpu/drm/ast/ast_drv.h | 7 +- drivers/gpu/drm/bochs/bochs_kms.c | 1 - drivers/gpu/drm/drm_client.c | 38 ++-- drivers/gpu/drm/drm_fb_helper.c | 238 ++++++++++++++++++-- drivers/gpu/drm/drm_gem.c | 28 ++- drivers/gpu/drm/drm_gem_cma_helper.c | 14 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 48 ++-- drivers/gpu/drm/drm_gem_vram_helper.c | 93 ++++---- drivers/gpu/drm/drm_internal.h | 5 +- drivers/gpu/drm/drm_prime.c | 14 +- drivers/gpu/drm/etnaviv/etnaviv_drv.h | 4 +- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 11 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_gem.h | 4 +- drivers/gpu/drm/lima/lima_gem.c | 6 +- drivers/gpu/drm/lima/lima_sched.c | 11 +- drivers/gpu/drm/mgag200/mgag200_mode.c | 12 +- drivers/gpu/drm/nouveau/nouveau_gem.h | 4 +- drivers/gpu/drm/nouveau/nouveau_prime.c | 9 +- drivers/gpu/drm/panfrost/panfrost_perfcnt.c | 14 +- drivers/gpu/drm/qxl/qxl_display.c | 13 +- drivers/gpu/drm/qxl/qxl_draw.c | 16 +- drivers/gpu/drm/qxl/qxl_drv.h | 8 +- drivers/gpu/drm/qxl/qxl_object.c | 23 +- drivers/gpu/drm/qxl/qxl_object.h | 2 +- drivers/gpu/drm/qxl/qxl_prime.c | 12 +- drivers/gpu/drm/radeon/radeon_gem.c | 4 +- drivers/gpu/drm/radeon/radeon_prime.c | 9 +- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 22 +- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 4 +- drivers/gpu/drm/tiny/cirrus.c | 10 +- drivers/gpu/drm/tiny/gm12u320.c | 10 +- drivers/gpu/drm/udl/udl_modeset.c | 8 +- drivers/gpu/drm/vboxvideo/vbox_mode.c | 11 +- drivers/gpu/drm/vc4/vc4_bo.c | 6 +- drivers/gpu/drm/vc4/vc4_drv.h | 2 +- drivers/gpu/drm/vgem/vgem_drv.c | 16 +- drivers/gpu/drm/xen/xen_drm_front_gem.c | 18 +- drivers/gpu/drm/xen/xen_drm_front_gem.h | 6 +- include/drm/drm_client.h | 7 +- include/drm/drm_gem.h | 5 +- include/drm/drm_gem_cma_helper.h | 4 +- include/drm/drm_gem_shmem_helper.h | 4 +- include/drm/drm_gem_vram_helper.h | 4 +- include/drm/drm_mode_config.h | 12 - include/drm/ttm/ttm_bo_api.h | 24 ++ include/linux/dma-buf-map.h | 92 +++++++- 51 files changed, 685 insertions(+), 305 deletions(-) -- 2.28.0

4 34

[PATCH] drm/fb-helper: Add locking to sysrq handling
by Daniel Vetter 08 Oct '20

08 Oct '20

We didn't take the kernel_fb_helper_lock mutex, which protects that code. While at it, simplify the code - inline the function (originally shared with kgdb I think) - drop the error tracking and all the complications - drop the pointless early out, it served nothing Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: David Airlie <airlied(a)linux.ie> Cc: Daniel Vetter <daniel(a)ffwll.ch> --- drivers/gpu/drm/drm_fb_helper.c | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 8697554ccd41..c2f72bb6afb1 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -281,18 +281,12 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper) EXPORT_SYMBOL(drm_fb_helper_restore_fbdev_mode_unlocked); #ifdef CONFIG_MAGIC_SYSRQ -/* - * restore fbcon display for all kms driver's using this helper, used for sysrq - * and panic handling. - */ -static bool drm_fb_helper_force_kernel_mode(void) +/* emergency restore, don't bother with error reporting */ +static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) { - bool ret, error = false; struct drm_fb_helper *helper; - if (list_empty(&kernel_fb_helper_list)) - return false; - + mutex_lock(&kernel_fb_helper_lock); list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) { struct drm_device *dev = helper->dev; @@ -300,22 +294,12 @@ static bool drm_fb_helper_force_kernel_mode(void) continue; mutex_lock(&helper->lock); - ret = drm_client_modeset_commit_locked(&helper->client); - if (ret) - error = true; + drm_client_modeset_commit_locked(&helper->client); mutex_unlock(&helper->lock); } - return error; + mutex_unlock(&kernel_fb_helper_lock); } -static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) -{ - bool ret; - - ret = drm_fb_helper_force_kernel_mode(); - if (ret == true) - DRM_ERROR("Failed to restore crtc configuration\n"); -} static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn); static void drm_fb_helper_sysrq(int dummy1) -- 2.28.0

2 2

[PATCH] drm/fourcc: Add AXBXGXRX106106106106 format
by Matteo Franchin 08 Oct '20

08 Oct '20

Add ABGR format with 10-bit components packed in 64-bit per pixel. This format can be used to handle VK_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16 on little-endian architectures. Signed-off-by: Matteo Franchin <matteo.franchin(a)arm.com> --- drivers/gpu/drm/drm_fourcc.c | 1 + include/uapi/drm/drm_fourcc.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 722c7ebe4e88..bba03fcb016d 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -202,6 +202,7 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 }, { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 82f327801267..76eedba52b77 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -155,6 +155,13 @@ extern "C" { #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +/* + * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits + * of unused padding per component: + * [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian + */ +#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') + /* packed YCbCr */ #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ -- 2.17.1

4 6

[PATCH 5/6] drm/etnaviv: Fix typo arbitary
by Naoki Hayama 08 Oct '20

08 Oct '20

Fix comment typo. s/arbitary/arbitrary/ Signed-off-by: Naoki Hayama <naoki.hayama(a)lineo.co.jp> --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index c6404b8d067f..5077004f7fbf 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1811,7 +1811,7 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) /* * We treat the device as initially suspended. The runtime PM - * autosuspend delay is rather arbitary: no measurements have + * autosuspend delay is rather arbitrary: no measurements have * yet been performed to determine an appropriate value. */ pm_runtime_use_autosuspend(gpu->dev); -- 2.17.1

1 0

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