dri-devel March 2020

dri-devel@lists.freedesktop.org

328 participants
771 discussions

[PATCH 0/5] Add support for PinePhone LCD panel
by Icenowy Zheng 11 Mar '20

11 Mar '20

This patchset adds support for the LCD panel of PinePhone. The first 3 patches are for the panel itself, and the last 2 patches are for enabling it on PinePhone. PATCH 4 is the fix of a bug in sun6i_mipi_dsi which will gets triggered on XBD599. Icenowy Zheng (5): dt-bindings: vendor-prefixes: Add Xingbangda dt-bindings: panel: add binding for Xingbangda XBD599 panel drm: panel: add Xingbangda XBD599 panel drm/sun4i: sun6i_mipi_dsi: fix horizontal timing calculation arm64: allwinner: dts: a64: add LCD-related device nodes for PinePhone .../display/panel/xingbangda,xbd599.yaml | 50 +++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + .../dts/allwinner/sun50i-a64-pinephone.dtsi | 37 ++ drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-xingbangda-xbd599.c | 367 ++++++++++++++++++ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 10 +- 7 files changed, 471 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/xingbangda,xbd599.yaml create mode 100644 drivers/gpu/drm/panel/panel-xingbangda-xbd599.c -- 2.24.1

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[PATCH v11 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing
by Enric Balletbo i Serra 11 Mar '20

11 Mar '20

Dear all, These patches are intended to solve an old standing issue on some Mediatek devices (mt8173, mt2701 and mt2712 are affected by this issue). Up to now both drivers, clock and drm are probed with the same device tree compatible. But only the first driver gets probed, which in effect breaks graphics on those devices. The MMSYS (Multimedia subsystem) in Mediatek SoCs has some registers to control clock gates (which is used in the clk driver) and some registers to set the routing and enable the differnet blocks of the display and MDP (Media Data Path) subsystem. On this series the clk driver is not a pure clock controller but a system controller that can provide access to the shared registers between the different drivers that need it (mediatek-drm and mediatek-mdp). Hence the MMSYS clk driver was moved to drivers/soc/mediatek and is the entry point (parent) which will trigger the probe of the corresponding mediatek-drm driver. **IMPORTANT** This series only fixes the issue on mt8173 to make it simple and as is the only platform I can test. Similar changes should be applied for mt2701 and mt2712 to have display working. These patches apply on top of linux-next. For reference, here are the links to the old discussions: * v10: https://patchwork.kernel.org/project/linux-mediatek/list/?series=248505 * v9: https://patchwork.kernel.org/project/linux-clk/list/?series=247591 * v8: https://patchwork.kernel.org/project/linux-mediatek/list/?series=244891 * v7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=241217 * v6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 * v5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=44063 * v4: * https://patchwork.kernel.org/patch/10530871/ * https://patchwork.kernel.org/patch/10530883/ * https://patchwork.kernel.org/patch/10530885/ * https://patchwork.kernel.org/patch/10530911/ * https://patchwork.kernel.org/patch/10530913/ * v3: * https://patchwork.kernel.org/patch/10367857/ * https://patchwork.kernel.org/patch/10367861/ * https://patchwork.kernel.org/patch/10367877/ * https://patchwork.kernel.org/patch/10367875/ * https://patchwork.kernel.org/patch/10367885/ * https://patchwork.kernel.org/patch/10367883/ * https://patchwork.kernel.org/patch/10367889/ * https://patchwork.kernel.org/patch/10367907/ * https://patchwork.kernel.org/patch/10367909/ * https://patchwork.kernel.org/patch/10367905/ * v2: No relevant discussion, see v3 * v1: * https://patchwork.kernel.org/patch/10016497/ * https://patchwork.kernel.org/patch/10016499/ * https://patchwork.kernel.org/patch/10016505/ * https://patchwork.kernel.org/patch/10016507/ Best regards, Enric Changes in v11: - Leave the clocks part in drivers/clk (clk-mt8173-mm) - Instantiate the clock driver from the mtk-mmsys driver. - Add default config option to not break anything. - Removed the Reviewed-by CK tag as changed the organization. Changes in v10: - Update the binding documentation for the mmsys system controller. - Renamed to be generic mtk-mmsys - Add driver data support to be able to support diferent SoCs - Select CONFIG_MTK_MMSYS (CK) - Pass device pointer of mmsys device instead of config regs (CK) - Match driver data to get display routing. Changes in v9: - Move mmsys to drivers/soc/mediatek (CK) - Introduced a new patch to move routing control into mmsys driver. - Removed the patch to use regmap as is not needed anymore. - Do not move the display routing from the drm driver (CK) Changes in v8: - Be a builtin_platform_driver like other mediatek mmsys drivers. - New patch introduced in this series. Changes in v7: - Free clk_data->clks as well - Get rid of private data structure Enric Balletbo i Serra (3): dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller soc / drm: mediatek: Move routing control to mmsys device soc / drm: mediatek: Fix mediatek-drm device probing Matthias Brugger (2): drm/mediatek: Omit warning on probe defers clk / soc: mediatek: Move mt8173 MMSYS to platform driver .../bindings/arm/mediatek/mediatek,mmsys.txt | 7 +- drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8173-mm.c | 146 ++++++++ drivers/clk/mediatek/clk-mt8173.c | 104 ------ drivers/gpu/drm/mediatek/Kconfig | 1 + drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 5 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 259 +------------- drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - drivers/gpu/drm/mediatek/mtk_drm_drv.c | 45 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 +- drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 +- drivers/soc/mediatek/Kconfig | 8 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-mmsys.c | 335 ++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ 21 files changed, 590 insertions(+), 411 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8173-mm.c create mode 100644 drivers/soc/mediatek/mtk-mmsys.c create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h -- 2.25.1

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[PATCH V4 0/3] mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers
by Kamal Dasu 11 Mar '20

11 Mar '20

V2 Changes: Refactored drivers/mtd/nand/raw/brcmnand/brcmnand.c based on initial review comments V3 Changes : No change ignore this patch set V4 changes : - Included cover letter to resend the patch set .../devicetree/bindings/mtd/brcm,brcmnand.txt - Added Reviewed-by tag arch/mips/boot/dts/brcm/bcm7425.dtsi - Added Reviwed-by, Acked-by tag drivers/mtd/nand/raw/brcmnand/brcmnand.c - refactored code based on V2 review changes Kamal Dasu (3): dt: bindings: brcmnand: Add support for flash-edu arch: mips: brcm: Add 7425 flash-edu support mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers .../devicetree/bindings/mtd/brcm,brcmnand.txt | 10 +- arch/mips/boot/dts/brcm/bcm7425.dtsi | 4 +- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 293 +++++++++++++++++- 3 files changed, 294 insertions(+), 13 deletions(-) -- 2.17.1

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[PATCH v2] dt-bindings: display: convert rockchip vop bindings to yaml
by Johan Jonker 11 Mar '20

11 Mar '20

Current dts files with 'vop' nodes are manually verified. In order to automate this process rockchip-vop.txt has to be converted to yaml. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changes v2: No new properties --- .../bindings/display/rockchip/rockchip-vop.txt | 74 ------------ .../bindings/display/rockchip/rockchip-vop.yaml | 126 +++++++++++++++++++++ 2 files changed, 126 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt deleted file mode 100644 index 8b3a5f514..000000000 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ /dev/null @@ -1,74 +0,0 @@ -device-tree bindings for rockchip soc display controller (vop) - -VOP (Visual Output Processor) is the Display Controller for the Rockchip -series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3036-vop"; - "rockchip,rk3126-vop"; - "rockchip,px30-vop-lit"; - "rockchip,px30-vop-big"; - "rockchip,rk3066-vop"; - "rockchip,rk3188-vop"; - "rockchip,rk3288-vop"; - "rockchip,rk3368-vop"; - "rockchip,rk3366-vop"; - "rockchip,rk3399-vop-big"; - "rockchip,rk3399-vop-lit"; - "rockchip,rk3228-vop"; - "rockchip,rk3328-vop"; - -- reg: Must contain one entry corresponding to the base address and length - of the register space. Can optionally contain a second entry - corresponding to the CRTC gamma LUT address. - -- interrupts: should contain a list of all VOP IP block interrupts in the - order: VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: Must contain - aclk_vop: for ddr buffer transfer. - hclk_vop: for ahb bus to R/W the phy regs. - dclk_vop: pixel clock. - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - axi - - ahb - - dclk - -- iommus: required a iommu node - -- port: A port node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: -SoC specific DT entry: - vopb: vopb@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - vopb_out_edp: endpoint@0 { - reg = <0>; - remote-endpoint=<&edp_in_vopb>; - }; - vopb_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint=<&hdmi_in_vopb>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml new file mode 100644 index 000000000..cb88849f2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip soc display controller (VOP) + +description: + VOP (Visual Output Processor) is the Display Controller for the Rockchip + series of SoCs which transfers the image data from a video memory + buffer to an external LCD interface. + +maintainers: + - Sandy Huang <hjc(a)rock-chips.com> + - Heiko Stuebner <heiko(a)sntech.de> + +properties: + compatible: + oneOf: + - const: rockchip,px30-vop-big + - const: rockchip,px30-vop-lit + - const: rockchip,rk3036-vop + - const: rockchip,rk3066-vop + - const: rockchip,rk3126-vop + - const: rockchip,rk3188-vop + - const: rockchip,rk3228-vop + - const: rockchip,rk3288-vop + - const: rockchip,rk3328-vop + - const: rockchip,rk3366-vop + - const: rockchip,rk3368-vop + - const: rockchip,rk3399-vop-big + - const: rockchip,rk3399-vop-lit + + reg: + minItems: 1 + items: + - description: + Must contain one entry corresponding to the base address and length + of the register space. + - description: + Can optionally contain a second entry corresponding to + the CRTC gamma LUT address. + + interrupts: + maxItems: 1 + description: + Should contain a list of all VOP IP block interrupts in the + order VSYNC, LCD_SYSTEM. The interrupt specifier + format depends on the interrupt controller used. + + clocks: + items: + - description: Clock for ddr buffer transfer. + - description: Pixel clock. + - description: Clock for the ahb bus to R/W the phy regs. + + clock-names: + items: + - const: aclk_vop + - const: dclk_vop + - const: hclk_vop + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: axi + - const: ahb + - const: dclk + + port: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + vopb: vopb@ff930000 { + compatible = "rockchip,rk3288-vop"; + reg = <0x0 0xff930000 0x0 0x19c>, + <0x0 0xff931000 0x0 0x1000>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP0>, + <&cru DCLK_VOP0>, + <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint=<&edp_in_vopb>; + }; + vopb_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint=<&hdmi_in_vopb>; + }; + }; + }; -- 2.11.0

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P2P for DMA-buf
by Christian König 11 Mar '20

11 Mar '20

This is the third and final part of my series to start supporting P2P with DMA-buf. The implementation is straight forward, apart from a helper to aid constructing scatterlists without having struct pages we only add a new flag indicating that an DMA-buf importer can handle peer2peer. The exporter can then check if P2P is general possible using the pci_p2pdma_distance_many() function and if necessary can also clear the flag. The rest is an example how to implementing the necessary functionality into the amdgpu driver to setup scatterlists pointing to device memory. Please review and comment, Christian.

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[PATCH] drm: sysfs: Use scnprintf() for avoiding potential buffer overflow
by Takashi Iwai 11 Mar '20

11 Mar '20

Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- drivers/gpu/drm/drm_sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index dd2bc85f43cc..9b3180e8c12f 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -230,7 +230,7 @@ static ssize_t modes_show(struct device *device, mutex_lock(&connector->dev->mode_config.mutex); list_for_each_entry(mode, &connector->modes, head) { - written += snprintf(buf + written, PAGE_SIZE - written, "%s\n", + written += scnprintf(buf + written, PAGE_SIZE - written, "%s\n", mode->name); } mutex_unlock(&connector->dev->mode_config.mutex); -- 2.16.4

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[RFC v2 0/8] MIPS: CI20: add HDMI out support
by H. Nikolaus Schaller 11 Mar '20

11 Mar '20

* Converted .txt bindings to .yaml (by Sam Ravnborg <sam(a)ravnborg.org> - big THANKS) RFC V1 2020-02-26 20:13:06: This patch series adds HDMI output to the jz4780/CI20 board. It is based on taking the old 3.18 vendor kernel and trying to achieve the same with modern DTS setup and new/modified drivers. Unfortunately, in this first RFC, only EDID and creation of /dev/fb0 are working. Also, HDMI hot plugging is detected. But there is no HDMI output signal. So some tiny piece seems to be missing to enable/configure the Synposys HDMI controller. We need help from the community to fix this. Original authors of most patches are * Paul Boddie <paul(a)boddie.org.uk> * Zubair Lutfullah Kakakhel <Zubair.Kakakhel(a)imgtec.com> H. Nikolaus Schaller (2): drm: ingenic-drm: add MODULE_DEVICE_TABLE MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 Paul Boddie (4): drm: ingenic: add jz4780 Synopsys HDMI driver. pinctrl: ingenic: add hdmi-ddc pin control group MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller MIPS: DTS: CI20: add HDMI setup Sam Ravnborg (2): dt-bindings: display: add ingenic-jz4780-lcd DT Schema dt-bindings: display: add ingenic-jz4780-hdmi DT Schema .../bindings/display/ingenic-jz4780-hdmi.yaml | 83 ++++++++++++ .../bindings/display/ingenic-jz4780-lcd.yaml | 78 ++++++++++++ arch/mips/boot/dts/ingenic/ci20.dts | 64 ++++++++++ arch/mips/boot/dts/ingenic/jz4780.dtsi | 32 +++++ arch/mips/configs/ci20_defconfig | 3 + drivers/gpu/drm/ingenic/Kconfig | 8 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c | 120 ++++++++++++++++++ drivers/gpu/drm/ingenic/ingenic-drm.c | 2 + drivers/pinctrl/pinctrl-ingenic.c | 7 + 10 files changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml create mode 100644 drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c -- 2.23.0

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[PATCH v4] drm/i915: Init lspcon after HPD in intel_dp_detect()
by Kai-Heng Feng 11 Mar '20

11 Mar '20

On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port becomes useless and never responds to cable hotplugging: [ 3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon [ 3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D Seems like the lspcon chip on the system in question only gets powered after the cable is plugged. So let's call lspcon_init() dynamically to properly initialize the lspcon chip and make HDMI port work. Signed-off-by: Kai-Heng Feng <kai.heng.feng(a)canonical.com> --- v4: - Trust VBT in intel_infoframe_init(). - Init lspcon in intel_dp_detect(). v3: - Make sure it's handled under long HPD case. v2: - Move lspcon_init() inside of intel_dp_hpd_pulse(). drivers/gpu/drm/i915/display/intel_ddi.c | 17 +---------------- drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- 3 files changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 33f1dc3d7c1a..ca717434b406 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4741,7 +4741,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) &dev_priv->vbt.ddi_port_info[port]; struct intel_digital_port *intel_dig_port; struct intel_encoder *encoder; - bool init_hdmi, init_dp, init_lspcon = false; + bool init_hdmi, init_dp; enum phy phy = intel_port_to_phy(dev_priv, port); init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; @@ -4754,7 +4754,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) * is initialized before lspcon. */ init_dp = true; - init_lspcon = true; init_hdmi = false; DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); } @@ -4833,20 +4832,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) goto err; } - if (init_lspcon) { - if (lspcon_init(intel_dig_port)) - /* TODO: handle hdmi info frame part */ - DRM_DEBUG_KMS("LSPCON init success on port %c\n", - port_name(port)); - else - /* - * LSPCON init faied, but DP init was success, so - * lets try to drive as DP++ port. - */ - DRM_ERROR("LSPCON init failed on port %c\n", - port_name(port)); - } - intel_infoframe_init(intel_dig_port); return; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c7424e2a04a3..43117aa86292 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5663,8 +5663,19 @@ intel_dp_detect(struct drm_connector *connector, /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); - else if (intel_digital_port_connected(encoder)) + else if (intel_digital_port_connected(encoder)) { + if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port) && + !dig_port->lspcon.active) { + if (lspcon_init(dig_port)) + DRM_DEBUG_KMS("LSPCON init success on port %c\n", + port_name(dig_port->base.port)); + else + DRM_DEBUG_KMS("LSPCON init failed on port %c\n", + port_name(dig_port->base.port)); + } + status = intel_dp_detect_dpcd(intel_dp); + } else status = connector_status_disconnected; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 93ac0f296852..27a5aa8cefc9 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3100,7 +3100,7 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) intel_dig_port->set_infoframes = g4x_set_infoframes; intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; } else if (HAS_DDI(dev_priv)) { - if (intel_dig_port->lspcon.active) { + if (intel_bios_is_lspcon_present(dev_priv, intel_dig_port->base.port)) { intel_dig_port->write_infoframe = lspcon_write_infoframe; intel_dig_port->read_infoframe = lspcon_read_infoframe; intel_dig_port->set_infoframes = lspcon_set_infoframes; -- 2.17.1

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[PATCH v3 0/2] Add LVDS panel support to HiHope RZ/G2M
by Lad Prabhakar 11 Mar '20

11 Mar '20

Dear All, The HiHope RZ/G2M is advertised as supporting panel idk-1110wr from Advantech, but the panel doesn't come with the board, it has to purchased separatey, therefore this series adds panel support to a new DT. The v2 version somehow missed being merged. v2->v3 * Included Reviewed-by from Rob and Laurent * Switched to dual license * Added myself as the maintainer * Updated copyright year * Rebased the patches v1->v2 * fixed a space according to Geert's feedback. Thanks, Prabhakar Fabrizio Castro (2): dt-bindings: display: Add idk-1110wr binding arm64: dts: renesas: Add HiHope RZ/G2M board with idk-1110wr display .../display/panel/advantech,idk-1110wr.yaml | 69 +++++++++++++++++ arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts | 86 ++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/advantech,idk-1110wr.yaml create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts -- 2.7.4

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[PATCH v8 00/12] Convert PWM period and duty cycle to u64
by Guru Das Srinagesh 11 Mar '20

11 Mar '20

Because period and duty cycle are defined in the PWM framework structs as ints with units of nanoseconds, the maximum time duration that can be set is limited to ~2.147 seconds. Consequently, applications desiring to set greater time periods via the PWM framework are not be able to do so - like, for instance, causing an LED to blink at an interval of 5 seconds. Redefining the period and duty cycle struct members in the core PWM framework structs as u64 values will enable larger time durations to be set and solve this problem. Such a change to the framework mandates that drivers using these struct members (and corresponding helper functions) also be modified correctly in order to prevent compilation errors. This patch series introduces the changes to all the drivers first, followed by the framework change at the very end so that when the latter is applied, all the drivers are in good shape and there are no compilation errors. Changes from v7: - Changed commit messages of all patches to be brief and to the point. - Added explanation of change in cover letter. - Dropped change to pwm-sti.c as upon review it was unnecessary as struct pwm_capture is not being modified in the PWM core. Changes from v6: - Split out the driver changes out into separate patches, one patch per file for ease of reviewing. Changes from v5: - Dropped the conversion of struct pwm_capture to u64 for reasons mentioned in https://www.spinics.net/lists/linux-pwm/msg11541.html Changes from v4: - Split the patch into two: one for changes to the drivers, and the actual switch to u64 for ease of reverting should the need arise. - Re-examined the patch and made the following corrections: * intel_panel.c: DIV64_U64_ROUND_UP -> DIV_ROUND_UP_ULL (as only the numerator would be 64-bit in this case). * pwm-sti.c: do_div -> div_u64 (do_div is optimized only for x86 architectures, and div_u64's comment block suggests to use this as much as possible). Changes from v3: - Rebased to current tip of for-next. Changes from v2: - Fixed %u -> %llu in a dev_dbg in pwm-stm32-lp.c, thanks to kbuild test robot - Added a couple of fixes to pwm-imx-tpm.c and pwm-sifive.c Changes from v1: - Fixed compilation errors seen when compiling for different archs. v1: - Reworked the change pushed upstream earlier [1] so as to not add an extension to an obsolete API. With this change, pwm_ops->apply() can be used to set pwm_state parameters as usual. [1] https://lore.kernel.org/lkml/20190916140048.GB7488@ulmo/ Cc: Lee Jones <lee.jones(a)linaro.org> Cc: Daniel Thompson <daniel.thompson(a)linaro.org> Cc: Jingoo Han <jingoohan1(a)gmail.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie(a)samsung.com> Cc: linux-fbdev(a)vger.kernel.org Cc: Maxime Ripard <mripard(a)kernel.org> Cc: Chen-Yu Tsai <wens(a)csie.org> Cc: Philipp Zabel <p.zabel(a)pengutronix.de> Cc: Fabrice Gasnier <fabrice.gasnier(a)st.com> Cc: Maxime Coquelin <mcoquelin.stm32(a)gmail.com> Cc: Alexandre Torgue <alexandre.torgue(a)st.com> Cc: Palmer Dabbelt <palmer(a)dabbelt.com> Cc: Paul Walmsley <paul.walmsley(a)sifive.com> Cc: linux-riscv(a)lists.infradead.org Cc: Yash Shah <yash.shah(a)sifive.com> Cc: Atish Patra <atish.patra(a)wdc.com> Cc: Shawn Guo <shawnguo(a)kernel.org> Cc: Sascha Hauer <s.hauer(a)pengutronix.de> Cc: Pengutronix Kernel Team <kernel(a)pengutronix.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: NXP Linux Team <linux-imx(a)nxp.com> Cc: Sascha Hauer <s.hauer(a)pengutronix.de> Cc: Pengutronix Kernel Team <kernel(a)pengutronix.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: NXP Linux Team <linux-imx(a)nxp.com> Cc: Alexander Shiyan <shc_work(a)mail.ru> Cc: Mauro Carvalho Chehab <mchehab(a)kernel.org> Cc: Richard Fontana <rfontana(a)redhat.com> Cc: Thomas Gleixner <tglx(a)linutronix.de> Cc: Kate Stewart <kstewart(a)linuxfoundation.org> Cc: Allison Randal <allison(a)lohutok.net> Cc: linux-media(a)vger.kernel.org Cc: Kamil Debski <kamil(a)wypas.org> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie(a)samsung.com> Cc: Jean Delvare <jdelvare(a)suse.com> Cc: Guenter Roeck <linux(a)roeck-us.net> Cc: Liam Girdwood <lgirdwood(a)gmail.com> Cc: Mark Brown <broonie(a)kernel.org> Cc: linux-hwmon(a)vger.kernel.org Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Cc: David Airlie <airlied(a)linux.ie> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: Chris Wilson <chris(a)chris-wilson.co.uk> Cc: "Ville Syrjälä" <ville.syrjala(a)linux.intel.com> Cc: intel-gfx(a)lists.freedesktop.org Cc: dri-devel(a)lists.freedesktop.org Cc: Michael Turquette <mturquette(a)baylibre.com> Cc: Stephen Boyd <sboyd(a)kernel.org> Cc: linux-clk(a)vger.kernel.org Guru Das Srinagesh (12): clk: pwm: Use 64-bit division function drm/i915: Use 64-bit division macro hwmon: pwm-fan: Use 64-bit division macro ir-rx51: Use 64-bit division macro pwm: clps711x: Use 64-bit division macro pwm: pwm-imx-tpm: Use 64-bit division macro pwm: imx27: Use 64-bit division macro and function pwm: sifive: Use 64-bit division macro pwm: stm32-lp: Use %llu format specifier for period pwm: sun4i: Use 64-bit division function backlight: pwm_bl: Use 64-bit division function pwm: core: Convert period and duty cycle to u64 drivers/clk/clk-pwm.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- drivers/hwmon/pwm-fan.c | 2 +- drivers/media/rc/ir-rx51.c | 3 ++- drivers/pwm/core.c | 4 ++-- drivers/pwm/pwm-clps711x.c | 2 +- drivers/pwm/pwm-imx-tpm.c | 2 +- drivers/pwm/pwm-imx27.c | 5 ++--- drivers/pwm/pwm-sifive.c | 2 +- drivers/pwm/pwm-stm32-lp.c | 2 +- drivers/pwm/pwm-sun4i.c | 2 +- drivers/pwm/sysfs.c | 8 ++++---- drivers/video/backlight/pwm_bl.c | 3 ++- include/linux/pwm.h | 12 ++++++------ 14 files changed, 26 insertions(+), 25 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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dri-devel March 2020