dri-devel June 2020

dri-devel@lists.freedesktop.org

315 participants
731 discussions

[PATCH 0/2] drm: rockchip: add NV15 and NV20 support
by Jonas Karlman 14 Jul '20

14 Jul '20

Hi, This series adds support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399. First patch adds a new fourcc 10-bit YUV format with 4:2:2 sub-sampling. Second patch adds support for using the the two new fourcc formats. Both depend on "drm: drm_fourcc: add NV15, Q410, Q401 YUV formats" at [1]. This series can also be found at [2], and can be tested on RK3399 using an upcoming rkvdec series at [3] together with ffmpeg at [4] and kodi-gbm or mpv. [1] https://patchwork.freedesktop.org/series/76326/ [2] https://github.com/Kwiboo/linux-rockchip/commits/next-20200605-fmt_10 [3] https://github.com/Kwiboo/linux-rockchip/commits/next-20200605-rkvdec [4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-hwaccel-4.2.2-rkvdec Regards, Jonas Jonas Karlman (2): drm: drm_fourcc: add NV20 YUV format drm: rockchip: add NV15 and NV20 support drivers/gpu/drm/drm_fourcc.c | 4 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 27 ++++++++++++++++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 31 +++++++++++++++++---- include/uapi/drm/drm_fourcc.h | 1 + 5 files changed, 56 insertions(+), 8 deletions(-) -- 2.17.1

5 13

[PATCH v2 0/8] dt-bindings: media: Conversion of Renesas bindings to YAML
by Laurent Pinchart 14 Jul '20

14 Jul '20

This patch series converts the DT bindings for the Renesas R-Car FCP, FDP1 and VSP1 to YAML. It also updates the bindings based on the properties that have been added to the DT sources over time but never documented. Compared to v1, review comments have been incorporated to fix small typos and simplify a few comments in the bindings, and MAINTAINERS has been updated. Rob, this series has been reviewed by Geert, could you merge it ? Alternatively you can provide acks and I can send a pull request to get it merged through the linux-media tree. Laurent Pinchart (8): dt-bindings: media: renesas,fcp: Convert binding to YAML dt-bindings: media: renesas,fcp: Make power-domains mandatory dt-bindings: media: renesas,fcp: Add resets and iommus properties dt-bindings: media: renesas,fdp1: Convert binding to YAML dt-bindings: media: renesas,fdp1: Make power-domains mandatory dt-bindings: media: renesas,fdp1: Add resets property dt-bindings: media: renesas,vsp1: Convert binding to YAML dt-bindings: media: renesas,vsp1: Add power-domains and resets .../devicetree/bindings/media/renesas,fcp.txt | 34 ------- .../bindings/media/renesas,fcp.yaml | 66 +++++++++++++ .../bindings/media/renesas,fdp1.txt | 37 ------- .../bindings/media/renesas,fdp1.yaml | 69 +++++++++++++ .../bindings/media/renesas,vsp1.txt | 30 ------ .../bindings/media/renesas,vsp1.yaml | 97 +++++++++++++++++++ MAINTAINERS | 6 +- 7 files changed, 235 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/renesas,fcp.txt create mode 100644 Documentation/devicetree/bindings/media/renesas,fcp.yaml delete mode 100644 Documentation/devicetree/bindings/media/renesas,fdp1.txt create mode 100644 Documentation/devicetree/bindings/media/renesas,fdp1.yaml delete mode 100644 Documentation/devicetree/bindings/media/renesas,vsp1.txt create mode 100644 Documentation/devicetree/bindings/media/renesas,vsp1.yaml -- Regards, Laurent Pinchart

4 26

[PATCH v2 01/10] dt-bindings: display: Convert ingenic, lcd.txt to YAML
by Paul Cercueil 14 Jul '20

14 Jul '20

Convert the ingenic,lcd.txt to a new ingenic,lcd.yaml file. In the process, the new ingenic,jz4780-lcd compatible string has been added. Reviewed-by: Rob Herring <robh(a)kernel.org> Acked-by: Sam Ravnborg <sam(a)ravnborg.org> Signed-off-by: Paul Cercueil <paul(a)crapouillou.net> --- Notes: v2: Add info about IPU at port@8 .../bindings/display/ingenic,lcd.txt | 45 ------- .../bindings/display/ingenic,lcd.yaml | 126 ++++++++++++++++++ 2 files changed, 126 insertions(+), 45 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.yaml diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.txt b/Documentation/devicetree/bindings/display/ingenic,lcd.txt deleted file mode 100644 index 01e3261defb6..000000000000 --- a/Documentation/devicetree/bindings/display/ingenic,lcd.txt +++ /dev/null @@ -1,45 +0,0 @@ -Ingenic JZ47xx LCD driver - -Required properties: -- compatible: one of: - * ingenic,jz4740-lcd - * ingenic,jz4725b-lcd - * ingenic,jz4770-lcd -- reg: LCD registers location and length -- clocks: LCD pixclock and device clock specifiers. - The device clock is only required on the JZ4740. -- clock-names: "lcd_pclk" and "lcd" -- interrupts: Specifies the interrupt line the LCD controller is connected to. - -Example: - -panel { - compatible = "sharp,ls020b1dd01d"; - - backlight = <&backlight>; - power-supply = <&vcc>; - - port { - panel_input: endpoint { - remote-endpoint = <&panel_output>; - }; - }; -}; - - -lcd: lcd-controller@13050000 { - compatible = "ingenic,jz4725b-lcd"; - reg = <0x13050000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <31>; - - clocks = <&cgu JZ4725B_CLK_LCD>; - clock-names = "lcd"; - - port { - panel_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.yaml b/Documentation/devicetree/bindings/display/ingenic,lcd.yaml new file mode 100644 index 000000000000..d56db1802fad --- /dev/null +++ b/Documentation/devicetree/bindings/display/ingenic,lcd.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/ingenic,lcd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs LCD controller devicetree bindings + +maintainers: + - Paul Cercueil <paul(a)crapouillou.net> + +properties: + $nodename: + pattern: "^lcd-controller@[0-9a-f]+$" + + compatible: + enum: + - ingenic,jz4740-lcd + - ingenic,jz4725b-lcd + - ingenic,jz4770-lcd + - ingenic,jz4780-lcd + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Pixel clock + - description: Module clock + minItems: 1 + + clock-names: + items: + - const: lcd_pclk + - const: lcd + minItems: 1 + + port: + description: OF graph bindings (specified in bindings/graph.txt). + + ports: + description: OF graph bindings (specified in bindings/graph.txt). + type: object + properties: + port@0: + type: object + description: DPI output, to interface with TFT panels. + + port@8: + type: object + description: Link to the Image Processing Unit (IPU). + (See ingenic,ipu.yaml). + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - ingenic,jz4740-lcd + - ingenic,jz4780-lcd +then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 +else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/jz4740-cgu.h> + lcd-controller@13050000 { + compatible = "ingenic,jz4740-lcd"; + reg = <0x13050000 0x1000>; + + interrupt-parent = <&intc>; + interrupts = <30>; + + clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>; + clock-names = "lcd_pclk", "lcd"; + + port { + endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + + - | + #include <dt-bindings/clock/jz4725b-cgu.h> + lcd-controller@13050000 { + compatible = "ingenic,jz4725b-lcd"; + reg = <0x13050000 0x1000>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + clocks = <&cgu JZ4725B_CLK_LCD>; + clock-names = "lcd_pclk"; + + port { + endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; -- 2.27.0

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[PATCH] drm/vmwgfx: Use correct vmw_legacy_display_unit pointer
by Dan Carpenter 14 Jul '20

14 Jul '20

The "entry" pointer is an offset from the list head and it doesn't point to a valid vmw_legacy_display_unit struct. Presumably the intent was to point to the last entry. Also the "i++" wasn't used so I have removed that as well. Fixes: d7e1958dbe4a ("drm/vmwgfx: Support older hardware.") Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- >From static analysis. Not tested. This bug celebrated its tenth birthday last month. :) drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c index 16dafff5cab1..009f1742bed5 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c @@ -81,7 +81,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv) struct vmw_legacy_display_unit *entry; struct drm_framebuffer *fb = NULL; struct drm_crtc *crtc = NULL; - int i = 0; + int i; /* If there is no display topology the host just assumes * that the guest will set the same layout as the host. @@ -92,12 +92,11 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv) crtc = &entry->base.crtc; w = max(w, crtc->x + crtc->mode.hdisplay); h = max(h, crtc->y + crtc->mode.vdisplay); - i++; } if (crtc == NULL) return 0; - fb = entry->base.crtc.primary->state->fb; + fb = crtc->primary->state->fb; return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0], fb->format->cpp[0] * 8, -- 2.27.0

2 1

[PATCH v7 00/36] DRM: fix struct sg_table nents vs. orig_nents misuse
by Marek Szyprowski 14 Jul '20

14 Jul '20

Dear All, During the Exynos DRM GEM rework and fixing the issues in the. drm_prime_sg_to_page_addr_arrays() function [1] I've noticed that most drivers in DRM framework incorrectly use nents and orig_nents entries of the struct sg_table. In case of the most DMA-mapping implementations exchanging those two entries or using nents for all loops on the scatterlist is harmless, because they both have the same value. There exists however a DMA-mapping implementations, for which such incorrect usage breaks things. The nents returned by dma_map_sg() might be lower than the nents passed as its parameter and this is perfectly fine. DMA framework or IOMMU is allowed to join consecutive chunks while mapping if such operation is supported by the underlying HW (bus, bridge, IOMMU, etc). Example of the case where dma_map_sg() might return 1 'DMA' chunk for the 4 'physical' pages is described here [2] The DMA-mapping framework documentation [3] states that dma_map_sg() returns the numer of the created entries in the DMA address space. However the subsequent calls to dma_sync_sg_for_{device,cpu} and dma_unmap_sg must be called with the original number of entries passed to dma_map_sg. The common pattern in DRM drivers were to assign the dma_map_sg() return value to sg_table->nents and use that value for the subsequent calls to dma_sync_sg_* or dma_unmap_sg functions. Also the code iterated over nents times to access the pages stored in the processed scatterlist, while it should use orig_nents as the numer of the page entries. I've tried to identify all such incorrect usage of sg_table->nents and this is a result of my research. It looks that the incorrect pattern has been copied over the many drivers mainly in the DRM subsystem. Too bad in most cases it even worked correctly if the system used a simple, linear DMA-mapping implementation, for which swapping nents and orig_nents doesn't make any difference. To avoid similar issues in the future, I've introduced a common wrappers for DMA-mapping calls, which operate directly on the sg_table objects. I've also added wrappers for iterating over the scatterlists stored in the sg_table objects and applied them where possible. This, together with some common DRM prime helpers, allowed me to almost get rid of all nents/orig_nents usage in the drivers. I hope that such change makes the code robust, easier to follow and copy/paste safe. The biggest TODO is DRM/i915 driver and I don't feel brave enough to fix it fully. The driver creatively uses sg_table->orig_nents to store the size of the allocate scatterlist and ignores the number of the entries returned by dma_map_sg function. In this patchset I only fixed the sg_table objects exported by dmabuf related functions. I hope that I didn't break anything there. Patches are based on top of Linux next-20200618. The required changes to DMA-mapping framework has been already merged to v5.8-rc1. If possible I would like ask for merging most of the patches via DRM tree. Best regards, Marek Szyprowski References: [1] https://lkml.org/lkml/2020/3/27/555 [2] https://lkml.org/lkml/2020/3/29/65 [3] Documentation/DMA-API-HOWTO.txt [4] https://lore.kernel.org/linux-iommu/20200512121931.GD20393@lst.de/T/#ma18c9… Changelog: v7: - changed DMA page interators to standard DMA SG iterators in drm/prim and videobuf2-dma-contig as suggested by Robin Murphy - fixed build issues v6: https://lore.kernel.org/linux-iommu/20200618153956.29558-1-m.szyprowski@sam… - rebased onto Linux next-20200618, which is based on v5.8-rc1; fixed conflicts v5: https://lore.kernel.org/linux-iommu/20200513132114.6046-1-m.szyprowski@sams… - fixed some minor style issues and typos - fixed lack of the attrs argument in ion, dmabuf, rapidio, fastrpc and vfio patches v4: https://lore.kernel.org/linux-iommu/20200512121931.GD20393@lst.de/T/ - added for_each_sgtable_* wrappers and applied where possible - added drm_prime_get_contiguous_size() and applied where possible - applied drm_prime_sg_to_page_addr_arrays() where possible to remove page extraction from sg_table objects - added documentation for the introduced wrappers - improved patches description a bit v3: https://lore.kernel.org/dri-devel/20200505083926.28503-1-m.szyprowski@samsu… - introduce dma_*_sgtable_* wrappers and use them in all patches v2: https://lore.kernel.org/linux-iommu/c01c9766-9778-fd1f-f36e-2dc7bd376ba4@ar… - dropped most of the changes to drm/i915 - added fixes for rcar-du, xen, media and ion - fixed a few issues pointed by kbuild test robot - added wide cc: list for each patch v1: https://lore.kernel.org/linux-iommu/c01c9766-9778-fd1f-f36e-2dc7bd376ba4@ar… - initial version Patch summary: Marek Szyprowski (36): drm: prime: add common helper to check scatterlist contiguity drm: prime: use sgtable iterators in drm_prime_sg_to_page_addr_arrays() drm: core: fix common struct sg_table related issues drm: amdgpu: fix common struct sg_table related issues drm: armada: fix common struct sg_table related issues drm: etnaviv: fix common struct sg_table related issues drm: exynos: use common helper for a scatterlist contiguity check drm: exynos: fix common struct sg_table related issues drm: i915: fix common struct sg_table related issues drm: lima: fix common struct sg_table related issues drm: mediatek: use common helper for a scatterlist contiguity check drm: mediatek: use common helper for extracting pages array drm: msm: fix common struct sg_table related issues drm: omapdrm: use common helper for extracting pages array drm: omapdrm: fix common struct sg_table related issues drm: panfrost: fix common struct sg_table related issues drm: radeon: fix common struct sg_table related issues drm: rockchip: use common helper for a scatterlist contiguity check drm: rockchip: fix common struct sg_table related issues drm: tegra: fix common struct sg_table related issues drm: v3d: fix common struct sg_table related issues drm: virtio: fix common struct sg_table related issues drm: vmwgfx: fix common struct sg_table related issues drm: xen: fix common struct sg_table related issues xen: gntdev: fix common struct sg_table related issues drm: host1x: fix common struct sg_table related issues drm: rcar-du: fix common struct sg_table related issues dmabuf: fix common struct sg_table related issues staging: ion: remove dead code staging: ion: fix common struct sg_table related issues staging: tegra-vde: fix common struct sg_table related issues misc: fastrpc: fix common struct sg_table related issues rapidio: fix common struct sg_table related issues samples: vfio-mdev/mbochs: fix common struct sg_table related issues media: pci: fix common ALSA DMA-mapping related codes videobuf2: use sgtable-based scatterlist wrappers drivers/dma-buf/heaps/heap-helpers.c | 13 ++- drivers/dma-buf/udmabuf.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 8 +- drivers/gpu/drm/armada/armada_gem.c | 12 +-- drivers/gpu/drm/drm_cache.c | 2 +- drivers/gpu/drm/drm_gem_cma_helper.c | 23 +---- drivers/gpu/drm/drm_gem_shmem_helper.c | 14 ++- drivers/gpu/drm/drm_prime.c | 91 +++++++++++-------- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 12 +-- drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 13 +-- drivers/gpu/drm/exynos/exynos_drm_g2d.c | 10 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 23 +---- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 11 +-- .../gpu/drm/i915/gem/selftests/mock_dmabuf.c | 7 +- drivers/gpu/drm/lima/lima_gem.c | 11 ++- drivers/gpu/drm/lima/lima_vm.c | 5 +- drivers/gpu/drm/mediatek/mtk_drm_gem.c | 37 ++------ drivers/gpu/drm/msm/msm_gem.c | 13 +-- drivers/gpu/drm/msm/msm_gpummu.c | 14 ++- drivers/gpu/drm/msm/msm_iommu.c | 2 +- drivers/gpu/drm/omapdrm/omap_gem.c | 20 ++-- drivers/gpu/drm/panfrost/panfrost_gem.c | 4 +- drivers/gpu/drm/panfrost/panfrost_mmu.c | 7 +- drivers/gpu/drm/radeon/radeon_ttm.c | 11 +-- drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 3 +- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 42 +++------ drivers/gpu/drm/tegra/gem.c | 27 ++---- drivers/gpu/drm/tegra/plane.c | 15 +-- drivers/gpu/drm/v3d/v3d_mmu.c | 13 ++- drivers/gpu/drm/virtio/virtgpu_object.c | 36 +++++--- drivers/gpu/drm/virtio/virtgpu_vq.c | 12 +-- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 17 +--- drivers/gpu/drm/xen/xen_drm_front_gem.c | 2 +- drivers/gpu/host1x/job.c | 22 ++--- .../common/videobuf2/videobuf2-dma-contig.c | 34 +++---- .../media/common/videobuf2/videobuf2-dma-sg.c | 32 +++---- .../common/videobuf2/videobuf2-vmalloc.c | 12 +-- drivers/media/pci/cx23885/cx23885-alsa.c | 2 +- drivers/media/pci/cx25821/cx25821-alsa.c | 2 +- drivers/media/pci/cx88/cx88-alsa.c | 2 +- drivers/media/pci/saa7134/saa7134-alsa.c | 2 +- drivers/media/platform/vsp1/vsp1_drm.c | 8 +- drivers/misc/fastrpc.c | 4 +- drivers/rapidio/devices/rio_mport_cdev.c | 8 +- drivers/staging/android/ion/ion.c | 25 +++-- drivers/staging/android/ion/ion.h | 1 - drivers/staging/android/ion/ion_heap.c | 53 +++-------- drivers/staging/android/ion/ion_system_heap.c | 2 +- drivers/staging/media/tegra-vde/iommu.c | 4 +- drivers/xen/gntdev-dmabuf.c | 13 ++- include/drm/drm_prime.h | 2 + samples/vfio-mdev/mbochs.c | 3 +- 54 files changed, 312 insertions(+), 471 deletions(-) -- 2.17.1

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[v1] drm/msm/dpu: enumerate second cursor pipe for external interface
by Kalyan Thota 13 Jul '20

13 Jul '20

Setup an RGB HW pipe as cursor which can be used on secondary interface. For SC7180 2 HW pipes are enumerated as cursors 1 - primary interface 2 - secondary interface Signed-off-by: Kalyan Thota <kalyan_t(a)codeaurora.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8f2357d..23061fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -117,10 +117,10 @@ .reg_off = 0x2AC, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { - .reg_off = 0x2BC, .bit_off = 8}, + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x2C4, .bit_off = 8}, }, }; @@ -272,10 +272,10 @@ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; /************************************************************* -- 1.9.1

3 3

[PATCH] drm/lima: Expose job_hang_limit module parameter
by Andrey Lebedev 13 Jul '20

13 Jul '20

From: Andrey Lebedev <andrey(a)lebedev.lt> Some pp or gp jobs can be successfully repeated even after they time outs. Introduce lima module parameter to specify number of times a job can hang before being dropped. Signed-off-by: Andrey Lebedev <andrey(a)lebedev.lt> --- Hello, This patch allows to work around a freezing problem as discussed in https://gitlab.freedesktop.org/lima/linux/-/issues/33 drivers/gpu/drm/lima/lima_drv.c | 4 ++++ drivers/gpu/drm/lima/lima_drv.h | 1 + drivers/gpu/drm/lima/lima_sched.c | 5 +++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c index a831565af813..2807eba26c55 100644 --- a/drivers/gpu/drm/lima/lima_drv.c +++ b/drivers/gpu/drm/lima/lima_drv.c @@ -19,6 +19,7 @@ int lima_sched_timeout_ms; uint lima_heap_init_nr_pages = 8; uint lima_max_error_tasks; +int lima_job_hang_limit; MODULE_PARM_DESC(sched_timeout_ms, "task run timeout in ms"); module_param_named(sched_timeout_ms, lima_sched_timeout_ms, int, 0444); @@ -29,6 +30,9 @@ module_param_named(heap_init_nr_pages, lima_heap_init_nr_pages, uint, 0444); MODULE_PARM_DESC(max_error_tasks, "max number of error tasks to save"); module_param_named(max_error_tasks, lima_max_error_tasks, uint, 0644); +MODULE_PARM_DESC(job_hang_limit, "number of times to allow a job to hang before dropping it (default 0)"); +module_param_named(job_hang_limit, lima_job_hang_limit, int, 0444); + static int lima_ioctl_get_param(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_lima_get_param *args = data; diff --git a/drivers/gpu/drm/lima/lima_drv.h b/drivers/gpu/drm/lima/lima_drv.h index fdbd4077c768..39fd98e3b14d 100644 --- a/drivers/gpu/drm/lima/lima_drv.h +++ b/drivers/gpu/drm/lima/lima_drv.h @@ -11,6 +11,7 @@ extern int lima_sched_timeout_ms; extern uint lima_heap_init_nr_pages; extern uint lima_max_error_tasks; +extern int lima_job_hang_limit; struct lima_vm; struct lima_bo; diff --git a/drivers/gpu/drm/lima/lima_sched.c b/drivers/gpu/drm/lima/lima_sched.c index e6cefda00279..1602985dfa04 100644 --- a/drivers/gpu/drm/lima/lima_sched.c +++ b/drivers/gpu/drm/lima/lima_sched.c @@ -503,8 +503,9 @@ int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name) INIT_WORK(&pipe->recover_work, lima_sched_recover_work); - return drm_sched_init(&pipe->base, &lima_sched_ops, 1, 0, - msecs_to_jiffies(timeout), name); + return drm_sched_init(&pipe->base, &lima_sched_ops, 1, + lima_job_hang_limit, msecs_to_jiffies(timeout), + name); } void lima_sched_pipe_fini(struct lima_sched_pipe *pipe) -- 2.25.1

2 7

[PATCH v2] drm/atomic_helper: add a flag for duplicating drm_private_obj state
by Shawn Guo 11 Jul '20

11 Jul '20

From: Shawn Guo <shawn.guo(a)linaro.org> The msm/mdp5 driver uses state of drm_private_obj as its global atomic state, which keeps the assignment of hwpipe to plane. With drm_private_obj missing from duplicate state call in context of atomic suspend/resume helpers, mdp5 suspend works with no problem only for the very first time. Any subsequent suspend will hit the following warning, because hwpipe assignment doesn't get duplicated for suspend state. $ echo mem > /sys/power/state [ 38.111144] PM: suspend entry (deep) [ 38.111185] PM: Syncing filesystems ... done. [ 38.114630] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 38.115912] OOM killer disabled. [ 38.115914] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 38.122170] ------------[ cut here ]------------ [ 38.122212] WARNING: CPU: 0 PID: 1747 at drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c:145 mdp5_pipe_release+0x90/0xc0 [ 38.122215] Modules linked in: [ 38.122222] CPU: 0 PID: 1747 Comm: sh Not tainted 4.19.107-00515-g9d5e4d7a33ed-dirty #323 [ 38.122224] Hardware name: Square, Inc. T2 Devkit (DT) [ 38.122228] pstate: 40000005 (nZcv daif -PAN -UAO) [ 38.122230] pc : mdp5_pipe_release+0x90/0xc0 [ 38.122233] lr : mdp5_pipe_release+0x90/0xc0 [ 38.122235] sp : ffff00000d13b7f0 [ 38.122236] x29: ffff00000d13b7f0 x28: 0000000000000000 [ 38.122240] x27: 0000000000000002 x26: ffff800079adce00 [ 38.122243] x25: ffff800079405200 x24: 0000000000000000 [ 38.122246] x23: ffff80007a78cc08 x22: ffff80007b1cc018 [ 38.122249] x21: ffff80007b1cc000 x20: ffff80007b317080 [ 38.122252] x19: ffff80007a78ce80 x18: 0000000000020000 [ 38.122255] x17: 0000000000000000 x16: 0000000000000000 [ 38.122258] x15: 00000000fffffff0 x14: ffff000008c3fb48 [ 38.122261] x13: ffff000008cdac4a x12: ffff000008c3f000 [ 38.122264] x11: 0000000000000000 x10: ffff000008cda000 [ 38.122267] x9 : 0000000000000000 x8 : ffff000008ce4a40 [ 38.122269] x7 : 0000000000000000 x6 : 0000000039ea41a9 [ 38.122272] x5 : 0000000000000000 x4 : 0000000000000000 [ 38.122275] x3 : ffffffffffffffff x2 : c7580c109cae4500 [ 38.122278] x1 : 0000000000000000 x0 : 0000000000000024 [ 38.122281] Call trace: [ 38.122285] mdp5_pipe_release+0x90/0xc0 [ 38.122288] mdp5_plane_atomic_check+0x2c0/0x448 [ 38.122294] drm_atomic_helper_check_planes+0xd0/0x208 [ 38.122298] drm_atomic_helper_check+0x38/0xa8 [ 38.122302] drm_atomic_check_only+0x3e8/0x630 [ 38.122305] drm_atomic_commit+0x18/0x58 [ 38.122309] __drm_atomic_helper_disable_all.isra.12+0x15c/0x1a8 [ 38.122312] drm_atomic_helper_suspend+0x80/0xf0 [ 38.122316] msm_pm_suspend+0x4c/0x70 [ 38.122320] dpm_run_callback.isra.6+0x20/0x68 [ 38.122323] __device_suspend+0x110/0x308 [ 38.122326] dpm_suspend+0x100/0x1f0 [ 38.122329] dpm_suspend_start+0x64/0x70 [ 38.122334] suspend_devices_and_enter+0x110/0x500 [ 38.122336] pm_suspend+0x268/0x2c0 [ 38.122339] state_store+0x88/0x110 [ 38.122345] kobj_attr_store+0x14/0x28 [ 38.122352] sysfs_kf_write+0x3c/0x50 [ 38.122355] kernfs_fop_write+0x118/0x1e0 [ 38.122360] __vfs_write+0x30/0x168 [ 38.122363] vfs_write+0xa4/0x1a8 [ 38.122366] ksys_write+0x64/0xe8 [ 38.122368] __arm64_sys_write+0x18/0x20 [ 38.122374] el0_svc_common+0x6c/0x178 [ 38.122377] el0_svc_compat_handler+0x1c/0x28 [ 38.122381] el0_svc_compat+0x8/0x18 [ 38.122383] ---[ end trace 24145b7d8545345b ]--- [ 38.491552] Disabling non-boot CPUs ... Let's add a flag for duplicating the state of drm_private_obj and set the flag from msm/mdp5 driver, so that the problem can be fixed while other drivers using drm_private_obj stay unaffected. Signed-off-by: Shawn Guo <shawn.guo(a)linaro.org> --- Changes for v2: - Add a flag to duplicate the state of drm_private_obj conditionally, so that other drivers using drm_private_obj stay unaffected. drivers/gpu/drm/drm_atomic_helper.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 +++++++ include/drm/drm_atomic.h | 11 +++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 85d163f16801..4bf041730b9e 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3140,6 +3140,7 @@ drm_atomic_helper_duplicate_state(struct drm_device *dev, struct drm_atomic_state *state; struct drm_connector *conn; struct drm_connector_list_iter conn_iter; + struct drm_private_obj *priv_obj; struct drm_plane *plane; struct drm_crtc *crtc; int err = 0; @@ -3184,6 +3185,19 @@ drm_atomic_helper_duplicate_state(struct drm_device *dev, } drm_connector_list_iter_end(&conn_iter); + drm_for_each_privobj(priv_obj, dev) { + struct drm_private_state *priv_state; + + if (!priv_obj->needs_duplicate_state) + continue; + + priv_state = drm_atomic_get_private_obj_state(state, priv_obj); + if (IS_ERR(priv_state)) { + err = PTR_ERR(priv_state); + goto free; + } + } + /* clear the acquire context so that it isn't accidentally reused */ state->acquire_ctx = NULL; @@ -3278,6 +3292,8 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, struct drm_connector_state *new_conn_state; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + struct drm_private_state *new_priv_state; + struct drm_private_obj *priv_obj; state->acquire_ctx = ctx; @@ -3290,6 +3306,12 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, for_each_new_connector_in_state(state, connector, new_conn_state, i) state->connectors[i].old_state = connector->state; + for_each_new_private_obj_in_state(state, priv_obj, new_priv_state, i) { + if (!priv_obj->needs_duplicate_state) + continue; + state->private_objs[i].old_state = priv_obj->state; + } + ret = drm_atomic_commit(state); state->acquire_ctx = NULL; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 19ec48695ffb..20971c75f3a2 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -139,6 +139,13 @@ static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, &state->base, &mdp5_global_state_funcs); + + /* + * Set needs_duplicate_state flag, as we have assignment of hwpipe in + * global atomic state that needs to be duplicated for suspend state. + */ + mdp5_kms->glob_state.needs_duplicate_state = true; + return 0; } diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 7b6cb4774e7d..72d35ca7b59e 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -273,6 +273,17 @@ struct drm_private_obj { * &drm_private_state_funcs. */ const struct drm_private_state_funcs *funcs; + + /** + * @needs_duplicate_state: + * + * A flag that's set by driver in order to duplicate the state of this + * private object in drm_atomic_helper_duplicate_state(). It's required + * by drivers like msm/mdp5 where the state is used as the driver global + * atomic state, and needs to be duplicated in context of suspend helper + * drm_atomic_helper_suspend(), restored on drm_atomic_helper_resume(). + */ + bool needs_duplicate_state; }; /** -- 2.17.1

2 1

[PATCH] drm/msm/a6xx: fix crashstate capture for A650
by Jonathan Marek 10 Jul '20

10 Jul '20

A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek <jonathan(a)marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +++++ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 25 +++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 12 ++++++---- 3 files changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 47df4745db50..c6d2bced8e5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -127,6 +127,11 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ interval, timeout) +static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) +{ + return msm_readl(gmu->rscc + (offset << 2)); +} + static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) { return msm_writel(value, gmu->rscc + (offset << 2)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index d6023ba8033c..959656ad6987 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -736,7 +736,8 @@ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, const struct a6xx_registers *regs, - struct a6xx_gpu_state_obj *obj) + struct a6xx_gpu_state_obj *obj, + bool rscc) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -755,9 +756,17 @@ static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, u32 count = RANGE(regs->registers, i); int j; - for (j = 0; j < count; j++) - obj->data[index++] = gmu_read(gmu, - regs->registers[i] + j); + for (j = 0; j < count; j++) { + u32 offset = regs->registers[i] + j; + u32 val; + + if (rscc) + val = gmu_read_rscc(gmu, offset); + else + val = gmu_read(gmu, offset); + + obj->data[index++] = val; + } } } @@ -777,7 +786,9 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, /* Get the CX GMU registers from AHB */ _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0], - &a6xx_state->gmu_registers[0]); + &a6xx_state->gmu_registers[0], false); + _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], + &a6xx_state->gmu_registers[1], true); if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) return; @@ -785,8 +796,8 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, /* Set the fence to ALLOW mode so we can access the registers */ gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); - _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], - &a6xx_state->gmu_registers[1]); + _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2], + &a6xx_state->gmu_registers[2], false); } #define A6XX_GBIF_REGLIST_SIZE 1 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 24c974c293e5..846fd5b54c23 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -341,10 +341,6 @@ static const u32 a6xx_gmu_cx_registers[] = { 0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165, 0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc, 0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201, - /* GPU RSCC */ - 0x8c8c, 0x8c8c, 0x8d01, 0x8d02, 0x8f40, 0x8f42, 0x8f44, 0x8f47, - 0x8f4c, 0x8f87, 0x8fec, 0x8fef, 0x8ff4, 0x902f, 0x9094, 0x9097, - 0x909c, 0x90d7, 0x913c, 0x913f, 0x9144, 0x917f, /* GMU AO */ 0x9300, 0x9316, 0x9400, 0x9400, /* GPU CC */ @@ -357,8 +353,16 @@ static const u32 a6xx_gmu_cx_registers[] = { 0xbc00, 0xbc16, 0xbc20, 0xbc27, }; +static const u32 a6xx_gmu_cx_rscc_registers[] = { + /* GPU RSCC */ + 0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347, + 0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497, + 0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f, +}; + static const struct a6xx_registers a6xx_gmu_reglist[] = { REGS(a6xx_gmu_cx_registers, 0, 0), + REGS(a6xx_gmu_cx_rscc_registers, 0, 0), REGS(a6xx_gmu_gx_registers, 0, 0), }; -- 2.26.1

2 1

[PATCH v8 0/6] Add support for DisplayPort driver on SnapDragon
by Tanmay Shah 10 Jul '20

10 Jul '20

These patches add Display-Port driver on SnapDragon/msm hardware. This series also contains device-tree bindings for msm DP driver. It also contains Makefile and Kconfig changes to compile msm DP driver. The block diagram of DP driver is shown below: +-------------+ |DRM FRAMEWORK| +------+------+ | +----v----+ | DP DRM | +----+----+ | +----v----+ +------------+| DP +----------++------+ + +---+| DISPLAY |+---+ | | | + +-+-----+-+ | | | | | | | | | | | | | | | | | | | | | | | | v v v v v v v +------+ +------+ +---+ +----+ +----+ +---+ +-----+ | DP | | DP | |DP | | DP | | DP | |DP | | DP | |PARSER| | HPD | |AUX| |LINK| |CTRL| |PHY| |POWER| +--+---+ +---+--+ +---+ +----+ +--+-+ +-+-+ +-----+ | | | +--v---+ +v-----v+ |DEVICE| | DP | | TREE | |CATALOG| +------+ +---+---+ | +---v----+ |CTRL/PHY| | HW | +--------+ Changes in v7: - Modify cover letter description and fix title. - Introduce dp-controller.yaml for common bindings across SOC - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml for SC7180 bindings - Rename compatible string to qcom,sc7180-dp - Add assigned-clocks and assigned-clock-parents properties in bindings - Remove redundant code from driver - Extend series to include HPD detection logic Changes in v8: - Add MDSS AHB clock in bindings - Replace mode->vrefresh use with drm_mode_vrefresh API - Remove redundant aux config code from parser and aux module - Assign default max lanes if data-lanes property is not available - Fix use-after-free during DP driver remove - Unregister hardware clocks during driver cleanup This series depends-on: https://patchwork.freedesktop.org/patch/366159/ https://patchwork.freedesktop.org/patch/369859/ Chandan Uddaraju (4): dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon drm: add constant N value in helper file drm/msm/dp: add displayPort driver support drm/msm/dp: add support for DP PLL driver Jeykumar Sankaran (1): drm/msm/dpu: add display port support in DPU Tanmay Shah (1): drm/msm/dp: Add Display Port HPD feature .../display/msm/dp-controller-sc7180.yaml | 144 ++ .../bindings/display/msm/dp-controller.yaml | 61 + .../bindings/display/msm/dpu-sc7180.yaml | 11 + drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/msm/Kconfig | 16 + drivers/gpu/drm/msm/Makefile | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 83 +- drivers/gpu/drm/msm/dp/dp_aux.c | 510 +++++ drivers/gpu/drm/msm/dp/dp_aux.h | 29 + drivers/gpu/drm/msm/dp/dp_catalog.c | 1060 ++++++++++ drivers/gpu/drm/msm/dp/dp_catalog.h | 104 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1707 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 35 + drivers/gpu/drm/msm/dp/dp_display.c | 1017 ++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 31 + drivers/gpu/drm/msm/dp/dp_drm.c | 168 ++ drivers/gpu/drm/msm/dp/dp_drm.h | 18 + drivers/gpu/drm/msm/dp/dp_hpd.c | 69 + drivers/gpu/drm/msm/dp/dp_hpd.h | 79 + drivers/gpu/drm/msm/dp/dp_link.c | 1216 ++++++++++++ drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 490 +++++ drivers/gpu/drm/msm/dp/dp_panel.h | 95 + drivers/gpu/drm/msm/dp/dp_parser.c | 267 +++ drivers/gpu/drm/msm/dp/dp_parser.h | 138 ++ drivers/gpu/drm/msm/dp/dp_pll.c | 99 + drivers/gpu/drm/msm/dp/dp_pll.h | 61 + drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 917 +++++++++ drivers/gpu/drm/msm/dp/dp_pll_private.h | 111 ++ drivers/gpu/drm/msm/dp/dp_power.c | 392 ++++ drivers/gpu/drm/msm/dp/dp_power.h | 103 + drivers/gpu/drm/msm/dp/dp_reg.h | 517 +++++ drivers/gpu/drm/msm/msm_drv.c | 2 + drivers/gpu/drm/msm/msm_drv.h | 59 +- include/drm/drm_dp_helper.h | 1 + 37 files changed, 9776 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.c create mode 100644 drivers/gpu/drm/msm/dp/dp_aux.h create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.c create mode 100644 drivers/gpu/drm/msm/dp/dp_catalog.h create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.h create mode 100644 drivers/gpu/drm/msm/dp/dp_display.c create mode 100644 drivers/gpu/drm/msm/dp/dp_display.h create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_drm.h create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.h create mode 100644 drivers/gpu/drm/msm/dp/dp_link.c create mode 100644 drivers/gpu/drm/msm/dp/dp_link.h create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.c create mode 100644 drivers/gpu/drm/msm/dp/dp_panel.h create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.c create mode 100644 drivers/gpu/drm/msm/dp/dp_parser.h create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h create mode 100644 drivers/gpu/drm/msm/dp/dp_power.c create mode 100644 drivers/gpu/drm/msm/dp/dp_power.h create mode 100644 drivers/gpu/drm/msm/dp/dp_reg.h base-commit: 0a19b068acc47d05212f03e494381926dc0381e2 prerequisite-patch-id: 8058026a54241aa728a91dd1685419afb249959e prerequisite-patch-id: ed730eb83f84501579332a0f0ab98f7ef649e868 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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dri-devel June 2020