dri-devel July 2020

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[PATCH v2 0/9] drm/ast: Convert to managed initialization
by Thomas Zimmermann 30 Jul '20

30 Jul '20

This is the next patchset for converting ast to managed initialization. For v2 of the series, I moved the I2C patches into a separate patchset. This resolves a mid-series problem wrt to releasing I2C. The rest of the patches are unchanged (except for a rebase). Patches #1 to #6 address modesetting and device structures. All are being embedded into struct ast_private. With struct ast_private being a subclass of struct drm_device, patch #6 switches ast to DRM's managed- allocation helpers. Patches #7 and #8 address firmware memory that ast allocates internally. Finally, patch #9 removes ast's destroy function in favor of managed release helpers. Tested on AST 2100 HW. v2: * removed I2C patches from series Thomas Zimmermann (9): drm/ast: Embed CRTC and connector in struct ast_private drm/ast: Separate DRM driver from PCI code drm/ast: Replace driver load/unload functions with device create/destroy drm/ast: Replace struct_drm_device.dev_private with to_ast_private() drm/ast: Don't use ast->dev if dev is available drm/ast: Embed struct drm_device in struct ast_private drm/ast: Managed release of ast firmware drm/ast: Manage release of firmware backup memory drm/ast: Managed device release drivers/gpu/drm/ast/ast_cursor.c | 8 ++-- drivers/gpu/drm/ast/ast_dp501.c | 23 +++++---- drivers/gpu/drm/ast/ast_drv.c | 82 ++++++++++++++------------------ drivers/gpu/drm/ast/ast_drv.h | 43 +++++++++-------- drivers/gpu/drm/ast/ast_main.c | 74 ++++++++++++++-------------- drivers/gpu/drm/ast/ast_mm.c | 2 +- drivers/gpu/drm/ast/ast_mode.c | 40 ++++------------ drivers/gpu/drm/ast/ast_post.c | 6 +-- 8 files changed, 130 insertions(+), 148 deletions(-) -- 2.27.0

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[PATCH] drm/doc: device hot-unplug for userspace
by Pekka Paalanen 30 Jul '20

30 Jul '20

From: Pekka Paalanen <pekka.paalanen(a)collabora.com> Set up the expectations on how hot-unplugging a DRM device should look like to userspace. Written by Daniel Vetter's request and largely based on his comments in IRC and from https://lists.freedesktop.org/archives/dri-devel/2020-May/265484.html . Signed-off-by: Pekka Paalanen <pekka.paalanen(a)collabora.com> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: Andrey Grodzovsky <andrey.grodzovsky(a)amd.com> Cc: Dave Airlie <airlied(a)redhat.com> Cc: Sean Paul <sean(a)poorly.run> --- Disclaimer: I am a userspace developer writing for other userspace developers. I took some liberties in defining what should happen without knowing what is actually possible or what existing drivers already implement. --- Documentation/gpu/drm-uapi.rst | 75 ++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 56fec6ed1ad8..80db4abd2cbd 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -1,3 +1,5 @@ +.. Copyright 2020 DisplayLink (UK) Ltd. + =================== Userland interfaces =================== @@ -162,6 +164,79 @@ other hand, a driver requires shared state between clients which is visible to user-space and accessible beyond open-file boundaries, they cannot support render nodes. +Device Hot-Unplug +================= + +.. note:: + The following is the plan. Implementation is not there yet + (2020 May 13). + +Graphics devices (display and/or render) may be connected via USB (e.g. +display adapters or docking stations) or Thunderbolt (e.g. eGPU). An end +user is able to hot-unplug this kind of devices while they are being +used, and expects that the very least the machine does not crash. Any +damage from hot-unplugging a DRM device needs to be limited as much as +possible and userspace must be given the chance to handle it if it wants +to. Ideally, unplugging a DRM device still lets a desktop to continue +running, but that is going to need explicit support throughout the whole +graphics stack: from kernel and userspace drivers, through display +servers, via window system protocols, and in applications and libraries. + +Other scenarios that should lead to the same are: unrecoverable GPU +crash, PCI device disappearing off the bus, or forced unbind of a driver +from the physical device. + +In other words, from userspace perspective everything needs to keep on +working more or less, until userspace stops using the disappeared DRM +device and closes it completely. Userspace will learn of the device +disappearance from the device removed uevent or in some cases specific +ioctls returning EIO. + +This goal raises at least the following requirements for the kernel and +drivers: + +- The kernel must not hang, crash or oops, no matter what userspace was + in the middle of doing when the device disappeared. + +- All GPU jobs that can no longer run must have their fences + force-signalled to avoid inflicting hangs to userspace. + +- KMS connectors must change their status to disconnected. + +- Legacy modesets and pageflips fake success. + +- Atomic commits, both real and TEST_ONLY, fake success. + +- Pending non-blocking KMS operations deliver the DRM events userspace + is expecting. + +- If underlying memory disappears, the mmaps are replaced with harmless + zero pages where access does not raise SIGBUS. Reads return zeros, + writes are ignored. + +- dmabuf which point to memory that has disappeared are rewritten to + point to harmless zero pages, similar to mmaps. Imports still succeed + both ways: an existing device importing a dmabuf pointing to + disappeared memory, and a disappeared device importing any dmabuf. + +- Render ioctls return EIO which is then handled in userspace drivers, + e.g. Mesa, to have the device disappearance handled in the way + specified for each API (OpenGL, GL ES: GL_KHR_robustness; + Vulkan: VK_ERROR_DEVICE_LOST; etc.) + +Raising SIGBUS is not an option, because userspace cannot realistically +handle it. Signal handlers are global, which makes them extremely +difficult to use correctly from libraries like Mesa produces. Signal +handlers are not composable, you can't have different handlers for GPU1 +and GPU2 from different vendors, and a third handler for mmapped regular +files. Threads cause additional pain with signal handling as well. + +Only after userspace has closed all relevant DRM device and dmabuf file +descriptors and removed all mmaps, the DRM driver can tear down its +instance for the device that no longer exists. If the same physical +device somehow comes back in the mean time, it shall be a new DRM +device. + .. _drm_driver_ioctl: IOCTL Support on Device Nodes -- 2.20.1

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[PATCH 1/1] drm/ttm: fix offset in VMAs with a pg_offs in ttm_bo_vm_access
by Felix Kuehling 30 Jul '20

30 Jul '20

VMAs with a pg_offs that's offset from the start of the vma_node need to adjust the offset within the BO accordingly. This matches the offset calculation in ttm_bo_vm_fault_reserved. Signed-off-by: Felix Kuehling <Felix.Kuehling(a)amd.com> Tested-by: Laurent Morichetti <laurent.morichetti(a)amd.com> --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 389128b8c4dd..60b41447bec8 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -405,8 +405,10 @@ static int ttm_bo_vm_access_kmap(struct ttm_buffer_object *bo, int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned long addr, void *buf, int len, int write) { - unsigned long offset = (addr) - vma->vm_start; struct ttm_buffer_object *bo = vma->vm_private_data; + unsigned long offset = (addr) - vma->vm_start + + ((vma->vm_pgoff - drm_vma_node_start(&bo->base.vma_node)) + << PAGE_SHIFT); int ret; if (len < 1 || (offset + len) >> PAGE_SHIFT > bo->num_pages) -- 2.17.1

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[PATCH v2 0/8] drm/mgag200: Support desktop chips
by Thomas Zimmermann 30 Jul '20

30 Jul '20

This patchset puts device initialization in the correct order and adds support for G200 Desktop chips (PCI ids 0x520 and 0x521). The patchset has already been reviewed. In v2 I changed the patch 8 to copy the BIOS ROM to system memory, which simplifies parsing. The first 7 patches prepare the driver. Desktop chips would probably work without them, but since we're at it we can also do it right. Patch 1 enables cached page mappings GEM buffers. SHMEM supports this well now and the MGA device does not access the buffer memory directly. So no corrupt display output is to be expected. Patches 2 to 6 fix the initialization of device registers. Several fundamental registers were only set late during device initialization. This was probably not a problem in practice, as the VGA BIOS does the setup during POST anyway. These patches move the code to the beginning of the device initialization. If we ever have to POST an MGA device from the driver, the correct order of operations will matter. G200SEs store a unique id in the device structure. Patch 7 moves the value to model-specific data area. This will be helpful for patch 8. Patch 8 adds support for desktop chips' PCI ids. All the memory and modesetting code continues to work as before. The PLL setup code gets an additional helper for the new HW. PCI and DAC registers get a few new default values. Most significantly, the driver parses the VGA BIOS for clock settings. It's all separate from the server code, so no regressions are to be expected. The new HW support is based on an earlier patch the was posted in July 2017. [1] Tested on G200EW and G200 AGP hardware by running the fbdev console, Weston and Gnome on Xorg. v2: * copy BIOS ROM to system memory; access with load/store * fix typos [1] https://lists.freedesktop.org/archives/dri-devel/2017-July/147647.html Thomas Zimmermann (8): drm/mgag200: Enable caching for SHMEM pages drm/mgag200: Move register initialization into helper function drm/mgag200: Initialize PCI registers early during device setup drm/mgag200: Enable MGA mode during device register initialization drm/mgag200: Set MISC memory flags in mm init code drm/mgag200: Clear <page> field during MM init drm/mgag200: Move G200SE's unique id into model-specific data drm/mgag200: Add support for G200 desktop cards MAINTAINERS | 2 +- drivers/gpu/drm/mgag200/Kconfig | 12 +- drivers/gpu/drm/mgag200/mgag200_drv.c | 225 +++++++++++++++++++++++-- drivers/gpu/drm/mgag200/mgag200_drv.h | 19 ++- drivers/gpu/drm/mgag200/mgag200_mm.c | 8 + drivers/gpu/drm/mgag200/mgag200_mode.c | 153 ++++++++++------- drivers/gpu/drm/mgag200/mgag200_reg.h | 4 + 7 files changed, 340 insertions(+), 83 deletions(-) -- 2.27.0

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[PATCH i-g-t] MAINTAINERS: Change Arek's email address
by Arkadiusz Hiler 30 Jul '20

30 Jul '20

The current one will become inactive after this Friday. Cc: Petri Latvala <petri.latvala(a)intel.com> Cc: Lukasz Fiedorowicz <lukasz.fiedorowicz(a)intel.com> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler(a)intel.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index ea4e642c..383c327c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1,2 +1,2 @@ Petri Latvala <petri.latvala(a)intel.com> -Arkadiusz Hiler <arkadiusz.hiler(a)intel.com> +Arkadiusz Hiler <arek(a)hiler.eu> -- 2.25.4

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[PATCH] drm/mcde: Retry DSI read/write transactions
by Linus Walleij 30 Jul '20

30 Jul '20

The vendor driver makes a few retries on read DSI transactions, something that is needed especially in case of read (such as reading the panel MTP ID) while the panel is running in video mode. This happens on the Samsung s6e63m0 panel on the Golden device. Retry reads and writes alike two times. Cc: Stephan Gerhold <stephan(a)gerhold.net> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- drivers/gpu/drm/mcde/mcde_dsi.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c index 337c4c5e3947..76fecd7ab658 100644 --- a/drivers/gpu/drm/mcde/mcde_dsi.c +++ b/drivers/gpu/drm/mcde/mcde_dsi.c @@ -207,8 +207,8 @@ static int mcde_dsi_host_detach(struct mipi_dsi_host *host, (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ (type == MIPI_DSI_DCS_READ)) -static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg) +static ssize_t mcde_dsi_host_transfer_commit(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) { struct mcde_dsi *d = host_to_mcde_dsi(host); const u32 loop_delay_us = 10; /* us */ @@ -353,6 +353,23 @@ static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, return ret; } +static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct mcde_dsi *d = host_to_mcde_dsi(host); + int retries = 2; + ssize_t ret; + + while (retries--) { + ret = mcde_dsi_host_transfer_commit(host, msg); + if (ret >= 0) + return ret; + } + + dev_err(d->dev, "gave up transfer after retrying\n"); + return ret; +} + static const struct mipi_dsi_host_ops mcde_dsi_host_ops = { .attach = mcde_dsi_host_attach, .detach = mcde_dsi_host_detach, -- 2.26.2

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[PATCH 00/13] drm/ast: Convert to managed initialization
by Thomas Zimmermann 30 Jul '20

30 Jul '20

This is the final patchset for converting ast to managed initialization. Patches #1 to #4 address I2C helpers. The structures are being stored in struct ast_connector. The initialization and cleanups is being converted to managed release helpers. Patches #5 to #10 address modesetting and device structures. All are being embedded into struct ast_private. With struct ast_private being a subclass of struct drm_device, patch #10 switches ast to DRM's managed- allocation helpers. Patches #11 and #12 address firmware memory that ast allocates internally. Finally, patch #13 removes ast's destroy function in favor of managed release helpers. Tested on AST 2100 HW. Thomas Zimmermann (13): drm/ast: Move I2C code within ast_mode.c drm/ast: Test if I2C support has been initialized drm/ast: Embed I2C fields in struct ast_connector drm/ast: Managed release of I2C adapter drm/ast: Embed CRTC and connector in struct ast_private drm/ast: Separate DRM driver from PCI code drm/ast: Replace driver load/unload functions with device create/destroy drm/ast: Replace struct_drm_device.dev_private with to_ast_private() drm/ast: Don't use ast->dev if dev is available drm/ast: Embed struct drm_device in struct ast_private drm/ast: Managed release of ast firmware drm/ast: Manage release of firmware backup memory drm/ast: Managed device release drivers/gpu/drm/ast/ast_cursor.c | 8 +- drivers/gpu/drm/ast/ast_dp501.c | 23 ++- drivers/gpu/drm/ast/ast_drv.c | 82 ++++---- drivers/gpu/drm/ast/ast_drv.h | 43 +++-- drivers/gpu/drm/ast/ast_main.c | 74 ++++---- drivers/gpu/drm/ast/ast_mm.c | 2 +- drivers/gpu/drm/ast/ast_mode.c | 310 ++++++++++++++----------------- drivers/gpu/drm/ast/ast_post.c | 6 +- 8 files changed, 263 insertions(+), 285 deletions(-) -- 2.27.0

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[PATCH v8 0/5] Add support for iMX8MQ Display Controller Subsystem
by Laurentiu Palcu 30 Jul '20

30 Jul '20

From: Laurentiu Palcu <laurentiu.palcu(a)nxp.com> Hi, This patchset adds initial DCSS support for iMX8MQ chip. Initial support includes only graphics plane support (no video planes), no HDR10 capabilities, no graphics decompression (only linear, tiled and super-tiled buffers allowed). Support for the rest of the features will be added incrementally, in subsequent patches. The patchset was tested with both HDP driver (in the downstream tree) and the upstream MIPI-DSI driver (with a couple of patches on top, to make it work correctly with DCSS). Thanks, Laurentiu Changes in v8: * Removed 'select RESET_CONTROLLER" from Kconfig as Philipp pointed out. SRC is not used in DCSS driver; * Nothing else changed; Changes in v7: * Added a patch to initialize the connector using the drm_bridge_connector API as Sam suggested. Tested it using NWL_DSI and ADV7535 with Guido's patch [1] applied and one fix for ADV [2]. Also, some extra patches for ADV and NWL were needed, from our downstream tree, which will be upstreamed soon by their author; * Rest of the patches are untouched; [1] https://lists.freedesktop.org/archives/dri-devel/2020-July/273025.html [2] https://lists.freedesktop.org/archives/dri-devel/2020-July/273132.html Changes in v6: * Addressed Rob's comment and added "additionalProperties: false" at the end of the bindings' properties. However, this change surfaced an issue with the assigned-clock* properties not being documented in the properties section. Added the descriptions and the bindings patch will need another review; * Added an entry for DCSS driver in the MAINTAINERS file; * Removed the component framework patch altogether; Changes in v5: * Rebased to latest; * Took out component framework support and made it a separate patch so that people can still test with HDP driver, which makes use of it. But the idea is to get rid of it once HDP driver's next versions will remove component framework as well; * Slight improvement to modesetting: avoid cutting off the pixel clock if the new mode and the old one are equal. Also, in this case, is not necessary to wait for DTG to shut off. This would allow to switch from 8b RGB to 12b YUV422, for example, with no interruptions (at least from DCSS point of view); * Do not fire off CTXLD when going to suspend, unless it still has entries that need to be committed to DCSS; * Addressed Rob's comments on bindings; Changes in v4: * Addressed Lucas and Philipp's comments: * Added DRM_KMS_CMA_HELPER dependency in Kconfig; * Removed usage of devm_ functions since I'm already doing all the clean-up in the submodules_deinit(); * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush(); * Removed en_completion variable from dcss_crtc since this was introduced mainly to avoid vblank timeout warnings which were fixed by arming the vblank event in flush() instead of begin(); * Removed clks_on and irq_enabled flags since all the calls to enabling/disabling clocks and interrupts were balanced; * Removed the custom atomic_commit callback and used the DRM core helper and, in the process, got rid of a workqueue that wasn't necessary anymore; * Fixed some minor DT binding issues flagged by Philipp; * Some other minor changes suggested by Lucas; * Removed YUV formats from the supported formats as these cannot work without the HDR10 module CSCs and LUTs. Will add them back when I will add support for video planes; Changes in v3: * rebased to latest linux-next and made it compile as drmP.h was removed; * removed the patch adding the VIDEO2_PLL clock. It's already applied; * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set(); * fixed a a spurious hang reported by Lukas Hartmann and encountered by me several times; * mask DPR and DTG interrupts by default, as they may come enabled from U-boot; Changes in v2: * Removed '0x' in node's unit-address both in DT and yaml; * Made the address region size lowercase, to be consistent; * Removed some left-over references to P010; * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence compilation issues reported by kbuild for other architectures; Laurentiu Palcu (5): drm/imx: compile imx directory by default drm/imx: Add initial support for DCSS on iMX8MQ drm/imx/dcss: use drm_bridge_connector API MAINTAINERS: Add entry for i.MX 8MQ DCSS driver dt-bindings: display: imx: add bindings for DCSS .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 +++ MAINTAINERS | 8 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/imx/Kconfig | 2 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dcss/Kconfig | 8 + drivers/gpu/drm/imx/dcss/Makefile | 6 + drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 70 ++ drivers/gpu/drm/imx/dcss/dcss-crtc.c | 219 +++++ drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +++++++++ drivers/gpu/drm/imx/dcss/dcss-dev.c | 325 +++++++ drivers/gpu/drm/imx/dcss/dcss-dev.h | 177 ++++ drivers/gpu/drm/imx/dcss/dcss-dpr.c | 562 ++++++++++++ drivers/gpu/drm/imx/dcss/dcss-drv.c | 138 +++ drivers/gpu/drm/imx/dcss/dcss-dtg.c | 409 +++++++++ drivers/gpu/drm/imx/dcss/dcss-kms.c | 198 +++++ drivers/gpu/drm/imx/dcss/dcss-kms.h | 44 + drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +++++++++ drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 ++++++++++++++++++ drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++++ 20 files changed, 4107 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig create mode 100644 drivers/gpu/drm/imx/dcss/Makefile create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c -- 2.23.0

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[PATCH 1/9] drm/ttm: initialize the system domain with defaults v2
by Christian König 30 Jul '20

30 Jul '20

Instead of repeating that in each driver. v2: keep the caching limitation for VMWGFX for now. Signed-off-by: Christian König <christian.koenig(a)amd.com> Reviewed-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> Reviewed-by: Thomas Zimmermann <tzimmermann(a)suse.de> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 --- drivers/gpu/drm/drm_gem_vram_helper.c | 3 --- drivers/gpu/drm/nouveau/nouveau_bo.c | 3 --- drivers/gpu/drm/qxl/qxl_ttm.c | 3 --- drivers/gpu/drm/radeon/radeon_ttm.c | 3 --- drivers/gpu/drm/ttm/ttm_bo.c | 2 ++ drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 1 - 7 files changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0dd5e802091d..e57c49a91b73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -84,9 +84,6 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, switch (type) { case TTM_PL_SYSTEM: /* System memory */ - man->flags = 0; - man->available_caching = TTM_PL_MASK_CACHING; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_TT: /* GTT memory */ diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index 3296ed3df358..be177afdeb9a 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -1009,9 +1009,6 @@ static int bo_driver_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, { switch (type) { case TTM_PL_SYSTEM: - man->flags = 0; - man->available_caching = TTM_PL_MASK_CACHING; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_VRAM: man->func = &ttm_bo_manager_func; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 4ccf937df0d0..53af25020bb2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -655,9 +655,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, switch (type) { case TTM_PL_SYSTEM: - man->flags = 0; - man->available_caching = TTM_PL_MASK_CACHING; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_VRAM: man->flags = TTM_MEMTYPE_FLAG_FIXED; diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 1d8e07b8b19e..e9b8c921c1f0 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -54,9 +54,6 @@ static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, switch (type) { case TTM_PL_SYSTEM: /* System memory */ - man->flags = 0; - man->available_caching = TTM_PL_MASK_CACHING; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_VRAM: case TTM_PL_PRIV: diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index b474781a0920..b4cb75361577 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -76,9 +76,6 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, switch (type) { case TTM_PL_SYSTEM: /* System memory */ - man->flags = 0; - man->available_caching = TTM_PL_MASK_CACHING; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_TT: man->func = &ttm_bo_manager_func; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 469aa93ea317..b5608a0087a9 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1673,6 +1673,8 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev, * Initialize the system memory buffer type. * Other types need to be driver / IOCTL initialized. */ + bdev->man[TTM_PL_SYSTEM].available_caching = TTM_PL_MASK_CACHING; + bdev->man[TTM_PL_SYSTEM].default_caching = TTM_PL_FLAG_CACHED; ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0); if (unlikely(ret != 0)) goto out_no_sys; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index 1d78187eaba6..b2761a4b4992 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -743,7 +743,6 @@ static int vmw_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, case TTM_PL_SYSTEM: /* System memory */ man->available_caching = TTM_PL_FLAG_CACHED; - man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_VRAM: /* "On-card" video ram */ -- 2.17.1

1 8

[PATCH] drm/i915: Avoid modeset when content protection changes
by Sean Paul 30 Jul '20

30 Jul '20

From: Sean Paul <seanpaul(a)chromium.org> Instead of doing a full modeset to enable/disable content protection, simply go through the update_pipe flow which was introduced in the related patch below. This avoids flashing the screen every time the user starts viewing protected content. Related: 634852d1f468 ("drm/i915: HDCP state handling in ddi_update_pipe") Cc: Ramalingam C <ramalingam.c(a)intel.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Jani Nikula <jani.nikula(a)linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen(a)linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi(a)intel.com> Cc: intel-gfx(a)lists.freedesktop.org Signed-off-by: Sean Paul <seanpaul(a)chromium.org> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 89a4d294822d..839ce1715253 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2191,7 +2191,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, return; } - crtc_state->mode_changed = true; + to_intel_crtc_state(crtc_state)->update_pipe = true; } /* Handles the CP_IRQ raised from the DP HDCP sink */ -- Sean Paul, Software Engineer, Google / Chromium OS

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dri-devel July 2020