dri-devel July 2020

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[PATCH AUTOSEL 5.4 21/34] drm/amdgpu/gfx10: fix race condition for kiq
by Sasha Levin 20 Jul '20

20 Jul '20

From: Jack Xiao <Jack.Xiao(a)amd.com> [ Upstream commit 7d65a577bb58d4f27a3398a4c0cb0b00ab7d0511 ] During preemption test for gfx10, it uses kiq to trigger gfx preemption, which would result in race condition with flushing TLB for kiq. Signed-off-by: Jack Xiao <Jack.Xiao(a)amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang(a)amd.com> Acked-by: Christian König <christian.koenig(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 6f118292e40fb..64d96eb0a2337 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4683,12 +4683,17 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); return -ENOMEM; + } /* assert preemption condition */ amdgpu_ring_set_preempt_cond_exec(ring, false); @@ -4699,6 +4704,8 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) ++ring->trail_seq); amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); + /* poll the trailing fence */ for (i = 0; i < adev->usec_timeout; i++) { if (ring->trail_seq == -- 2.25.1

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[PATCH AUTOSEL 5.7 27/40] drm/amdgpu: fix preemption unit test
by Sasha Levin 20 Jul '20

20 Jul '20

From: Jack Xiao <Jack.Xiao(a)amd.com> [ Upstream commit d845a2051b6b673fab4229b920ea04c7c4352b51 ] Remove signaled jobs from job list and ensure the job was indeed preempted. Signed-off-by: Jack Xiao <Jack.Xiao(a)amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c0f9a651dc067..92b18c4760e55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1156,27 +1156,37 @@ static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched) static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring) { struct amdgpu_job *job; - struct drm_sched_job *s_job; + struct drm_sched_job *s_job, *tmp; uint32_t preempt_seq; struct dma_fence *fence, **ptr; struct amdgpu_fence_driver *drv = &ring->fence_drv; struct drm_gpu_scheduler *sched = &ring->sched; + bool preempted = true; if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) return; preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2)); - if (preempt_seq <= atomic_read(&drv->last_seq)) - return; + if (preempt_seq <= atomic_read(&drv->last_seq)) { + preempted = false; + goto no_preempt; + } preempt_seq &= drv->num_fences_mask; ptr = &drv->fences[preempt_seq]; fence = rcu_dereference_protected(*ptr, 1); +no_preempt: spin_lock(&sched->job_list_lock); - list_for_each_entry(s_job, &sched->ring_mirror_list, node) { + list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { + if (dma_fence_is_signaled(&s_job->s_fence->finished)) { + /* remove job from ring_mirror_list */ + list_del_init(&s_job->node); + sched->ops->free_job(s_job); + continue; + } job = to_amdgpu_job(s_job); - if (job->fence == fence) + if (preempted && job->fence == fence) /* mark the job as preempted */ job->preemption_status |= AMDGPU_IB_PREEMPTED; } -- 2.25.1

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[PATCH AUTOSEL 5.7 26/40] drm/amdgpu/gfx10: fix race condition for kiq
by Sasha Levin 20 Jul '20

20 Jul '20

From: Jack Xiao <Jack.Xiao(a)amd.com> [ Upstream commit 7d65a577bb58d4f27a3398a4c0cb0b00ab7d0511 ] During preemption test for gfx10, it uses kiq to trigger gfx preemption, which would result in race condition with flushing TLB for kiq. Signed-off-by: Jack Xiao <Jack.Xiao(a)amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang(a)amd.com> Acked-by: Christian König <christian.koenig(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0e0daf0021b60..ff94f756978d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4746,12 +4746,17 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); return -ENOMEM; + } /* assert preemption condition */ amdgpu_ring_set_preempt_cond_exec(ring, false); @@ -4762,6 +4767,8 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) ++ring->trail_seq); amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); + /* poll the trailing fence */ for (i = 0; i < adev->usec_timeout; i++) { if (ring->trail_seq == -- 2.25.1

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[PATCH] drm/nouveau/kms/nv50-: Fix CRC-related compile errors with debugfs disabled
by Lyude Paul 20 Jul '20

20 Jul '20

Looks like I made the mistake of forgetting to check whether or not this would build without CONFIG_DEBUG_FS, as the Kbuild bot reported some issues building with tegra_defconfig: In file included from drivers/gpu/drm/nouveau/nouveau_display.c:47: ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_head_crc_late_register’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:47: error: parameter name omitted 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:54: warning: no return statement in function returning non-void [-Wreturn-type] 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_handle_vblank’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:57: warning: ‘return’ with a value, in function returning void [-Wreturn-type] 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:1: note: declared here 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_check’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:23: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:43: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:9: error: parameter name omitted 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:16: warning: no return statement in function returning non-void [-Wreturn-type] 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_stop_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:114:32: error: parameter name omitted 114 | nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_prepare_notifier_contexts’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:116:43: error: parameter name omitted 116 | nv50_crc_atomic_prepare_notifier_contexts(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_start_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:118:33: error: parameter name omitted 118 | nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_set’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:21: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:41: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_clr’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:122:21: error: parameter name omitted 122 | nv50_crc_atomic_clr(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/nouveau/nouveau_display.c: In function ‘nouveau_framebuffer_new’: drivers/gpu/drm/nouveau/nouveau_display.c:286:15: warning: variable ‘width’ set but not used [-Wunused-but-set-variable] 286 | unsigned int width, height, i; | ^~~~~ So, fix the inline function declarations we use in drm/drivers/gpu/drm/nouveau/dispnv50/crc.h when CONFIG_DEBUG_FS is enabled. Fixes: 12885ecbfe62 ("drm/nouveau/kms/nvd9-: Add CRC support") Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Lyude Paul <lyude(a)redhat.com> --- drivers/gpu/drm/nouveau/dispnv50/crc.h | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index 4bc59e7793151..92df084492a8c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -106,26 +106,27 @@ struct nv50_crc_atom {}; #define nv50_crc_set_source NULL static inline void nv50_crc_init(struct drm_device *dev) {} -static inline int nv50_head_crc_late_register(struct nv50_head *) {} -static inline void -nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } +static inline int +nv50_head_crc_late_register(struct nv50_head *head) { return 0; } +static inline void nv50_crc_handle_vblank(struct nv50_head *head) {} static inline int -nv50_crc_atomic_check_head(struct nv50_head *, struct nv50_head_atom *, - struct nv50_head_atom *) {} +nv50_crc_atomic_check_head(struct nv50_head *head, + struct nv50_head_atom *asyh, + struct nv50_head_atom *armh) { return 0; } static inline void nv50_crc_atomic_check_outp(struct nv50_atom *atom) {} static inline void -nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {} +nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *) {} +nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *) {} +nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} +nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} +nv50_crc_atomic_set(struct nv50_head *head, struct nv50_head_atom *state) {} static inline void -nv50_crc_atomic_clr(struct nv50_head *) {} +nv50_crc_atomic_clr(struct nv50_head *head) {} #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */ #endif /* !__NV50_CRC_H__ */ -- 2.26.2

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[v3] arm64: dts: sc7180: add nodes for idp display
by Harigovindan P 20 Jul '20

20 Jul '20

Add nodes for IDP display. The display is Visionox RM69299. Signed-off-by: Harigovindan P <harigovi(a)codeaurora.org> --- Changes in v2: - Adding dependency patchwork series - Removing suspend configuration - Adding blank before space curly brace Changes in v3: - Updating status for mdp and mdss node to get the display working - Change in commit text This patch depends on following patchwork series: https://patchwork.kernel.org/patch/11364687/ https://patchwork.kernel.org/patch/11366303/ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 63 +++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 388f50ad4fde..349db8fe78a5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7180.dtsi" #include "pm6150.dtsi" @@ -232,6 +233,57 @@ vreg_bob: bob { }; }; +&dsi0 { + status = "okay"; + + vdda-supply = <&vreg_l3c_1p2>; + + panel@0 { + compatible = "visionox,rm69299-1080p-display"; + reg = <0>; + + vdda-supply = <&vreg_l8c_1p8>; + vdd3p3-supply = <&vreg_l18a_2p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pins>; + + reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi_phy { + status = "okay"; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + &qspi { status = "okay"; pinctrl-names = "default"; @@ -289,6 +341,17 @@ &usb_1_qmpphy { /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&pm6150l_gpio { + disp_pins: disp-pins { + pins = "gpio3"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; +}; + &qspi_clk { pinconf { pins = "gpio63"; -- 2.25.0

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[PATCH v3] arm64: dts: qcom: sc7180: Add Display Port dt node
by Tanmay Shah 20 Jul '20

20 Jul '20

Add DP device node on sc7180. Changes in v2: - Add assigned-clocks and assigned-clock-parents - Remove cell-index and pixel_rcg - Change compatible to qcom,sc7180-dp Changes in v3: - Update commit text - Make DP child node of MDSS - Remove data-lanes property from SOC dts - Disable DP node in SOC dts - Assign DP to Port2 in MDP node - Add MDSS AHB clock in DP device node This patch depends-on: https://patchwork.freedesktop.org/series/78953/ Signed-off-by: Tanmay Shah <tanmay(a)codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 49 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31b9217bb5bf..271d55db62ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2371,6 +2371,13 @@ dpu_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; }; @@ -2440,6 +2447,44 @@ dsi_phy: dsi-phy@ae94400 { status = "disabled"; }; + + msm_dp: displayport-controller@ae90000{ + status = "disabled"; + compatible = "qcom,sc7180-dp"; + + reg = <0 0xae90000 0 0x1400>; + reg-names = "dp_controller"; + + interrupt-parent = <&mdss>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&msm_dp 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + }; }; dispcc: clock-controller@af00000 { @@ -2449,8 +2494,8 @@ dispcc: clock-controller@af00000 { <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>; + <&msm_dp 0>, + <&msm_dp 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk", -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[Bug 208589] New: amdgpu screen corruption with DRI_PRIME on external monitor at resolution 2560x1440 and more then 60hz
by bugzilla-daemon＠bugzilla.kernel.org 20 Jul '20

20 Jul '20

https://bugzilla.kernel.org/show_bug.cgi?id=208589 Bug ID: 208589 Summary: amdgpu screen corruption with DRI_PRIME on external monitor at resolution 2560x1440 and more then 60hz Product: Drivers Version: 2.5 Kernel Version: 5.8.0-rc5 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: dani(a)rodler-keller.de Regression: No Created attachment 290323 --> https://bugzilla.kernel.org/attachment.cgi?id=290323&action=edit dmesg On my Dell Inc. G5 5505 I get screen corruption if I use a resolution of 2560x1440 and more than 60HZ while using the dedicated AMD Radeon RX 5600M and an external monitor. On the built in Laptop screen everything runs at 1920x1080 and 144 Hz without screen corruption. Monitor: Iiyama XUB2792QSU connected with Displayport CPU Brand: AMD Ryzen 7 4800H with Radeon Graphics Operating System Version: "Arch Linux" (64 bit) Kernel Name: Linux Kernel Version: 5.8.0-rc5-1-mainline Window Manager: GNOME Shell (Wayland) DRI_PRIME=1 glxinfo Device: AMD Radeon RX 5600M (NAVI10, DRM 3.38.0, 5.8.0-rc5-1-mainline, LLVM 10.0.0) (0x731f) Version: 20.1.3 DRI_PRIME=0 glxinfo Device: AMD RENOIR (DRM 3.38.0, 5.8.0-rc5-1-mainline, LLVM 10.0.0) (0x1636) Version: 20.1.3 -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH v6 0/4] Add support for iMX8MQ Display Controller Subsystem
by Laurentiu Palcu 20 Jul '20

20 Jul '20

From: Laurentiu Palcu <laurentiu.palcu(a)nxp.com> Hi, This patchset adds initial DCSS support for iMX8MQ chip. Initial support includes only graphics plane support (no video planes), no HDR10 capabilities, no graphics decompression (only linear, tiled and super-tiled buffers allowed). Support for the rest of the features will be added incrementally, in subsequent patches. The patchset was tested with both HDP driver (in the downstream tree) and the upstream MIPI-DSI driver (with a couple of patches on top, to make it work correctly with DCSS). Thanks, Laurentiu Changes in v6: * Addressed Rob's comment and added "additionalProperties: false" at the end of the bindings' properties. However, this change surfaced an issue with the assigned-clock* properties not being documented in the properties section. Added the descriptions and the bindings patch will need another review; * Added an entry for DCSS driver in the MAINTAINERS file; * Removed the component framework patch altogether; Changes in v5: * Rebased to latest; * Took out component framework support and made it a separate patch so that people can still test with HDP driver, which makes use of it. But the idea is to get rid of it once HDP driver's next versions will remove component framework as well; * Slight improvement to modesetting: avoid cutting off the pixel clock if the new mode and the old one are equal. Also, in this case, is not necessary to wait for DTG to shut off. This would allow to switch from 8b RGB to 12b YUV422, for example, with no interruptions (at least from DCSS point of view); * Do not fire off CTXLD when going to suspend, unless it still has entries that need to be committed to DCSS; * Addressed Rob's comments on bindings; Changes in v4: * Addressed Lucas and Philipp's comments: * Added DRM_KMS_CMA_HELPER dependency in Kconfig; * Removed usage of devm_ functions since I'm already doing all the clean-up in the submodules_deinit(); * Moved the drm_crtc_arm_vblank_event() in dcss_crtc_atomic_flush(); * Removed en_completion variable from dcss_crtc since this was introduced mainly to avoid vblank timeout warnings which were fixed by arming the vblank event in flush() instead of begin(); * Removed clks_on and irq_enabled flags since all the calls to enabling/disabling clocks and interrupts were balanced; * Removed the custom atomic_commit callback and used the DRM core helper and, in the process, got rid of a workqueue that wasn't necessary anymore; * Fixed some minor DT binding issues flagged by Philipp; * Some other minor changes suggested by Lucas; * Removed YUV formats from the supported formats as these cannot work without the HDR10 module CSCs and LUTs. Will add them back when I will add support for video planes; Changes in v3: * rebased to latest linux-next and made it compile as drmP.h was removed; * removed the patch adding the VIDEO2_PLL clock. It's already applied; * removed an unnecessary 50ms sleep in the dcss_dtg_sync_set(); * fixed a a spurious hang reported by Lukas Hartmann and encountered by me several times; * mask DPR and DTG interrupts by default, as they may come enabled from U-boot; Changes in v2: * Removed '0x' in node's unit-address both in DT and yaml; * Made the address region size lowercase, to be consistent; * Removed some left-over references to P010; * Added a Kconfig dependency of DRM && ARCH_MXC. This will also silence compilation issues reported by kbuild for other architectures; Laurentiu Palcu (4): drm/imx: compile imx directory by default drm/imx: Add initial support for DCSS on iMX8MQ MAINTAINERS: Add entry for i.MX 8MQ DCSS driver dt-bindings: display: imx: add bindings for DCSS .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 +++ MAINTAINERS | 8 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/imx/Kconfig | 2 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dcss/Kconfig | 9 + drivers/gpu/drm/imx/dcss/Makefile | 6 + drivers/gpu/drm/imx/dcss/dcss-blkctl.c | 70 ++ drivers/gpu/drm/imx/dcss/dcss-crtc.c | 219 +++++ drivers/gpu/drm/imx/dcss/dcss-ctxld.c | 424 +++++++++ drivers/gpu/drm/imx/dcss/dcss-dev.c | 314 +++++++ drivers/gpu/drm/imx/dcss/dcss-dev.h | 177 ++++ drivers/gpu/drm/imx/dcss/dcss-dpr.c | 562 ++++++++++++ drivers/gpu/drm/imx/dcss/dcss-drv.c | 138 +++ drivers/gpu/drm/imx/dcss/dcss-dtg.c | 409 +++++++++ drivers/gpu/drm/imx/dcss/dcss-kms.c | 177 ++++ drivers/gpu/drm/imx/dcss/dcss-kms.h | 43 + drivers/gpu/drm/imx/dcss/dcss-plane.c | 405 +++++++++ drivers/gpu/drm/imx/dcss/dcss-scaler.c | 826 ++++++++++++++++++ drivers/gpu/drm/imx/dcss/dcss-ss.c | 180 ++++ 20 files changed, 4075 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml create mode 100644 drivers/gpu/drm/imx/dcss/Kconfig create mode 100644 drivers/gpu/drm/imx/dcss/Makefile create mode 100644 drivers/gpu/drm/imx/dcss/dcss-blkctl.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-crtc.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ctxld.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dev.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dpr.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-drv.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-dtg.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-kms.h create mode 100644 drivers/gpu/drm/imx/dcss/dcss-plane.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-scaler.c create mode 100644 drivers/gpu/drm/imx/dcss/dcss-ss.c -- 2.17.1

4 11

[GIT PULL] etnaviv-next for 5.9
by Lucas Stach 20 Jul '20

20 Jul '20

Hi Dave, Daniel, please pull the following etnaviv updates for 5.9. Nothing too exciting: - a cleanup of our clock handling and improved error handling in this area from Lubomir - conversion to pin_user_pages for long page references from John - fixed PM runtime API error handling from Navid Regards, Lucas The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407: Linux 5.8-rc1 (2020-06-14 12:45:04 -0700) are available in the Git repository at: https://git.pengutronix.de/git/lst/linux etnaviv/next for you to fetch changes up to c5d5a32ead1e3a61a07a1e59eb52a53e4a6b2a7f: drm/etnaviv: fix ref count leak via pm_runtime_get_sync (2020-07-17 17:10:34 +0200) ---------------------------------------------------------------- John Hubbard (1): drm/etnaviv: convert get_user_pages() --> pin_user_pages() Lubomir Rintel (4): drm/etnaviv: Fix error path on failure to enable bus clk drm/etnaviv: Don't ignore errors on getting clocks drm/etnaviv: Make the "core" clock mandatory drm/etnaviv: Simplify clock enable/disable Navid Emamdoost (1): drm/etnaviv: fix ref count leak via pm_runtime_get_sync drivers/gpu/drm/etnaviv/etnaviv_gem.c | 6 ++-- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 80 +++++++++++++++++++++++++---------------------------- 2 files changed, 40 insertions(+), 46 deletions(-)

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Re: linux-next: Tree for Jul 20 (drivers/gpu/drm/bridge/sil-sii8620.o)
by Randy Dunlap 20 Jul '20

20 Jul '20

On 7/20/20 2:42 AM, Stephen Rothwell wrote: > Hi all, > > Changes since 20200717: > on x86_64: CONFIG_EXTCON=m CONFIG_DRM_SIL_SII8620=y ld: drivers/gpu/drm/bridge/sil-sii8620.o: in function `sii8620_remove': sil-sii8620.c:(.text+0x1e2): undefined reference to `extcon_unregister_notifier' ld: drivers/gpu/drm/bridge/sil-sii8620.o: in function `sii8620_probe': sil-sii8620.c:(.text+0x3751): undefined reference to `extcon_find_edev_by_node' ld: sil-sii8620.c:(.text+0x37ff): undefined reference to `extcon_register_notifier' ld: drivers/gpu/drm/bridge/sil-sii8620.o: in function `sii8620_extcon_work': sil-sii8620.c:(.text+0x3894): undefined reference to `extcon_get_state' Full randconfig file is attached. -- ~Randy Reported-by: Randy Dunlap <rdunlap(a)infradead.org>

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dri-devel July 2020