dri-devel July 2020

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[PATCH v2 0/6] iommu-arm-smmu: Add auxiliary domains and per-instance pagetables
by Jordan Crouse 08 Jul '20

08 Jul '20

This is a new refresh of support for auxiliary domains for arm-smmu-v2 and per-instance pagetables for drm/msm. The big change here from past efforts is that outside of creating a single aux-domain to enable TTBR0 all of the per-instance pagetables are created and managed exclusively in drm/msm without involving the arm-smmu driver. This fits in with the suggested model of letting the GPU hardware do what it needs and leave the arm-smmu driver blissfully unaware. Almost. In order to set up the io-pgtable properly in drm/msm we need to query the pagetable configuration from the current active domain and we need to rely on the iommu API to flush TLBs after a unmap. In the future we can optimize this in the drm/msm driver to track the state of the TLBs but for now the big hammer lets us get off the ground. This series is built on the split pagetable support [1]. [1] https://patchwork.kernel.org/patch/11628543/ v2: Remove unneeded cruft in the a6xx page switch sequence Jordan Crouse (6): iommu/arm-smmu: Add auxiliary domain support for arm-smmuv2 iommu/io-pgtable: Allow a pgtable implementation to skip TLB operations iommu/arm-smmu: Add a domain attribute to pass the pagetable config drm/msm: Add support to create a local pagetable drm/msm: Add support for address space instances drm/msm/a6xx: Add support for per-instance pagetables drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++ drivers/gpu/drm/msm/msm_drv.c | 15 +- drivers/gpu/drm/msm/msm_drv.h | 4 + drivers/gpu/drm/msm/msm_gem_vma.c | 9 + drivers/gpu/drm/msm/msm_gpu.c | 17 ++ drivers/gpu/drm/msm/msm_gpu.h | 5 + drivers/gpu/drm/msm/msm_gpummu.c | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 180 +++++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 16 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + drivers/iommu/arm-smmu.c | 231 ++++++++++++++++++++++++-- drivers/iommu/arm-smmu.h | 1 + include/linux/io-pgtable.h | 11 +- include/linux/iommu.h | 1 + 14 files changed, 507 insertions(+), 29 deletions(-) -- 2.17.1

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[PATCH v7 00/12] PCI: brcmstb: enable PCIe for STB chips
by Jim Quinlan 08 Jul '20

08 Jul '20

Patchset Summary: Enhance a PCIe host controller driver. Because of its unusual design we are foced to change dev->dma_pfn_offset into a more general role allowing multiple offsets. See the 'v1' notes below for more info. v7: Commit: "device core: Introduce DMA range map, supplanting ..." -- remove second kcalloc/copy in device.c (AndyS) -- use PTR_ERR_OR_ZERO() and PHYS_PFN() (AndyS) -- indentation, sizeof(struct ...) => sizeof(*r) (AndyS) -- add pfn.h definitions: PFN_DMA_ADDR(), DMA_ADDR_PFN() (AndyS) -- Fixed compile error in "sun6i_csi.c" (kernel test robot) Commit "ata: ahci_brcm: Fix use of BCM7216 reset controller" -- correct name of function in the commit msg (SergeiS) v6: Commit "device core: Introduce DMA range map": -- of_dma_get_range() now takes a single argument and returns either NULL, a valid map, or an ERR_PTR. (Robin) -- offsets are no longer a PFN value but an actual address. (Robin) -- the bus_dma_region struct stores the range size instead of the cpu_end and pci_end values. (Robin) -- devices that were setting a single offset with no boundaries have been modified to have boundaries; in a few places where this informatino was unavilable a /* FIXME: ... */ comment was added. (Robin) -- dma_attach_offset_range() can be called when an offset map already exists; if it's range is already present nothing is done and success is returned. (Robin) All commits: -- Man name/style/corrections/etc changed (Bjorn) -- rebase to Torvalds master v5: Commit "device core: Introduce multiple dma pfn offsets" -- in of/address.c: "map_size = 0" => "*map_size = 0" -- use kcalloc instead of kzalloc (AndyS) -- use PHYS_ADDR_MAX instead of "~(phys_addr_t)0" Commit "PCI: brcmstb: Set internal memory viewport sizes" -- now gives error on missing dma-ranges property. Commit "dt-bindings: PCI: Add bindings for more Brcmstb chips" -- removed "Allof:" from brcm,scb-sizes definition (RobH) All Commits: -- indentation style, use max chars 100 (AndyS) -- rebased to torvalds master v4: Commit "device core: Introduce multiple dma pfn offsets" -- of_dma_get_range() does not take a dev param but instead takes two "out" params: map and map_size. We do this so that the code that parses dma-ranges is separate from the code that modifies 'dev'. (Nicolas) -- the separate case of having a single pfn offset has been removed and is now processed by going through the map array. (Nicolas) -- move attach_uniform_dma_pfn_offset() from of/address.c to dma/mapping.c so that it does not depend on CONFIG_OF. (Nicolas) -- devm_kcalloc => devm_kzalloc (DanC) -- add/fix assignment to dev->dma_pfn_offset_map for func attach_uniform_dma_pfn_offset() (DanC, Nicolas) -- s/struct dma_pfn_offset_region/struct bus_dma_region/ (Nicolas) -- s/attach_uniform_dma_pfn_offset/dma_attach_uniform_pfn_offset/ -- s/attach_dma_pfn_offset_map/dma_attach_pfn_offset_map/ -- More use of PFN_{PHYS,DOWN,UP}. (AndyS) Commit "of: Include a dev param in of_dma_get_range()" -- this commit was sqaushed with "device core: Introduce ..." v3: Commit "device core: Introduce multiple dma pfn offsets" Commit "arm: dma-mapping: Invoke dma offset func if needed" -- The above two commits have been squashed. More importantly, the code has been modified so that the functionality for multiple pfn offsets subsumes the use of dev->dma_pfn_offset. In fact, dma_pfn_offset is removed and supplanted by dma_pfn_offset_map, which is a pointer to an array. The more common case of a uniform offset is now handled as a map with a single entry, while cases requiring multiple pfn offsets use a map with multiple entries. Code paths that used to do this: dev->dma_pfn_offset = mydrivers_pfn_offset; have been changed to do this: attach_uniform_dma_pfn_offset(dev, pfn_offset); Commit "dt-bindings: PCI: Add bindings for more Brcmstb chips" -- Add if/then clause for required props: resets, reset-names (RobH) -- Change compatible list from const to enum (RobH) -- Change list of u32-tuples to u64 (RobH) Commit "of: Include a dev param in of_dma_get_range()" -- modify of/unittests.c to add NULL param in of_dma_get_range() call. Commit "device core: Add ability to handle multiple dma offsets" -- align comment in device.h (AndyS). -- s/cpu_beg/cpu_start/ and s/dma_beg/dma_start/ in struct dma_pfn_offset_region (AndyS). v2: Commit: "device core: Add ability to handle multiple dma offsets" o Added helper func attach_dma_pfn_offset_map() in address.c (Chistoph) o Helpers funcs added to __phys_to_dma() & __dma_to_phys() (Christoph) o Added warning when multiple offsets are needed and !DMA_PFN_OFFSET_MAP o dev->dma_pfn_map => dev->dma_pfn_offset_map o s/frm/from/ for dma_pfn_offset_frm_{phys,dma}_addr() (Christoph) o In device.h: s/const void */const struct dma_pfn_offset_region */ o removed 'unlikely' from unlikely(dev->dma_pfn_offset_map) since guarded by CONFIG_DMA_PFN_OFFSET_MAP (Christoph) o Since dev->dma_pfn_offset is copied in usb/core/{usb,message}.c, now dev->dma_pfn_offset_map is copied as well. o Merged two of the DMA commits into one (Christoph). Commit "arm: dma-mapping: Invoke dma offset func if needed": o Use helper functions instead of #if CONFIG_DMA_PFN_OFFSET Other commits' changes: o Removed need for carrying of_id var in priv (Nicolas) o Commit message rewordings (Bjorn) o Commit log messages filled to 75 chars (Bjorn) o devm_reset_control_get_shared()) => devm_reset_control_get_optional_shared (Philipp) o Add call to reset_control_assert() in PCIe remove routines (Philipp) v1: This patchset expands the usefulness of the Broadcom Settop Box PCIe controller by building upon the PCIe driver used currently by the Raspbery Pi. Other forms of this patchset were submitted by me years ago and not accepted; the major sticking point was the code required for the DMA remapping needed for the PCIe driver to work [1]. There have been many changes to the DMA and OF subsystems since that time, making a cleaner and less intrusive patchset possible. This patchset implements a generalization of "dev->dma_pfn_offset", except that instead of a single scalar offset it provides for multiple offsets via a function which depends upon the "dma-ranges" property of the PCIe host controller. This is required for proper functionality of the BrcmSTB PCIe controller and possibly some other devices. [1] https://lore.kernel.org/linux-arm-kernel/1516058925-46522-5-git-send-email-… Jim Quinlan (12): PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB ata: ahci_brcm: Fix use of BCM7216 reset controller dt-bindings: PCI: Add bindings for more Brcmstb chips PCI: brcmstb: Add bcm7278 register info PCI: brcmstb: Add suspend and resume pm_ops PCI: brcmstb: Add bcm7278 PERST# support PCI: brcmstb: Add control of rescal reset device core: Introduce DMA range map, supplanting dma_pfn_offset PCI: brcmstb: Set additional internal memory DMA viewport sizes PCI: brcmstb: Accommodate MSI for older chips PCI: brcmstb: Set bus max burst size by chip type PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list .../bindings/pci/brcm,stb-pcie.yaml | 56 ++- arch/arm/include/asm/dma-mapping.h | 9 +- arch/arm/mach-keystone/keystone.c | 17 +- arch/sh/drivers/pci/pcie-sh7786.c | 9 +- arch/sh/kernel/dma-coherent.c | 16 +- arch/x86/pci/sta2x11-fixup.c | 7 +- drivers/acpi/arm64/iort.c | 5 +- drivers/ata/ahci_brcm.c | 11 +- drivers/gpu/drm/sun4i/sun4i_backend.c | 7 +- drivers/iommu/io-pgtable-arm.c | 2 +- .../platform/sunxi/sun4i-csi/sun4i_csi.c | 6 +- .../platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +- drivers/of/address.c | 95 ++-- drivers/of/device.c | 47 +- drivers/of/of_private.h | 9 +- drivers/of/unittest.c | 35 +- drivers/pci/controller/Kconfig | 3 +- drivers/pci/controller/pcie-brcmstb.c | 408 +++++++++++++++--- drivers/remoteproc/remoteproc_core.c | 2 +- .../staging/media/sunxi/cedrus/cedrus_hw.c | 8 +- drivers/usb/core/message.c | 4 +- drivers/usb/core/usb.c | 2 +- include/linux/device.h | 4 +- include/linux/dma-direct.h | 10 +- include/linux/dma-mapping.h | 37 ++ include/linux/pfn.h | 2 + kernel/dma/coherent.c | 10 +- kernel/dma/mapping.c | 53 +++ 28 files changed, 682 insertions(+), 197 deletions(-) -- 2.17.1

1 1

[PULL] drm-intel-fixes
by Rodrigo Vivi 08 Jul '20

08 Jul '20

Hi Dave and Daniel, A few patches this week while I'm covering Joonas vacation. Most of the patches below also target stable trees (5.5+) Here goes drm-intel-fixes-2020-07-08: One display's fbc patch fixing fence_y_offset calculation from Ville and 4 patches from Chris on GEM: 1 fixing a debugfs panic and others fixing vma construction and pin under vm->mutex. Thanks, Rodrigo. The following changes since commit dcb7fd82c75ee2d6e6f9d8cc71c52519ed52e258: Linux 5.8-rc4 (2020-07-05 16:20:22 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-07-08 for you to fetch changes up to 5a383d443b29a140094430f3ad1d02fa1acc2b80: drm/i915/gt: Pin the rings before marking active (2020-07-07 18:00:15 -0700) ---------------------------------------------------------------- One display's fbc patch fixing fence_y_offset calculation from Ville and 4 patches from Chris on GEM: 1 fixing a debugfs panic and others fixing vma construction and pin under vm->mutex. ---------------------------------------------------------------- Chris Wilson (4): drm/i915: Skip stale object handle for debugfs per-file-stats drm/i915: Drop vm.ref for duplicate vma on construction drm/i915: Also drop vm.ref along error paths for vma construction drm/i915/gt: Pin the rings before marking active Ville Syrjälä (1): drm/i915/fbc: Fix fence_y_offset handling drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 1 + drivers/gpu/drm/i915/display/intel_fbc.c | 32 +++++++++------------------- drivers/gpu/drm/i915/gt/intel_context.c | 12 +++++------ drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_vma.c | 15 ++++++------- 7 files changed, 38 insertions(+), 41 deletions(-)

1 0

[PATCH 0/2] drm/probe_helper, i915: Validate MST modes against PBN limits
by Lyude Paul 08 Jul '20

08 Jul '20

Something we've been missing for a while with drivers that support MST is being able to prune modes that can't be set due to bandwidth limitations. So, let's go ahead and add that. This also adds a new hook that was needed, mode_valid_ctx, so that we can grab additional locks as needed when validating modes. Lee Shawn C (1): drm/i915/mst: filter out the display mode exceed sink's capability Lyude Paul (1): drm/probe_helper: Add drm_connector_helper_funcs.mode_valid_ctx drivers/gpu/drm/drm_crtc_helper_internal.h | 6 +- drivers/gpu/drm/drm_probe_helper.c | 65 ++++++++++++++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 39 +++++++++++-- include/drm/drm_modeset_helper_vtables.h | 41 +++++++++++++ 4 files changed, 123 insertions(+), 28 deletions(-) -- 2.26.2

2 7

[PATCH][next] drm/nouveau: Use fallthrough pseudo-keyword
by Gustavo A. R. Silva 08 Jul '20

08 Jul '20

Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fa… Signed-off-by: Gustavo A. R. Silva <gustavoars(a)kernel.org> --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 - drivers/gpu/drm/nouveau/nouveau_bo.c | 2 - drivers/gpu/drm/nouveau/nouveau_connector.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c | 34 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 10 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c | 12 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c | 2 - 17 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index d472942102f5..ee365f31056b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -932,7 +932,7 @@ nv50_dp_bpc_to_depth(unsigned int bpc) switch (bpc) { case 6: return 0x2; case 8: return 0x5; - case 10: /* fall-through */ + case 10: fallthrough; default: return 0x6; } } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index c40f127de3d0..00581e6d183f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1458,7 +1458,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) /* untiled */ break; - /* fall through - tiled memory */ + fallthrough; /* tiled memory */ case TTM_PL_VRAM: reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.base = device->func->resource_addr(device, 1); diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 1b383ae0248f..ae3b3002d737 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -331,7 +331,7 @@ nouveau_conn_attach_properties(struct drm_connector *connector) case DRM_MODE_CONNECTOR_VGA: if (disp->disp.object.oclass < NV50_DISP) break; /* Can only scale on DFPs. */ - /* Fall-through. */ + fallthrough; default: drm_object_attach_property(&connector->base, dev->mode_config. scaling_mode_property, @@ -446,7 +446,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector) case DCB_OUTPUT_LVDS: switcheroo_ddc = !!(vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC); - /* fall-through */ + fallthrough; default: if (!nv_encoder->i2c) break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c index 7147dc6d9018..1ccfc8314812 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c @@ -23,55 +23,55 @@ void pack_hdmi_infoframe(struct packed_hdmi_infoframe *packed_frame, */ case 17: subpack1_high = (raw_frame[16] << 16); - /* fall through */ + fallthrough; case 16: subpack1_high |= (raw_frame[15] << 8); - /* fall through */ + fallthrough; case 15: subpack1_high |= raw_frame[14]; - /* fall through */ + fallthrough; case 14: subpack1_low = (raw_frame[13] << 24); - /* fall through */ + fallthrough; case 13: subpack1_low |= (raw_frame[12] << 16); - /* fall through */ + fallthrough; case 12: subpack1_low |= (raw_frame[11] << 8); - /* fall through */ + fallthrough; case 11: subpack1_low |= raw_frame[10]; - /* fall through */ + fallthrough; case 10: subpack0_high = (raw_frame[9] << 16); - /* fall through */ + fallthrough; case 9: subpack0_high |= (raw_frame[8] << 8); - /* fall through */ + fallthrough; case 8: subpack0_high |= raw_frame[7]; - /* fall through */ + fallthrough; case 7: subpack0_low = (raw_frame[6] << 24); - /* fall through */ + fallthrough; case 6: subpack0_low |= (raw_frame[5] << 16); - /* fall through */ + fallthrough; case 5: subpack0_low |= (raw_frame[4] << 8); - /* fall through */ + fallthrough; case 4: subpack0_low |= raw_frame[3]; - /* fall through */ + fallthrough; case 3: header = (raw_frame[2] << 16); - /* fall through */ + fallthrough; case 2: header |= (raw_frame[1] << 8); - /* fall through */ + fallthrough; case 1: header |= raw_frame[0]; - /* fall through */ + fallthrough; case 0: break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c index 7f1adab21a5f..5159d5df20a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c @@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, break; case NV_MEM_ACCESS_WO: dmaobj->flags0 |= 0x00008000; - /* fall through */ + fallthrough; case NV_MEM_ACCESS_RW: dmaobj->flags2 |= 0x00000002; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 93493b335d76..c1d1b1aa5bc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -117,10 +117,10 @@ nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) switch (mthd) { case 0x0000 ... 0x0000: /* subchannel's engine -> software */ nvkm_wr32(device, 0x003280, (engine &= ~mask)); - /* fall through */ + fallthrough; case 0x0180 ... 0x01fc: /* handle -> instance */ data = nvkm_rd32(device, 0x003258) & 0x0000ffff; - /* fall through */ + fallthrough; case 0x0100 ... 0x017c: case 0x0200 ... 0x1ffc: /* pass method down to sw */ if (!(engine & mask) && sw) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 47c16821c37f..2d61fd832ddb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,7 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); - /* fall through */ + fallthrough; case 0x40: case 0x41: case 0x42: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index a8d5d67feeaf..8698f260b988 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -172,8 +172,8 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, outp->dpconf.link_nr = 1; break; } + fallthrough; - /* fall-through... */ case DCB_OUTPUT_TMDS: case DCB_OUTPUT_LVDS: outp->link = (conf & 0x00000030) >> 4; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c index b099d1209be8..c694501ae206 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c @@ -100,7 +100,7 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx, switch (*ver) { case 0x20: info->mask |= 0x00c0; /* match any link */ - /* fall-through */ + fallthrough; case 0x21: case 0x30: info->flags = nvbios_rd08(bios, data + 0x05); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 7112992e0e38..f039388f0676 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -135,7 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x30: info->script = nvbios_rd16(bios, perf + 0x02); - /* fall through */ + fallthrough; case 0x35: info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->voltage = nvbios_rd08(bios, perf + 0x07); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index bda6cc9a7aaf..350f10a3de37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c @@ -134,7 +134,7 @@ pll_map(struct nvkm_bios *bios) device->chipset == 0xaa || device->chipset == 0xac) return g84_pll_mapping; - /* fall through */ + fallthrough; default: return NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c index 20ff5173cf8f..2da45e29f68b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c @@ -115,21 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx, switch (min_t(u8, *hdr, 25)) { case 25: p->timing_10_24 = nvbios_rd08(bios, data + 0x18); - /* fall through */ + fallthrough; case 24: case 23: case 22: p->timing_10_21 = nvbios_rd08(bios, data + 0x15); - /* fall through */ + fallthrough; case 21: p->timing_10_20 = nvbios_rd08(bios, data + 0x14); - /* fall through */ + fallthrough; case 20: p->timing_10_CWL = nvbios_rd08(bios, data + 0x13); - /* fall through */ + fallthrough; case 19: p->timing_10_18 = nvbios_rd08(bios, data + 0x12); - /* fall through */ + fallthrough; case 18: case 17: p->timing_10_16 = nvbios_rd08(bios, data + 0x10); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index 40e564524b7a..dc184e857f85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -90,7 +90,7 @@ nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, case NVKM_CLK_BOOST_NONE: if (clk->base_khz && freq > clk->base_khz) return false; - /* fall through */ + fallthrough; case NVKM_CLK_BOOST_BIOS: if (clk->boost_khz && freq > clk->boost_khz) return false; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 4f000237796f..efa50274df97 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -363,7 +363,7 @@ mcp77_clk_prog(struct nvkm_clk *base) switch (clk->vsrc) { case nv_clk_src_cclk: mast |= 0x00400000; - /* fall through */ + fallthrough; default: nvkm_wr32(device, 0x4600, clk->vdiv); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c index c3dae05348eb..317ce9fb8225 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c @@ -119,11 +119,11 @@ powerctrl_1_shift(int chip_version, int reg) switch (reg) { case 0x680520: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680508: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680504: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680500: shift += 4; } @@ -245,11 +245,11 @@ setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, switch (reg1) { case 0x680504: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680500: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680520: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680508: shift_c040 += 2; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 5f4c287d7943..97b3a28ca5c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -131,13 +131,13 @@ nv40_ram_prog(struct nvkm_ram *base) nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004048, ram->coef); nvkm_wr32(device, 0x004030, ram->coef); - /* fall through */ + fallthrough; case 0x43: case 0x49: case 0x4b: nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x00403c, ram->coef); - /* fall through */ + fallthrough; default: nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004024, ram->coef); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index 2a6150ab5611..70e2c414bb7b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -159,7 +159,7 @@ mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb) break; case 0x0e: /* eDP, falls through to DPint */ ctx.outp[1] |= 0x00010000; - /* fall through */ + fallthrough; case 0x07: /* DP internal, wtf is this?? HP8670w */ ctx.outp[1] |= 0x00000004; /* use_power_scripts? */ type = DCB_CONNECTOR_eDP;

3 3

[RFC PATCH 0/2] Add Xilinx DSI-TX DRM driver
by Venkateshwar Rao Gannavarapu 08 Jul '20

08 Jul '20

MIPI DSI TX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between the video processing subsystems and MIPI-based displays. An internal high-speed physical layer design, D-PHY, is provided to allow direct connection to display peripherals. The subsystem consists of the following sub-blocks: - MIPI D-PHY - MIPI DSI TX Controller - AXI Crossbar Please refer pg238 [1]. The DSI TX Controller receives stream of image data through an input stream interface. At design time, this subsystem can be configured to number of lanes and command mode support. This patch series adds the dt-binding and DRM driver for Xilinx DSI-TX soft IP. patch is created on git://linuxtv.org/pinchartl/media.git drm/dpsub/next References: [1]: https://www.xilinx.com/support/documentation/ip_documentation/mipi_dsi_tx_s… Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings drm: xlnx: driver for Xilinx DSI TX Subsystem .../devicetree/bindings/display/xlnx/xlnx,dsi.txt | 68 ++ drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 +++++++++++++++++++++ 4 files changed, 836 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

5 16

[PATCH] drm: imx: Fix occasional screen corruption on modeset.
by Martin Fuzzey 08 Jul '20

08 Jul '20

When performing a modeset the atomic core calls ipu_crtc_atomic_disable() which switches off the DC and DI. When we immediately restart as in the modeset case this sometimes leads to corruption at the bottom of the screen looking like a mirror image of the top. The exact reason isn't understood but it seems timing related. This was observed on i.MX6DL on a system that does 2 mode transitions on boot (fbcon->android boot animation->android homescreen) then no more during normal operation resulting in corruption about once every 10 boots that lasted for variable durations from a few seconds to several hours. Dumping the buffers confirmed that they were correct in memory, just the display was wrong. For tests the problem was reproduced systematically by forcing a full modeset every 10 frames even if when not required. Leaving the DC and DI on if the CRTC is staying on fixes this. Signed-off-by: Martin Fuzzey <martin.fuzzey(a)flowbird.group> --- drivers/gpu/drm/imx/ipuv3-crtc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 63c0284..9137b64 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -84,8 +84,15 @@ static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); - ipu_dc_disable_channel(ipu_crtc->dc); - ipu_di_disable(ipu_crtc->di); + /* + * If we are just doing a modeset don't disable dc/di as that + * sometimes leads to corruption at the bottom of the screen + */ + if (!crtc->state->active) { + ipu_dc_disable_channel(ipu_crtc->dc); + ipu_di_disable(ipu_crtc->di); + } + /* * Planes must be disabled before DC clock is removed, as otherwise the * attached IDMACs will be left in undefined state, possibly hanging -- 1.9.1

3 2

[PATCH v2] drm/vgem: Replace opencoded version of drm_gem_dumb_map_offset()
by Chris Wilson 08 Jul '20

08 Jul '20

drm_gem_dumb_map_offset() now exists and does everything vgem_gem_dump_map does and *ought* to do. In particular, vgem_gem_dumb_map() was trying to reject mmapping an imported dmabuf by checking the existence of obj->filp. Unfortunately, we always allocated an obj->filp, even if unused for an imported dmabuf. Instead, the drm_gem_dumb_map_offset(), since 90378e589192 ("drm/gem: drm_gem_dumb_map_offset(): reject dma-buf"), uses the obj->import_attach to reject such invalid mmaps. This prevents vgem from allowing userspace mmapping the dumb handle and attempting to incorrectly fault in remote pages belonging to another device, where there may not even be a struct page. v2: Use the default drm_gem_dumb_map_offset() callback Fixes: af33a9190d02 ("drm/vgem: Enable dmabuf import interfaces") Signed-off-by: Chris Wilson <chris(a)chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: <stable(a)vger.kernel.org> # v4.13+ --- drivers/gpu/drm/vgem/vgem_drv.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index 909eba43664a..204d1df5a21d 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -229,32 +229,6 @@ static int vgem_gem_dumb_create(struct drm_file *file, struct drm_device *dev, return 0; } -static int vgem_gem_dumb_map(struct drm_file *file, struct drm_device *dev, - uint32_t handle, uint64_t *offset) -{ - struct drm_gem_object *obj; - int ret; - - obj = drm_gem_object_lookup(file, handle); - if (!obj) - return -ENOENT; - - if (!obj->filp) { - ret = -EINVAL; - goto unref; - } - - ret = drm_gem_create_mmap_offset(obj); - if (ret) - goto unref; - - *offset = drm_vma_node_offset_addr(&obj->vma_node); -unref: - drm_gem_object_put_unlocked(obj); - - return ret; -} - static struct drm_ioctl_desc vgem_ioctls[] = { DRM_IOCTL_DEF_DRV(VGEM_FENCE_ATTACH, vgem_fence_attach_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(VGEM_FENCE_SIGNAL, vgem_fence_signal_ioctl, DRM_RENDER_ALLOW), @@ -448,7 +422,6 @@ static struct drm_driver vgem_driver = { .fops = &vgem_driver_fops, .dumb_create = vgem_gem_dumb_create, - .dumb_map_offset = vgem_gem_dumb_map, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -- 2.27.0

1 1

[PATCH AUTOSEL 4.14 1/5] drm/exynos: fix ref count leak in mic_pre_enable
by Sasha Levin 08 Jul '20

08 Jul '20

From: Navid Emamdoost <navid.emamdoost(a)gmail.com> [ Upstream commit d4f5a095daf0d25f0b385e1ef26338608433a4c5 ] in mic_pre_enable, pm_runtime_get_sync is called which increments the counter even in case of failure, leading to incorrect ref count. In case of failure, decrement the ref count before returning. Signed-off-by: Navid Emamdoost <navid.emamdoost(a)gmail.com> Signed-off-by: Inki Dae <inki.dae(a)samsung.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/exynos/exynos_drm_mic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c index ba4a32b132baa..59ce068b152f5 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_mic.c +++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c @@ -267,8 +267,10 @@ static void mic_pre_enable(struct drm_bridge *bridge) goto unlock; ret = pm_runtime_get_sync(mic->dev); - if (ret < 0) + if (ret < 0) { + pm_runtime_put_noidle(mic->dev); goto unlock; + } mic_set_path(mic, 1); -- 2.25.1

1 0

[PATCH AUTOSEL 4.19 1/8] drm/msm: fix potential memleak in error branch
by Sasha Levin 08 Jul '20

08 Jul '20

From: Bernard Zhao <bernard(a)vivo.com> [ Upstream commit 177d3819633cd520e3f95df541a04644aab4c657 ] In function msm_submitqueue_create, the queue is a local variable, in return -EINVAL branch, queue didn`t add to ctx`s list yet, and also didn`t kfree, this maybe bring in potential memleak. Signed-off-by: Bernard Zhao <bernard(a)vivo.com> [trivial commit msg fixup] Signed-off-by: Rob Clark <robdclark(a)chromium.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index 5115f75b5b7f3..325da440264a3 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -78,8 +78,10 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, queue->flags = flags; if (priv->gpu) { - if (prio >= priv->gpu->nr_rings) + if (prio >= priv->gpu->nr_rings) { + kfree(queue); return -EINVAL; + } queue->prio = prio; } -- 2.25.1

1 1

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dri-devel July 2020