dri-devel July 2020

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[RFC PATCH v5 0/6] Exynos: Simple QoS for exynos-bus using interconnect
by Sylwester Nawrocki 02 Jul '20

02 Jul '20

This patchset adds interconnect API support for the Exynos SoC "samsung, exynos-bus" compatible devices, which already have their corresponding exynos-bus driver in the devfreq subsystem. Complementing the devfreq driver with an interconnect functionality allows to ensure the QoS requirements of devices accessing the system memory (e.g. video processing devices) are fulfilled and to avoid issues like the one discussed in thread [1]. This patch series depends on 3 patches from Artur for the interconnect API [2], which introduce following changes: - exporting of_icc_get_from_provider() to avoid hard coding every graph edge in the DT or driver source, - relaxing the requirement on #interconnect-cells, so there is no need to provide dummy node IDs in the DT, - adding new field in struct icc_provider to explicitly allow configuring node pairs from two different providers. This series adds implementation of interconnect provider per each "samsung, exynos-bus" compatible DT node, with one interconnect node per provider. The interconnect code which was previously added as a part of the devfreq driver has been converted to a separate platform driver. In the devfreq a corresponding virtual child platform device is registered. Integration of devfreq and interconnect frameworks is achieved through the PM QoS API. A sample interconnect consumer for exynos-mixer is added in patches 5/6, 6/6, it is currently added only for exynos4412 and allows to address the mixer DMA underrun error issues [1]. The series has been tested on Odroid U3 board. It is based on icc-next branch with devfreq-next branch merged and patches [2] applied. -- Regards, Sylwester -- Changes since v3 [3] (v4 skipped to align with patchset [1]), detailed changes are listed at each patch: - conversion to a separate interconnect (platform) driver, - an update of the DT binding documenting new optional properties: #interconnect-cells, samsung,interconnect-parent in "samsung,exynos-bus" nodes, - new DT properties added to the SoC, rather than to the board specific files. Changes since v2 [5]: - Use icc_std_aggregate(). - Implement a different modification of apply_constraints() in drivers/interconnect/core.c (patch 03). - Use 'exynos,interconnect-parent-node' in the DT instead of 'devfreq'/'parent', depending on the bus. - Rebase on DT patches that deprecate the 'devfreq' DT property. - Improve error handling, including freeing generated IDs on failure. - Remove exynos_bus_icc_connect() and add exynos_bus_icc_get_parent(). Changes since v1 [4]: - Rebase on coupled regulators patches. - Use dev_pm_qos_*() API instead of overriding frequency in exynos_bus_target(). - Use IDR for node ID allocation. - Reverse order of multiplication and division in mixer_set_memory_bandwidth() (patch 07) to avoid integer overflow. References: [1] https://patchwork.kernel.org/patch/10861757/ (original issue) [2] https://www.spinics.net/lists/linux-samsung-soc/msg70014.html [3] https://lore.kernel.org/linux-pm/20191220115653.6487-1-a.swigon@samsung.com [4] https://patchwork.kernel.org/cover/11054417/ (v1 of this RFC) [5] https://patchwork.kernel.org/cover/11152595/ (v2 of this RFC) Artur Świgoń (1): ARM: dts: exynos: Add interconnects to Exynos4412 mixer Marek Szyprowski (1): drm: exynos: mixer: Add interconnect support Sylwester Nawrocki (4): dt-bindings: exynos-bus: Add documentation for interconnect properties interconnect: Add generic interconnect driver for Exynos SoCs PM / devfreq: exynos-bus: Add registration of interconnect child device ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes .../devicetree/bindings/devfreq/exynos-bus.txt | 15 +- arch/arm/boot/dts/exynos4412.dtsi | 6 + drivers/devfreq/exynos-bus.c | 17 ++ drivers/gpu/drm/exynos/exynos_mixer.c | 73 +++++++- drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/exynos/Kconfig | 6 + drivers/interconnect/exynos/Makefile | 4 + drivers/interconnect/exynos/exynos.c | 185 +++++++++++++++++++++ 9 files changed, 301 insertions(+), 7 deletions(-) create mode 100644 drivers/interconnect/exynos/Kconfig create mode 100644 drivers/interconnect/exynos/Makefile create mode 100644 drivers/interconnect/exynos/exynos.c -- 2.7.4

5 26

[PATCH] drm/hisilicon: Use drmm_kzalloc() instead of devm_kzalloc()
by Tian Tao 02 Jul '20

02 Jul '20

using the new API drmm_kzalloc() instead of devm_kzalloc() Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index a6fd0c2..2f20704 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -23,6 +23,7 @@ #include <drm/drm_print.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> +#include <drm/drm_managed.h> #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" @@ -267,7 +268,7 @@ static int hibmc_load(struct drm_device *dev) struct hibmc_drm_private *priv; int ret; - priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); + priv = drmm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) { DRM_ERROR("no memory to allocate for hibmc_drm_private\n"); return -ENOMEM; -- 2.7.4

4 4

Re: [PATCH] drm/msm/dpu: fix wrong return value in dpu_encoder_init()
by Markus Elfring 02 Jul '20

02 Jul '20

> A positive value ENOMEM is returned here. I thinr this is a typo error. > It is necessary to return a negative error value. I imagine that a small adjustment could be nice for this change description. How do you think about to follow progress for the integration of a previous patch like “[RESEND] drm/msm/dpu: fix error return code in dpu_encoder_init”? https://lore.kernel.org/dri-devel/20200618062803.152097-1-chentao107@huawei… https://lore.kernel.org/patchwork/patch/1257957/ https://lkml.org/lkml/2020/6/18/46 Regards, Markus

1 0

[PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain"
by Lionel Landwerlin 02 Jul '20

02 Jul '20

This reverts commit 5de376bb434f80a13138f0ebedc8351ab73d8b0d. This change breaks synchronization of a timeline. dma_fence_chain_find_seqno() might be a bit of a confusing name but this function is not trying to find a particular seqno, is supposed to give a fence to wait on for a particular point in the timeline. In a timeline, a particular value is reached when all the points up to and including that value have signaled. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> --- drivers/dma-buf/dma-fence-chain.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index c435bbba851c..3d123502ff12 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -99,12 +99,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) return -EINVAL; dma_fence_chain_for_each(*pfence, &chain->base) { - if ((*pfence)->seqno < seqno) { /* already signaled */ - dma_fence_put(*pfence); - *pfence = NULL; - break; - } - if ((*pfence)->context != chain->base.context || to_dma_fence_chain(*pfence)->prev_seqno < seqno) break; @@ -228,7 +222,6 @@ EXPORT_SYMBOL(dma_fence_chain_ops); * @chain: the chain node to initialize * @prev: the previous fence * @fence: the current fence - * @seqno: the sequence number (syncpt) of the fence within the chain * * Initialize a new chain node and either start a new chain or add the node to * the existing chain of the previous fence. -- 2.27.0

7 19

[PATCH 00/14] drm/ast: Managed modesetting
by Thomas Zimmermann 02 Jul '20

02 Jul '20

This is the first patchset to convert ast to use managed interfaces. These patches address modesetting. I expect that there will be at least one more set of patches for memory management and one for device strcutures. Patches 1 to 11 tackle HW cursor handling. The overall point is to get cursor support out of the plane functions and put the code into helpers. There are quite a few improvements that make cursors easier and faster to use. Patch 10 converts cursors to managed release. With cursors out of the way, modesetting initialization is much more simple. Patches 12 to 14 put all related code next to each other and switch to managed initialization. The patchset was tested on AST2100 hardware. Thomas Zimmermann (14): drm/ast: Move cursor functions to ast_cursor.c drm/ast: Pass struct ast_private instance to cursor init/fini functions drm/ast: Move cursor fb pinning and mapping into helper drm/ast: Update cursor image and checksum from same function drm/ast: Move cursor pageflip into helper drm/ast: Replace ast_cursor_move() with ast_cursor_show() drm/ast: Don't enable HW cursors twice during atomic update drm/ast: Add helper to hide cursor drm/ast: Keep cursor HW BOs mapped drm/ast: Managed cursor release drm/ast: Init cursors before creating modesetting structures drm/ast: Replace struct ast_crtc with struct drm_crtc drm/ast: Use managed mode-config init drm/ast: Initialize mode setting in ast_mode_config_init() drivers/gpu/drm/ast/Makefile | 3 +- drivers/gpu/drm/ast/ast_cursor.c | 289 +++++++++++++++++++++++++++ drivers/gpu/drm/ast/ast_drv.h | 19 +- drivers/gpu/drm/ast/ast_main.c | 35 +--- drivers/gpu/drm/ast/ast_mode.c | 322 ++++++------------------------- 5 files changed, 359 insertions(+), 309 deletions(-) create mode 100644 drivers/gpu/drm/ast/ast_cursor.c -- 2.27.0

3 19

[PATCH 00/59] Add support for Keem Bay DRM driver
by Anitha Chrisanthus 02 Jul '20

02 Jul '20

This is a new DRM driver for Intel's KeemBay SOC. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This driver is tested with the KMB EVM board which is the refernce baord for Keem Bay SOC. The SOC's display pipeline is as follows +--------------+ +---------+ +-----------------------+ |LCD controller| -> |Mipi DSI | -> |Mipi to HDMI Converter | +--------------+ +---------+ +-----------------------+ LCD controller and Mipi DSI transmitter are part of the SOC and mipi to HDMI converter is ADV7535 for KMB EVM board. The DRM driver is a basic KMS atomic modesetting display driver and has no 2D or 3D graphics.It calls into the ADV bridge driver at the connector level. Only 1080p resolution and single plane is supported at this time. The usecase is for debugging video and camera outputs. Since we are just starting the upstream process, the KMB EVM board is not in mainline and so Device tree changes are missing. Anitha Chrisanthus (52): drm/kmb: Add support for KeemBay Display drm/kmb: Added id to kmb_plane drm/kmb: Set correct values in the LAYERn_CFG register drm/kmb: Use biwise operators for register definitions drm/kmb: Updated kmb_plane_atomic_check drm/kmb: Initial check-in for Mipi DSI drm/kmb: Set OUT_FORMAT_CFG register drm/kmb: Added mipi_dsi_host initialization drm/kmb: Part 1 of Mipi Tx Initialization drm/kmb: Part 2 of Mipi Tx Initialization drm/kmb: Use correct mmio offset from data book drm/kmb: Part3 of Mipi Tx initialization drm/kmb: Part4 of Mipi Tx Initialization drm/kmb: Correct address offsets for mipi registers drm/kmb: Part5 of Mipi Tx Intitialization drm/kmb: Part6 of Mipi Tx Initialization drm/kmb: Part7 of Mipi Tx Initialization drm/kmb: Part8 of Mipi Tx Initialization drm/kmb: Added ioremap/iounmap for register access drm/kmb: Register IRQ for LCD drm/kmb: IRQ handlers for LCD and mipi dsi drm/kmb: Set hardcoded values to LCD_VSYNC_START drm/kmb: Additional register programming to update_plane drm/kmb: Add ADV7535 bridge drm/kmb: Display clock enable/disable drm/kmb: rebase to newer kernel version drm/kmb: minor name change to match device tree drm/kmb: Changed MMIO size drm/kmb: Defer Probe drm/kmb: call bridge init in the very beginning drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable drm/kmb: Mipi DPHY initialization changes drm/kmb: Fixed driver unload drm/kmb: Added LCD_TEST config drm/kmb: Changes for LCD to Mipi drm/kmb: Update LCD programming to match MIPI drm/kmb: Changed name of driver to kmb-drm drm/kmb: Mipi settings from input timings drm/kmb: Enable LCD interrupts drm/kmb: Enable LCD interrupts during modeset drm/kmb: Don’t inadvertantly disable LCD controller drm/kmb: SWAP R and B LCD Layer order drm/kmb: Disable ping pong mode drm/kmb: Do the layer initializations only once drm/kmb: disable the LCD layer in EOF irq handler drm/kmb: Initialize uninitialized variables drm/kmb: Added useful messages in LCD ISR kmb/drm: Prune unsupported modes drm/kmb: workaround for dma undeflow issue drm/kmb: Get System Clock from SCMI drm/kmb: work around for planar formats Edmund Dea (7): drm/kmb: Cleanup probe functions drm/kmb: Revert dsi_host back to a static variable drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg. drm/kmb: Remove declaration of irq_lcd/irq_mipi drm/kmb: Enable MIPI TX HS Test Pattern Generation drm/kmb: Write to LCD_LAYERn_CFG only once drm/kmb: Cleaned up code drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/kmb/Kconfig | 12 + drivers/gpu/drm/kmb/Makefile | 2 + drivers/gpu/drm/kmb/kmb_crtc.c | 243 +++++ drivers/gpu/drm/kmb/kmb_crtc.h | 61 ++ drivers/gpu/drm/kmb/kmb_drv.c | 828 +++++++++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 196 ++++ drivers/gpu/drm/kmb/kmb_dsi.c | 1950 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 390 ++++++++ drivers/gpu/drm/kmb/kmb_plane.c | 538 +++++++++++ drivers/gpu/drm/kmb/kmb_plane.h | 142 +++ drivers/gpu/drm/kmb/kmb_regs.h | 758 +++++++++++++++ 13 files changed, 5123 insertions(+) create mode 100644 drivers/gpu/drm/kmb/Kconfig create mode 100644 drivers/gpu/drm/kmb/Makefile create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h -- 2.7.4

4 62

[Bug 208411] New: GPU reset end with ret = -110
by bugzilla-daemon＠bugzilla.kernel.org 02 Jul '20

02 Jul '20

https://bugzilla.kernel.org/show_bug.cgi?id=208411 Bug ID: 208411 Summary: GPU reset end with ret = -110 Product: Drivers Version: 2.5 Kernel Version: Mainline 5.7.6 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: phil2sat(a)gmail.com Regression: No [ 1922.162071] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out! [ 1927.068795] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=13670, emitted seq=13672 [ 1927.068928] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process pid 0 thread pid 0 [ 1927.068934] amdgpu 0000:03:00.0: GPU reset begin! [ 1927.084510] [drm] [Link 0] WARNING MOD_HDCP_STATUS_DISPLAY_NOT_FOUND IN STATE HDCP_UNINITIALIZED STAY COUNT 0 [ 1927.225062] amdgpu 0000:03:00.0: GPU reset succeeded, trying to resume [ 1927.225189] [drm] PCIE GART of 1024M enabled (table at 0x000000F400900000). [ 1927.225215] [drm] VRAM is lost due to GPU reset! [ 1927.225367] [drm] PSP is resuming... [ 1927.225371] sos fw version = 0x110043. [ 1927.245401] [drm] reserve 0x400000 from 0xf41f800000 for PSP TMR [ 1927.545277] SMU is resuming... [ 1927.545337] SMU is resumed successfully! [ 1927.730819] [drm] kiq ring mec 2 pipe 1 q 0 [ 1927.877005] amdgpu 0000:03:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring sdma0 test failed (-110) [ 1927.877071] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <sdma_v4_0> failed -110 [ 1927.877127] amdgpu 0000:03:00.0: GPU reset(1) failed [ 1927.877143] amdgpu 0000:03:00.0: GPU reset end with ret = -110 -- You are receiving this mail because: You are watching the assignee of the bug.

1 0

[PATCH 0/4] DVFS support for dpu and dsi
by Rajendra Nayak 02 Jul '20

02 Jul '20

These patches add DVFS support for DPU and DSI. Where posted earlier as part of a series with multiple different drivers [1] I have split them into specific driver changes in order to avoid confusion on dependencies. Also added the corresponding device tree changes for sdm845 and sc7180 platforms. These patches have no other dependency and will need to be merged in via the MSM DRM tree. DT patches will need to land via the msm tree. [1] https://lkml.org/lkml/2020/6/15/535 Rajendra Nayak (4): drm/msm/dpu: Use OPP API to set clk/perf state drm/msm: dsi: Use OPP API to set clk/perf state arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains arm64: dts: sc7180: Add DSI and MDP OPP tables and power-domains arch/arm64/boot/dts/qcom/sc7180.dtsi | 49 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 59 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 26 +++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++ drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 58 ++++++++++++++++++++++++++ 8 files changed, 201 insertions(+), 4 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

2 8

[PATCH RESEND v1] drm/meson: viu: fix setting the OSD burst length in VIU_OSD1_FIFO_CTRL_STAT
by Martin Blumenstingl 02 Jul '20

02 Jul '20

The burst length is configured in VIU_OSD1_FIFO_CTRL_STAT[31] and VIU_OSD1_FIFO_CTRL_STAT[11:10]. The public S905D3 datasheet describes this as: - 0x0 = up to 24 per burst - 0x1 = up to 32 per burst - 0x2 = up to 48 per burst - 0x3 = up to 64 per burst - 0x4 = up to 96 per burst - 0x5 = up to 128 per burst The lower two bits map to VIU_OSD1_FIFO_CTRL_STAT[11:10] while the upper bit maps to VIU_OSD1_FIFO_CTRL_STAT[31]. Replace meson_viu_osd_burst_length_reg() with pre-defined macros which set these values. meson_viu_osd_burst_length_reg() always returned 0 (for the two used values: 32 and 64 at least) and thus incorrectly set the burst size to 24. Fixes: 147ae1cbaa1842 ("drm: meson: viu: use proper macros instead of magic constants") Signed-off-by: Martin Blumenstingl <martin.blumenstingl(a)googlemail.com> --- re-send of v1 [0] with no changes as I still noticed that this is sitting in my tree and I wasn't asked to change anything in v1. [0] https://patchwork.kernel.org/patch/11510045/ drivers/gpu/drm/meson/meson_registers.h | 6 ++++++ drivers/gpu/drm/meson/meson_viu.c | 11 ++--------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 8ea00546cd4e..049c4bfe2a3a 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -261,6 +261,12 @@ #define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12) #define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22) #define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24) +#define VIU_OSD_BURST_LENGTH_24 (0x0 << 31 | 0x0 << 10) +#define VIU_OSD_BURST_LENGTH_32 (0x0 << 31 | 0x1 << 10) +#define VIU_OSD_BURST_LENGTH_48 (0x0 << 31 | 0x2 << 10) +#define VIU_OSD_BURST_LENGTH_64 (0x0 << 31 | 0x3 << 10) +#define VIU_OSD_BURST_LENGTH_96 (0x1 << 31 | 0x0 << 10) +#define VIU_OSD_BURST_LENGTH_128 (0x1 << 31 | 0x1 << 10) #define VD1_IF0_GEN_REG 0x1a50 #define VD1_IF0_CANVAS0 0x1a51 diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index 304f8ff1339c..aede0c67a57f 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -411,13 +411,6 @@ void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv) priv->io_base + _REG(VIU_MISC_CTRL1)); } -static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length) -{ - uint32_t val = (((length & 0x80) % 24) / 12); - - return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31)); -} - void meson_viu_init(struct meson_drm *priv) { uint32_t reg; @@ -444,9 +437,9 @@ void meson_viu_init(struct meson_drm *priv) VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - reg |= meson_viu_osd_burst_length_reg(32); + reg |= VIU_OSD_BURST_LENGTH_32; else - reg |= meson_viu_osd_burst_length_reg(64); + reg |= VIU_OSD_BURST_LENGTH_64; writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); -- 2.27.0

2 2

[PATCH v3] drm/hisilicon: Use drmm_kzalloc() instead of devm_kzalloc()
by Tian Tao 02 Jul '20

02 Jul '20

using the new API drmm_kzalloc() instead of devm_kzalloc() v3: still fixed include statements sorted alphabetically. v2: keep the DRM include statements sorted alphabetically. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> Reviewed-by: Thomas Zimmermann <tzimmermann(a)suse.de> --- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index a6fd0c2..249c298 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -20,6 +20,7 @@ #include <drm/drm_fb_helper.h> #include <drm/drm_gem_vram_helper.h> #include <drm/drm_irq.h> +#include <drm/drm_managed.h> #include <drm/drm_print.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> @@ -267,7 +268,7 @@ static int hibmc_load(struct drm_device *dev) struct hibmc_drm_private *priv; int ret; - priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); + priv = drmm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) { DRM_ERROR("no memory to allocate for hibmc_drm_private\n"); return -ENOMEM; -- 2.7.4

2 1

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dri-devel July 2020