dri-devel August 2020

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[v7] dt-bindings: msm: disp: add yaml schemas for DPU and DSI bindings
by Krishna Manikandan 03 Aug '20

03 Aug '20

MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for the device tree bindings for the same. Signed-off-by: Krishna Manikandan <mkrishn(a)codeaurora.org> Changes in v2: - Changed dpu to DPU (Sam Ravnborg) - Fixed indentation issues (Sam Ravnborg) - Added empty line between different properties (Sam Ravnborg) - Replaced reference txt files with their corresponding yaml files (Sam Ravnborg) - Modified the file to use "|" only when it is necessary (Sam Ravnborg) Changes in v3: - Corrected the license used (Rob Herring) - Added maxItems for properties (Rob Herring) - Dropped generic descriptions (Rob Herring) - Added ranges property (Rob Herring) - Corrected the indendation (Rob Herring) - Added additionalProperties (Rob Herring) - Split dsi file into two, one for dsi controller and another one for dsi phy per target (Rob Herring) - Corrected description for pinctrl-names (Rob Herring) - Corrected the examples used in yaml file (Rob Herring) - Delete dsi.txt and dpu.txt (Rob Herring) Changes in v4: - Move schema up by one level (Rob Herring) - Add patternProperties for mdp node (Rob Herring) - Corrected description of some properties (Rob Herring) Changes in v5: - Correct the indentation (Rob Herring) - Remove unnecessary description from properties (Rob Herring) - Correct the number of interconnect entries (Rob Herring) - Add interconnect names for sc7180 (Rob Herring) - Add description for ports (Rob Herring) - Remove common properties (Rob Herring) - Add unevalutatedProperties (Rob Herring) - Reference existing dsi controller yaml in the common dsi controller file (Rob Herring) - Correct the description of clock names to include only the clocks that are required (Rob Herring) - Remove properties which are already covered under the common binding (Rob Herring) - Add dsi phy supply nodes which are required for sc7180 and sdm845 targets (Rob Herring) - Add type ref for syscon-sfpb (Rob Herring) Changes in v6: - Fixed errors during dt_binding_check (Rob Herring) - Add maxItems for phys and phys-names (Rob Herring) - Use unevaluatedProperties wherever required (Rob Herring) - Removed interrupt controller from required properties for dsi controller (Rob Herring) - Add constraints for dsi-phy reg-names based on the compatible phy version (Rob Herring) - Add constraints for dsi-phy supply nodes based on the compatible phy version (Rob Herring) Changes in v7: - Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring) - Modify the schema for data-lanes (Rob Herring) - Split the phy schema into separate schemas based on the phy version (Rob Herring) --- .../bindings/display/msm/dpu-sc7180.yaml | 236 +++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 216 ++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 ------------ .../display/msm/dsi-common-controller.yaml | 249 +++++++++++++++++++++ .../display/msm/dsi-controller-sc7180.yaml | 120 ++++++++++ .../display/msm/dsi-controller-sdm845.yaml | 120 ++++++++++ .../bindings/display/msm/dsi-phy-10nm.yaml | 62 +++++ .../bindings/display/msm/dsi-phy-14nm.yaml | 61 +++++ .../bindings/display/msm/dsi-phy-20nm.yaml | 66 ++++++ .../bindings/display/msm/dsi-phy-28nm.yaml | 62 +++++ .../bindings/display/msm/dsi-phy-sc7180.yaml | 80 +++++++ .../bindings/display/msm/dsi-phy-sdm845.yaml | 82 +++++++ .../devicetree/bindings/display/msm/dsi.txt | 246 -------------------- 13 files changed, 1354 insertions(+), 387 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file mode 100644 index 0000000..df70393 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + interconnects: + description: | + Interconnect path specifier for MDSS according to + Documentation/devicetree/bindings/interconnect/interconnect.txt. + An entry should contain 2 paths corresponding to 2 AXI ports representing + source and destination ports. + minItems: 1 + + interconnect-names: + description: | + MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier. + items: + - const: mdp0-mem + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +patternProperties: + "^mdp@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 6 + + clock-names: + description: | + Device clock names, must be in same order as clocks property. + The following clocks are required. + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. These + are described by the standard properties documented in files + mentioned below. + + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 4 + + assigned-clock-rates: + maxItems: 4 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-controller + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 { + compatible = "qcom,sc7180-mdss"; + reg = <0 0xae00000 0 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + clock-names = "iface", "ahb", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + + mdp: mdp@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file mode 100644 index 0000000..17395f6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DPU dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SDM845 target. + +properties: + compatible: + items: + - const: qcom,sdm845-mdss + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + description: | + Device clock names in the same order as mentioned in clocks property. + The required clocks are mentioned below. + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + maxItems: 2 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +patternProperties: + "^mdp@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sdm845-dpu + reg: + maxItems: 2 + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + maxItems: 4 + + clock-names: + description: | + Device clock names, must be in same order as clocks property. + The following clocks are required. + items: + - const: iface + - const: bus + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. These + are described by the standard properties documented in files + mentioned below. + + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + port@1: + type: object + description: DPU_INTF2 (DSI2) + + assigned-clocks: + maxItems: 2 + + assigned-clock-rates: + maxItems: 2 + + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-controller + - iommus + +additionalProperties: false + +examples: +- | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <2>; + #size-cells = <2>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt deleted file mode 100644 index 551ae26..0000000 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ /dev/null @@ -1,141 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates -sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" -- reg: physical base address and length of contoller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- iommus: phandle of iommu device node. -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. -- interconnects : interconnect path specifier for MDSS according to - Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be - 2 paths corresponding to 2 AXI ports. -- interconnect-names : MDSS will have 2 port names to differentiate between the - 2 interconnect paths defined with interconnect specifier. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region is required: - * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. These ports connect - to interfaces that are external to the DPU hardware, such as DSI, DP etc. - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, - <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; - - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <0 0 300000000 19200000>; - - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml b/Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml new file mode 100644 index 0000000..dec2253 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-common-controller.yaml @@ -0,0 +1,249 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-common-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI controller dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Common Device tree bindings for DSI controller. + +allOf: + - $ref: "../dsi-controller.yaml#" + +properties: + compatible: + items: + - const: qcom,mdss-dsi-ctrl + + clocks: + maxItems: 6 + + clock-names: + description: | + Device clock names in the same order as mentioned in clocks property. + + assigned-clocks: + description: Parents of "byte" and "pixel" for the given platform. + + assigned-clock-parents: + description: | + The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. + Details on clock bindings are mentioned in + Documentation/devicetree/bindings/clock/clock-bindings.txt. + + vdd-supply: + description: Phandle to vdd regulator device node. + + vddio-supply: + description: Phandle to vdd-io regulator device node. + + vdda-supply: + description: Phandle to vdda regulator device node. + + phys: + description: Phandle to DSI PHY device node. + maxItems: 1 + + phy-names: + description: Name of the corresponding PHY device. + maxItems: 1 + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2). + $ref: "/schemas/types.yaml#/definitions/phandle" + + # Optional Properties for dsi controller + qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the DSI transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + DSI link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the DSI link rate time. + This is an optional property. + default: 14000 + + qcom,dual-dsi-mode: + type: boolean + description: | + Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. + + qcom,master-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. + + qcom,sync-dual-dsi: + type: boolean + description: | + Boolean value indicating if the DSI controller is driving a + 2-DSI panel whose 2 links need receive command simultaneously. + + pinctrl-names: + description: The pin control state names. + items: + - const: default + - const: sleep + + pinctrl-0: + description: The default pinctrl state (active) + + pinctrl-1: + description: The sleep pinctrl state (suspend) + + ports: + type: object + description: | + Contains DSI controller input and output ports as children, each + containing one endpoint subnode as defined in + Documentation/devicetree/bindings/graph.txt and + Documentation/devicetree/bindings/media/video-interfaces.txt. + + properties: + port@0: + type: object + description: | + Input endpoints of the controller. + + properties: + reg: + const: 0 + + endpoint: + type: object + properties: + remote-endpoint: + description: | + For port@0, set to phandle of the connected panel/bridge's + input endpoint. For port@1, set to the MDP interface output. + See Documentation/devicetree/bindings/graph.txt for + device graph info. + + data-lanes: + description: | + This describes how the physical DSI data lanes are mapped + to the logical lanes on the given platform. The value contained in + index n describes what physical lane is mapped to the logical lane n + (DATAn, where n lies between 0 and 3). The clock lane position is fixed + and can't be changed. Hence, they aren't a part of the DT bindings. See + Documentation/devicetree/bindings/media/video-interfaces.txt for + more info on the data-lanes property. + + For example: + data-lanes = <3 0 1 2>; + + The above mapping describes that the logical data lane DATA0 is mapped + to the physical data lane DATA3, logical DATA1 to physical DATA0, + logic DATA2 to phys DATA1 and logic DATA3 to phys DATA2. There are + only a limited number of physical to logical mappings possible. + oneOf: + - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 + port@1: + type: object + description: | + Output endpoints of the controller. + properties: + reg: + const: 1 + + endpoint: + type: object + properties: + remote-endpoint: true + data-lanes: + oneOf: + - items: + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 0 + - items: + - const: 2 + - const: 3 + - const: 0 + - const: 1 + - items: + - const: 3 + - const: 0 + - const: 1 + - const: 2 + - items: + - const: 0 + - const: 3 + - const: 2 + - const: 1 + - items: + - const: 1 + - const: 0 + - const: 3 + - const: 2 + - items: + - const: 2 + - const: 1 + - const: 0 + - const: 3 + - items: + - const: 3 + - const: 2 + - const: 1 + - const: 0 +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml new file mode 100644 index 0000000..6f3e179 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-sc7180.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-controller-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI controller dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for DSI controller for SC7180 target. + +allOf: + - $ref: dsi-common-controller.yaml# + +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg: + maxItems: 1 + + reg-names: + const: dsi_ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 6 + + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + phys: + maxItems: 1 + + phy-names: + const: dsi + + ports: true + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml new file mode 100644 index 0000000..5dae89e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-sdm845.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-controller-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI controller dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for DSI controller for SDM845 target. + +allOf: + - $ref: dsi-common-controller.yaml# + +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg: + maxItems: 1 + + reg-names: + const: dsi_ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 6 + + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + phys: + maxItems: 1 + + phy-names: + const: dsi + + ports: true + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml new file mode 100644 index 0000000..3c0a4f6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 10nm PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Common Device tree bindings for DSI 10nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-10nm + - const: qcom,dsi-phy-10nm-8998 + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + vdds-supply: + description: | + Phandle to vdds regulator device node. + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vdds-supply +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml new file mode 100644 index 0000000..9004339 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 14nm PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Common Device tree bindings for DSI 14nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-14nm + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + + vcca-supply: + description: | + Phandle to vcca regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vcca-supply +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml new file mode 100644 index 0000000..30ec182 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 20nm PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Common Device tree bindings for DSI 20nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-20nm + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + + vcca-supply: + description: | + Phandle to vcca regulator device node. + + vddio-supply: + description: | + Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - vddio-supply + - vcca-supply +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml new file mode 100644 index 0000000..42bf0d0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI 28nm PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Common Device tree bindings for DSI 28nm PHY. + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-28nm-hpm + - const: qcom,dsi-phy-28nm-lp + - const: qcom,dsi-phy-28nm-8960 + + reg-names: + items: + - const: dsi_pll + - const: dsi_phy + - const: dsi_phy_regulator + + clock-cells: + description: | + The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + description: | + The following clocks are required. + items: + - const: iface + - const: ref + + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: | + Boolean value indicating if the LDO mode PHY regulator is wanted (optional). + + vddio-supply: + description: | + Phandle to vdd-io regulator device node. + +required: + - compatible + - reg + - reg-names + - clocks + - vddio-supply +... diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml new file mode 100644 index 0000000..02f87bd --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-sc7180.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for DSI PHY for SC7180 target. + +allOf: + - $ref: dsi-phy-10nm.yaml# + +properties: + compatible: + const: qcom,dsi-phy-10nm + + reg: + maxItems: 3 + + reg-names: + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + + dsi_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + vdds-supply = <&vdda_mipi_dsi0_pll>; + #clock-cells = <1>; + #phy-cells = <0>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml new file mode 100644 index 0000000..8214235 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-sdm845.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Description of Qualcomm Display DSI PHY dt properties. + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for DSI PHY for SDM845 target. + +allOf: + - $ref: dsi-phy-10nm.yaml# + +properties: + compatible: + const: qcom,dsi-phy-10nm + + reg: + maxItems: 3 + + reg-names: + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + mdss: mdss { + #address-cells = <2>; + #size-cells = <2>; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vdda_mipi_dsi0_pll>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + }; + }; +... + diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt deleted file mode 100644 index af95586..0000000 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ /dev/null @@ -1,246 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon DSI output - -DSI Controller: -Required properties: -- compatible: - * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller -- reg-names: The names of register regions. The following regions are required: - * "dsi_ctrl" -- interrupts: The interrupt signal from the DSI block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. -- clock-names: the following clocks are required: - * "mdp_core" - * "iface" - * "bus" - * "core_mmss" - * "byte" - * "pixel" - * "core" - For DSIv2, we need an additional clock: - * "src" - For DSI6G v2.0 onwards, we need also need the clock: - * "byte_intf" -- assigned-clocks: Parents of "byte" and "pixel" for the given platform. -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided - by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node -- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node -- phys: phandle to DSI PHY device node -- phy-names: the name of the corresponding PHY device -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains - an endpoint subnode as defined in [2] and [3]. - -Optional properties: -- panel@0: Node of panel connected to this DSI controller. - See files in [4] for each supported panel. -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is - driving a panel which needs 2 DSI links. -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving - the master link of the 2-DSI panel. -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is - driving a 2-DSI panel whose 2 links need receive command simultaneously. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-n: the "sleep" pinctrl state -- ports: contains DSI controller input and output ports as children, each - containing one endpoint subnode. - - DSI Endpoint properties: - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's - input endpoint. For port@1, set to the MDP interface output. See [2] for - device graph info. - - - data-lanes: this describes how the physical DSI data lanes are mapped - to the logical lanes on the given platform. The value contained in - index n describes what physical lane is mapped to the logical lane n - (DATAn, where n lies between 0 and 3). The clock lane position is fixed - and can't be changed. Hence, they aren't a part of the DT bindings. See - [3] for more info on the data-lanes property. - - For example: - - data-lanes = <3 0 1 2>; - - The above mapping describes that the logical data lane DATA0 is mapped to - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 - to phys DATA1 and logic DATA3 to phys DATA2. - - There are only a limited number of physical to logical mappings possible: - <0 1 2 3> - <1 2 3 0> - <2 3 0 1> - <3 0 1 2> - <0 3 2 1> - <1 0 3 2> - <2 1 0 3> - <3 2 1 0> - -DSI PHY: -Required properties: -- compatible: Could be the following - * "qcom,dsi-phy-28nm-hpm" - * "qcom,dsi-phy-28nm-lp" - * "qcom,dsi-phy-20nm" - * "qcom,dsi-phy-28nm-8960" - * "qcom,dsi-phy-14nm" - * "qcom,dsi-phy-10nm" - * "qcom,dsi-phy-10nm-8998" -- reg: Physical base address and length of the registers of PLL, PHY. Some - revisions require the PHY regulator base address, whereas others require the - PHY lane base address. See below for each PHY revision. -- reg-names: The names of register regions. The following regions are required: - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - For DSI 14nm and 10nm PHYs: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_lane" -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating - 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. See [1] for details on clock bindings. -- clock-names: the following clocks are required: - * "iface" - * "ref" (only required for new DTS files/entries) - For 28nm HPM/LP, 28nm 8960 PHYs: -- vddio-supply: phandle to vdd-io regulator device node - For 20nm PHY: -- vddio-supply: phandle to vdd-io regulator device node -- vcca-supply: phandle to vcca regulator device node - For 14nm PHY: -- vcca-supply: phandle to vcca regulator device node - For 10nm PHY: -- vdds-supply: phandle to vdds regulator device node - -Optional properties: -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY - regulator is wanted. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split is enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/graph.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/display/panel/ - -Example: - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - qcom,dsi-host-index = <0>; - interrupt-parent = <&mdp>; - interrupts = <4 0>; - reg-names = "dsi_ctrl"; - reg = <0xfd922800 0x200>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "bus", - "byte", - "core", - "core_mmss", - "iface", - "mdp_core", - "pixel"; - clocks = - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_PCLK0_CLK>; - - assigned-clocks = - <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = - <&dsi_phy0 0>, - <&dsi_phy0 1>; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - phys = <&dsi_phy0>; - phy-names ="dsi-phy"; - - qcom,dual-dsi-mode; - qcom,master-dsi; - qcom,sync-dual-dsi; - - qcom,mdss-mdp-transfer-time-us = <12000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dsi_active>; - pinctrl-1 = <&dsi_suspend>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - qcom,dsi-phy-index = <0>; - reg-names = - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>; - clock-names = "iface"; - clocks = <&mmcc MDSS_AHB_CLK>; - #clock-cells = <1>; - vddio-supply = <&pma8084_l12>; - - qcom,dsi-phy-regulator-ldo-mode; - }; -- 1.9.1

1 0

[RFC PATCH 00/17] Drop uses of pci_read_config_*() return value
by Saheed O. Bolarinwa 02 Aug '20

02 Aug '20

The return value of pci_read_config_*() may not indicate a device error. However, the value read by these functions is more likely to indicate this kind of error. This presents two overlapping ways of reporting errors and complicates error checking. It is possible to move to one single way of checking for error if the dependencies on the return value of these functions are removed, then it can later be made to return void. Remove all uses of the return value of pci_read_config_*(). Check the actual value read for ~0. In this case, ~0 is an invalid value thus it indicates some kind of error. In some cases it madkes sence to make the calling function return void without causing any bug. Future callers can use the value obtained from these functions for validation. This case pertain to cs5536_read() and edac_pci_read_dword() MERGE: There is no dependency. Merge individually Saheed O. Bolarinwa (17): ata: Drop uses of pci_read_config_*() return value atm: Drop uses of pci_read_config_*() return value bcma: Drop uses of pci_read_config_*() return value hwrng: Drop uses of pci_read_config_*() return value dmaengine: ioat: Drop uses of pci_read_config_*() return value edac: Drop uses of pci_read_config_*() return value fpga: altera-cvp: Drop uses of pci_read_config_*() return value gpio: Drop uses of pci_read_config_*() return value drm/i915/vga: Drop uses of pci_read_config_*() return value hwmon: Drop uses of pci_read_config_*() return value intel_th: pci: Drop uses of pci_read_config_*() return value i2c: Drop uses of pci_read_config_*() return value ide: Drop uses of pci_read_config_*() return value IB: Drop uses of pci_read_config_*() return value iommu/vt-d: Drop uses of pci_read_config_*() return value mtd: Drop uses of pci_read_config_*() return value net: Drop uses of pci_read_config_*() return value drivers/ata/pata_cs5536.c | 6 +-- drivers/ata/pata_rz1000.c | 3 +- drivers/atm/eni.c | 3 +- drivers/atm/he.c | 12 +++-- drivers/atm/idt77252.c | 9 ++-- drivers/atm/iphase.c | 46 ++++++++++--------- drivers/atm/lanai.c | 4 +- drivers/atm/nicstar.c | 3 +- drivers/atm/zatm.c | 9 ++-- drivers/bcma/host_pci.c | 6 ++- drivers/char/hw_random/amd-rng.c | 6 +-- drivers/dma/ioat/dma.c | 6 +-- drivers/edac/amd64_edac.c | 8 ++-- drivers/edac/amd8111_edac.c | 16 ++----- drivers/edac/amd8131_edac.c | 6 +-- drivers/edac/i82443bxgx_edac.c | 3 +- drivers/edac/sb_edac.c | 12 +++-- drivers/edac/skx_common.c | 18 +++++--- drivers/fpga/altera-cvp.c | 8 ++-- drivers/gpio/gpio-amd8111.c | 7 ++- drivers/gpio/gpio-rdc321x.c | 21 +++++---- drivers/gpu/drm/i915/display/intel_vga.c | 3 +- drivers/hwmon/i5k_amb.c | 12 +++-- drivers/hwmon/vt8231.c | 8 ++-- drivers/hwtracing/intel_th/pci.c | 12 ++--- drivers/i2c/busses/i2c-ali15x3.c | 6 ++- drivers/i2c/busses/i2c-elektor.c | 3 +- drivers/i2c/busses/i2c-nforce2.c | 4 +- drivers/i2c/busses/i2c-sis5595.c | 17 ++++--- drivers/i2c/busses/i2c-sis630.c | 7 +-- drivers/i2c/busses/i2c-viapro.c | 11 +++-- drivers/ide/cs5536.c | 6 +-- drivers/ide/rz1000.c | 3 +- drivers/ide/setup-pci.c | 26 +++++++---- drivers/infiniband/hw/hfi1/pcie.c | 38 +++++++-------- drivers/infiniband/hw/mthca/mthca_reset.c | 19 ++++---- drivers/iommu/intel/iommu.c | 6 ++- drivers/mtd/maps/ichxrom.c | 4 +- drivers/net/can/peak_canfd/peak_pciefd_main.c | 6 ++- drivers/net/can/sja1000/peak_pci.c | 6 ++- drivers/net/ethernet/agere/et131x.c | 11 +++-- .../ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 5 +- .../cavium/liquidio/cn23xx_pf_device.c | 4 +- drivers/net/ethernet/marvell/sky2.c | 5 +- drivers/net/ethernet/mellanox/mlx4/catas.c | 7 +-- drivers/net/ethernet/mellanox/mlx4/reset.c | 10 ++-- .../net/ethernet/myricom/myri10ge/myri10ge.c | 4 +- drivers/net/wan/farsync.c | 5 +- .../broadcom/brcm80211/brcmfmac/pcie.c | 4 +- .../net/wireless/intel/iwlwifi/pcie/trans.c | 15 ++++-- 50 files changed, 270 insertions(+), 209 deletions(-) -- 2.18.4

5 7

[PATCH] drm/i915: Fix wrong return value
by Tianjia Zhang 02 Aug '20

02 Aug '20

In function i915_active_acquire_preallocate_barrier(), not all paths have the return value set correctly, and in case of memory allocation failure, a negative error code should be returned. Cc: Chris Wilson <chris(a)chris-wilson.co.uk> Signed-off-by: Tianjia Zhang <tianjia.zhang(a)linux.alibaba.com> --- drivers/gpu/drm/i915/i915_active.c | 4 ++-- drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c index d960d0be5bd2..cc017e3cc9c5 100644 --- a/drivers/gpu/drm/i915/i915_active.c +++ b/drivers/gpu/drm/i915/i915_active.c @@ -758,7 +758,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref, intel_engine_mask_t tmp, mask = engine->mask; struct llist_node *first = NULL, *last = NULL; struct intel_gt *gt = engine->gt; - int err; + int err = 0; GEM_BUG_ON(i915_active_is_idle(ref)); @@ -782,7 +782,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref, if (!node) { node = kmem_cache_alloc(global.slab_cache, GFP_KERNEL); if (!node) { - err = ENOMEM; + err = -ENOMEM; goto unwind; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 6014e8dfcbb1..dda801a87b8a 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -326,7 +326,7 @@ static int __igt_breadcrumbs_smoketest(void *arg) if (!wait) { i915_sw_fence_commit(submit); heap_fence_put(submit); - err = ENOMEM; + err = -ENOMEM; break; } -- 2.26.2

3 3

[PATCH] drm/i915: Fix wrong return value in intel_atomic_check()
by Tianjia Zhang 02 Aug '20

02 Aug '20

In the case of calling check_digital_port_conflicts() failed, a negative error code -EINVAL should be returned. Fixes: bf5da83e4bd80 ("drm/i915: Move check_digital_port_conflicts() earier") Cc: Ville Syrjälä <ville.syrjala(a)linux.intel.com> Signed-off-by: Tianjia Zhang <tianjia.zhang(a)linux.alibaba.com> --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 26996e1839e2..9f3a7ef58aba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14872,7 +14872,7 @@ static int intel_atomic_check(struct drm_device *dev, if (any_ms && !check_digital_port_conflicts(state)) { drm_dbg_kms(&dev_priv->drm, "rejecting conflicting digital port configuration\n"); - ret = EINVAL; + ret = -EINVAL; goto fail; } -- 2.26.2

1 0

[PATCH 1/3] dt-bindings: Add vendor prefix for Chefree
by Marek Vasut 02 Aug '20

02 Aug '20

The Chefree Technology Corp. is an LCD panel manufacturer. Signed-off-by: Marek Vasut <marex(a)denx.de> To: dri-devel(a)lists.freedesktop.org Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: devicetree(a)vger.kernel.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5b1343a8d198..7204e069d498 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -197,6 +197,8 @@ patternProperties: description: Ceva, Inc. "^checkpoint,.*": description: Check Point Software Technologies Ltd. + "^chefree,.*": + description: Chefree Technology Corp. "^chipidea,.*": description: Chipidea, Inc "^chipone,.*": -- 2.27.0

3 5

[PATCH] drm/syncobj: Tune down unordered timeline DRM_ERROR
by Daniel Vetter 01 Aug '20

01 Aug '20

Userspace can provoke this, we generally don't allow userspace to spam dmesg. Tune it down to debug. Unfortunately we don't have easy access to the drm_device here (not at all without changing a few things), so leave it as old style dmesg output for now. References: https://patchwork.freedesktop.org/series/80146/ Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Chris Wilson <chris(a)chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin(a)intel.com> Cc: "Christian König" <christian.koenig(a)amd.com> --- drivers/gpu/drm/drm_syncobj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index 3bf73971daf3..6e74e6745eca 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -297,7 +297,7 @@ void drm_syncobj_add_point(struct drm_syncobj *syncobj, prev = drm_syncobj_fence_get(syncobj); /* You are adding an unorder point to timeline, which could cause payload returned from query_ioctl is 0! */ if (prev && prev->seqno >= point) - DRM_ERROR("You are adding an unorder point to timeline!\n"); + DRM_DEBUG("You are adding an unorder point to timeline!\n"); dma_fence_chain_init(chain, prev, fence, point); rcu_assign_pointer(syncobj->fence, &chain->base); -- 2.27.0

3 2

[Bug 208489] New: amdgpu: kernel oops when overclocking Vega M GPU (i7-8809G)
by bugzilla-daemon＠bugzilla.kernel.org 01 Aug '20

01 Aug '20

https://bugzilla.kernel.org/show_bug.cgi?id=208489 Bug ID: 208489 Summary: amdgpu: kernel oops when overclocking Vega M GPU (i7-8809G) Product: Drivers Version: 2.5 Kernel Version: 5.7.7 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: crab2313(a)gmail.com Regression: No Created attachment 290165 --> https://bugzilla.kernel.org/attachment.cgi?id=290165&action=edit full kernel dmesg CPU: Intel(R) Core(TM) i7-8809G CPU @ 3.10GHz Intel Hades Canyon NUC Kit ❯ cat /sys/bus/pci/drivers/amdgpu/0000:01:00.0/pp_od_clk_voltage OD_SCLK: 0: 225MHz 750mV 1: 400MHz 750mV 2: 535MHz 750mV 3: 715MHz 750mV 4: 960MHz 750mV 5: 1080MHz 750mV 6: 1140MHz 750mV 7: 1250MHz 750mV OD_MCLK: 0: 300MHz 750mV 1: 500MHz 750mV 2: 800MHz 800mV OD_RANGE: SCLK: 225MHz 1600MHz MCLK: 300MHz 1000MHz VDDC: 750mV 750mV After doing this: #!/bin/sh sudo sh -c "echo 's 7 1250 750' > /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/pp_od_clk_voltage" sudo sh -c "echo 'c' > /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/pp_od_clk_voltage" kernel oops with the dmesg. [ 4.932714] Bluetooth: RFCOMM TTY layer initialized [ 4.932722] Bluetooth: RFCOMM socket layer initialized [ 4.932725] Bluetooth: RFCOMM ver 1.11 [ 9.120298] rfkill: input handler enabled [ 9.922018] fuse: init (API version 7.31) [ 10.492078] rfkill: input handler disabled [ 12.680512] wlp6s0: authenticate with 50:d2:f5:f1:12:ed [ 12.690803] wlp6s0: send auth to 50:d2:f5:f1:12:ed (try 1/3) [ 12.728470] wlp6s0: authenticated [ 12.728864] wlp6s0: associate with 50:d2:f5:f1:12:ed (try 1/3) [ 12.759696] wlp6s0: RX AssocResp from 50:d2:f5:f1:12:ed (capab=0x31 status=0 aid=2) [ 12.762966] wlp6s0: associated [ 13.100624] IPv6: ADDRCONF(NETDEV_CHANGE): wlp6s0: link becomes ready [ 606.958453] BUG: unable to handle page fault for address: ffff9032a4c849a4 [ 606.958455] #PF: supervisor read access in kernel mode [ 606.958456] #PF: error_code(0x0000) - not-present page [ 606.958457] PGD 173c01067 P4D 173c01067 PUD 0 [ 606.958459] Oops: 0000 [#1] PREEMPT SMP PTI [ 606.958460] CPU: 7 PID: 2337 Comm: bash Not tainted 5.7.7-zen1-1-zen #1 [ 606.958461] Hardware name: Intel Corporation NUC8i7HVK/NUC8i7HVB, BIOS HNKBLi70.86A.0054.2019.0214.1350 02/14/2019 [ 606.958528] RIP: 0010:phm_find_closest_vddci+0x3b/0x60 [amdgpu] [ 606.958529] Code: c0 eb 09 48 83 c0 01 48 39 d0 74 19 44 0f b7 44 c3 0c 89 c5 66 41 39 f0 72 e9 44 89 c0 5b 5d c3 bd ff ff ff ff 0f 1f 44 00 00 <44> 0f b7 44 eb 0c 5b 5d 44 89 c0 c3 48 c7 c6 f0 c1 96 c0 48 c7 c7 [ 606.958530] RSP: 0018:ffffa3ecc18ff948 EFLAGS: 00010246 [ 606.958531] RAX: 00000000000002ee RBX: ffff902aa4c849a0 RCX: 0000000000000008 [ 606.958532] RDX: 0000000000000000 RSI: 0000000000000226 RDI: ffff902aa4c849a0 [ 606.958532] RBP: 00000000ffffffff R08: ffffa3ecc18ff9d4 R09: 0000000000000029 [ 606.958533] R10: 000000000000e401 R11: 0000000000000000 R12: ffff902aa6861600 [ 606.958534] R13: ffff902aa4c84000 R14: ffff902aa4c85301 R15: ffffa3ecc18ff9d4 [ 606.958534] FS: 00007fe8233c0b80(0000) GS:ffff902aaedc0000(0000) knlGS:0000000000000000 [ 606.958535] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 606.958536] CR2: ffff9032a4c849a4 CR3: 0000000467468005 CR4: 00000000003606e0 [ 606.958536] Call Trace: [ 606.958587] vegam_get_dependency_volt_by_clk.isra.0+0x8e/0x220 [amdgpu] [ 606.958637] vegam_populate_all_graphic_levels+0x26a/0x960 [amdgpu] [ 606.958686] smu7_set_power_state_tasks+0x77c/0x12b0 [amdgpu] [ 606.958734] phm_set_power_state+0x5a/0x80 [amdgpu] [ 606.958784] psm_adjust_power_state_dynamic+0xca/0x1d0 [amdgpu] [ 606.958831] hwmgr_handle_task+0x49/0xf0 [amdgpu] [ 606.958882] pp_dpm_dispatch_tasks+0x3a/0x60 [amdgpu] [ 606.958915] amdgpu_set_pp_od_clk_voltage+0x3cb/0x490 [amdgpu] [ 606.958921] kernfs_fop_write+0xce/0x1b0 [ 606.958923] vfs_write+0x10a/0x420 [ 606.958925] __x64_sys_write+0x6d/0xf0 [ 606.958926] do_syscall_64+0x4e/0x160 [ 606.958928] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 606.958930] RIP: 0033:0x7fe823523b57 [ 606.958931] Code: 0c 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b7 0f 1f 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 51 c3 48 83 ec 28 48 89 54 24 18 48 89 74 24 [ 606.958931] RSP: 002b:00007ffea3ba5e88 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 [ 606.958932] RAX: ffffffffffffffda RBX: 0000000000000002 RCX: 00007fe823523b57 [ 606.958933] RDX: 0000000000000002 RSI: 00005648e5dda620 RDI: 0000000000000001 [ 606.958934] RBP: 00005648e5dda620 R08: 000000000000000a R09: 0000000000000001 [ 606.958934] R10: 00005648e5d20870 R11: 0000000000000246 R12: 0000000000000002 [ 606.958935] R13: 00007fe8235f4500 R14: 0000000000000002 R15: 00007fe8235f4700 [ 606.958936] Modules linked in: ccm fuse rfcomm xt_CHECKSUM xt_MASQUERADE xt_conntrack cmac algif_hash ipt_REJECT nf_reject_ipv4 algif_skcipher af_alg xt_tcpudp ip6table_mangle ip6table_nat iptable_mangle iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 libcrc32c ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter tun mousedev input_leds hid_generic joydev usbhid hid xpad ff_memless bridge stp llc bnep msr intel_rapl_msr intel_rapl_common x86_pkg_temp_thermal intel_powerclamp coretemp iwlmvm kvm_intel snd_hda_codec_realtek kvm snd_hda_codec_generic iTCO_wdt mac80211 iTCO_vendor_support irqbypass 8250_dw ledtrig_audio snd_hda_codec_hdmi mei_hdcp nls_iso8859_1 tps6598x crct10dif_pclmul typec libarc4 wmi_bmof crc32_pclmul nls_cp437 ghash_clmulni_intel intel_wmi_thunderbolt vfat aesni_intel snd_hda_intel btusb fat btrtl snd_intel_dspcfg iwlwifi btbcm crypto_simd cryptd glue_helper snd_hda_codec intel_cstate btintel intel_uncore snd_hda_core intel_rapl_perf pcspkr [ 606.958955] e1000e i2c_i801 cfg80211 snd_hwdep bluetooth igb snd_pcm mei_me ecdh_generic intel_lpss_pci rfkill dca snd_timer ecc intel_lpss mei idma64 intel_pch_thermal snd tpm_crb soundcore wmi tpm_tis i2c_multi_instantiate tpm_tis_core evdev tpm rng_core mac_hid tcp_bbr sch_cake sg crypto_user ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 sdhci_pci cqhci xhci_pci sdhci crc32c_intel xhci_hcd mmc_core amdgpu gpu_sched i2c_algo_bit ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops cec rc_core drm agpgart [ 606.958968] CR2: ffff9032a4c849a4 [ 606.958970] ---[ end trace d28ac9f0a176b773 ]--- [ 606.959020] RIP: 0010:phm_find_closest_vddci+0x3b/0x60 [amdgpu] [ 606.959021] Code: c0 eb 09 48 83 c0 01 48 39 d0 74 19 44 0f b7 44 c3 0c 89 c5 66 41 39 f0 72 e9 44 89 c0 5b 5d c3 bd ff ff ff ff 0f 1f 44 00 00 <44> 0f b7 44 eb 0c 5b 5d 44 89 c0 c3 48 c7 c6 f0 c1 96 c0 48 c7 c7 [ 606.959022] RSP: 0018:ffffa3ecc18ff948 EFLAGS: 00010246 [ 606.959023] RAX: 00000000000002ee RBX: ffff902aa4c849a0 RCX: 0000000000000008 [ 606.959023] RDX: 0000000000000000 RSI: 0000000000000226 RDI: ffff902aa4c849a0 [ 606.959024] RBP: 00000000ffffffff R08: ffffa3ecc18ff9d4 R09: 0000000000000029 [ 606.959024] R10: 000000000000e401 R11: 0000000000000000 R12: ffff902aa6861600 [ 606.959025] R13: ffff902aa4c84000 R14: ffff902aa4c85301 R15: ffffa3ecc18ff9d4 [ 606.959026] FS: 00007fe8233c0b80(0000) GS:ffff902aaedc0000(0000) knlGS:0000000000000000 [ 606.959027] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 606.959027] CR2: ffff9032a4c849a4 CR3: 0000000467468005 CR4: 00000000003606e0 -- You are receiving this mail because: You are watching the assignee of the bug.

1 1

[PATCH 0/2] Fix st7703 panel initialization failures
by Ondrej Jirman 01 Aug '20

01 Aug '20

When extending the driver for xbd599 panel support I tried to do minimal changes and keep the existing initialization timing. It turned out that it's not good enough and the existing init sequence is too aggressive and doesn't follow the specification. On PinePhone panel is being powered down/up during suspend/resume and with current timings this frequently leads to corrupted display. This patch series fixes the problems. The issue was reported by Samuel Holland. Relevant screenshots from the datasheet: Power on timing: https://megous.com/dl/tmp/35b72e674ce0ca27.png Power off timing: https://megous.com/dl/tmp/dea195517106ff17.png More optimal reset on poweron: https://megous.com/dl/tmp/a9e5caf14e1b0dc6.png Less optimal reset on poweron: https://megous.com/dl/tmp/246761039283c4cf.png Datasheet: https://megous.com/dl/tmp/ST7703_DS_v01_20160128.pdf Please take a look. thank you and regards, Ondrej Jirman Ondrej Jirman (2): drm/panel: st7703: Make the sleep exit timing match the spec drm/panel: st7703: Fix the power up sequence of the panel drivers/gpu/drm/panel/panel-sitronix-st7703.c | 29 ++++++++++--------- 1 file changed, 15 insertions(+), 14 deletions(-) -- 2.27.0

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Re: [PATCH] vgaarb: mark vga_tryget static
by daniel＠ffwll.ch 01 Aug '20

01 Aug '20

On Sat, Aug 01, 2020 at 08:17:13AM +0200, Christoph Hellwig wrote: > This symbols isn't used anywhere outside of vgaarb.c. > > Signed-off-by: Christoph Hellwig <hch(a)lst.de> Nice catch, patch queued up for 5.9. Thanks, Daniel > --- > drivers/gpu/vga/vgaarb.c | 3 +-- > include/linux/vgaarb.h | 6 ------ > 2 files changed, 1 insertion(+), 8 deletions(-) > > diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c > index f2f3ef8af2710f..5180c5687ee530 100644 > --- a/drivers/gpu/vga/vgaarb.c > +++ b/drivers/gpu/vga/vgaarb.c > @@ -529,7 +529,7 @@ EXPORT_SYMBOL(vga_get); > * > * 0 on success, negative error code on failure. > */ > -int vga_tryget(struct pci_dev *pdev, unsigned int rsrc) > +static int vga_tryget(struct pci_dev *pdev, unsigned int rsrc) > { > struct vga_device *vgadev; > unsigned long flags; > @@ -554,7 +554,6 @@ int vga_tryget(struct pci_dev *pdev, unsigned int rsrc) > spin_unlock_irqrestore(&vga_lock, flags); > return rc; > } > -EXPORT_SYMBOL(vga_tryget); > > /** > * vga_put - release lock on legacy VGA resources > diff --git a/include/linux/vgaarb.h b/include/linux/vgaarb.h > index 553b34c8b5f700..977caf96c8d2a3 100644 > --- a/include/linux/vgaarb.h > +++ b/include/linux/vgaarb.h > @@ -109,12 +109,6 @@ static inline int vga_get_uninterruptible(struct pci_dev *pdev, > return vga_get(pdev, rsrc, 0); > } > > -#if defined(CONFIG_VGA_ARB) > -extern int vga_tryget(struct pci_dev *pdev, unsigned int rsrc); > -#else > -static inline int vga_tryget(struct pci_dev *pdev, unsigned int rsrc) { return 0; } > -#endif > - > #if defined(CONFIG_VGA_ARB) > extern void vga_put(struct pci_dev *pdev, unsigned int rsrc); > #else > -- > 2.27.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

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[PATCH v2 1/1] drm: xlnx: zynqmp: Use switch - case for link rate downshift
by Hyun Kwon 01 Aug '20

01 Aug '20

Use switch - case to downshift from the current link rate. It's a small loop now, so fine to be replaced with switch - case. With a loop, it is confusing and hard to follow as reported below. The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem" from Jul 7, 2018, leads to the following static checker warning: drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure() error: iterator underflow 'bws' (-1)-2 Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com> Signed-off-by: Hyun Kwon <hyun.kwon(a)xilinx.com> --- v2 - Convert the for loop into switch - case --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index b735072..5d6adeaa 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -567,34 +567,37 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, u8 current_bw) { int max_rate = dp->link_config.max_rate; - u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; + u8 bw_code; u8 max_lanes = dp->link_config.max_lanes; u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate); u8 bpp = dp->config.bpp; u8 lane_cnt; - s8 i; - if (current_bw == DP_LINK_BW_1_62) { + /* Downshift from current one */ + switch (current_bw) { + case DP_LINK_BW_5_4: + bw_code = DP_LINK_BW_2_7; + break; + case DP_LINK_BW_2_7: + bw_code = DP_LINK_BW_1_62; + break; + case DP_LINK_BW_1_62: dev_err(dp->dev, "can't downshift. already lowest link rate\n"); return -EINVAL; - } - - for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) { - if (current_bw && bws[i] >= current_bw) - continue; - - if (bws[i] <= max_link_rate_code) - break; + default: + /* If not given, start with max supported */ + bw_code = max_link_rate_code; + break; } for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { int bw; u32 rate; - bw = drm_dp_bw_code_to_link_rate(bws[i]); + bw = drm_dp_bw_code_to_link_rate(bw_code); rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp); if (pclock <= rate) { - dp->mode.bw_code = bws[i]; + dp->mode.bw_code = bw_code; dp->mode.lane_cnt = lane_cnt; dp->mode.pclock = pclock; return dp->mode.bw_code; -- 2.7.4

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dri-devel August 2020