dri-devel January 2021

dri-devel@lists.freedesktop.org

322 participants
737 discussions

[PATCH 25/31] memory: tegra30: convert to use devm_pm_opp_* API
by Yangtao Li 04 Jan '21

04 Jan '21

Use devm_pm_opp_* API to simplify code. Signed-off-by: Yangtao Li <tiny.windzz(a)gmail.com> --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 44ac155936aa..a93d8c3629fe 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1483,31 +1483,31 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc) static int tegra_emc_opp_table_init(struct tegra_emc *emc) { u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); - struct opp_table *clk_opp_table, *hw_opp_table; + struct opp_table *opp_table; int err; - clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); - err = PTR_ERR_OR_ZERO(clk_opp_table); + opp_table = devm_pm_opp_set_clkname(emc->dev, NULL); + err = PTR_ERR_OR_ZERO(opp_table); if (err) { dev_err(emc->dev, "failed to set OPP clk: %d\n", err); return err; } - hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); - err = PTR_ERR_OR_ZERO(hw_opp_table); + opp_table = devm_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(opp_table); if (err) { dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); - goto put_clk_table; + return err; } - err = dev_pm_opp_of_add_table(emc->dev); + err = devm_pm_opp_of_add_table(emc->dev); if (err) { if (err == -ENODEV) dev_err(emc->dev, "OPP table not found, please update your device tree\n"); else dev_err(emc->dev, "failed to add OPP table: %d\n", err); - goto put_hw_table; + return err; } dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", @@ -1515,19 +1515,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) /* first dummy rate-set initializes voltage state */ err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); - if (err) { + if (err) dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); - goto remove_table; - } - - return 0; - -remove_table: - dev_pm_opp_of_remove_table(emc->dev); -put_hw_table: - dev_pm_opp_put_supported_hw(hw_opp_table); -put_clk_table: - dev_pm_opp_put_clkname(clk_opp_table); return err; } -- 2.25.1

2 1

[PATCH] drm/amd/display: Fix unused variable warning
by Arnd Bergmann 04 Jan '21

04 Jan '21

From: Arnd Bergmann <arnd(a)arndb.de> Some of the newly added code is hidden inside of #ifdef blocks, but one variable is unused when debugfs is disabled: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8370:8: error: unused variable 'configure_crc' [-Werror,-Wunused-variable] Change the #ifdef to an if(IS_ENABLED()) check to fix the warning and avoid adding more #ifdefs. Fixes: c920888c604d ("drm/amd/display: Expose new CRC window property") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 42b0fdb72e7b..5071b55ad0f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8379,8 +8379,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; manage_dm_interrupts(adev, acrtc, true); } -#ifdef CONFIG_DEBUG_FS - if (new_crtc_state->active && + if (IS_ENABLED(CONFIG_DEBUG_FS) && new_crtc_state->active && amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) { /** * Frontend may have changed so reapply the CRC capture @@ -8401,7 +8400,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) amdgpu_dm_crtc_configure_crc_source( crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src); } -#endif } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 0235bfb246e5..eba2f1d35d07 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -46,13 +46,13 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source } /* amdgpu_dm_crc.c */ -#ifdef CONFIG_DEBUG_FS bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state); bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state, struct dm_crtc_state *dm_old_crtc_state); int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_pipe_crc_source source); +#ifdef CONFIG_DEBUG_FS int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, -- 2.29.2

3 2

[PATCH] drm/amd/display: fix comparison pointer to bool warning in dc.c
by Tian Tao 04 Jan '21

04 Jan '21

Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc.c:1543:12-19: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:1496:14-42: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:971:15-48: WARNING: Comparison to bool drivers/gpu/drm/amd/display/dc/core/dc.c:976:15-44: WARNING: Comparison to bool Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 58eb0d6..ea28b75 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -968,12 +968,12 @@ struct dc *dc_create(const struct dc_init_data *init_params) goto alloc_fail; if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) { - if (false == dc_construct_ctx(dc, init_params)) { + if (!dc_construct_ctx(dc, init_params)) { dc_destruct(dc); goto construct_fail; } } else { - if (false == dc_construct(dc, init_params)) { + if (!dc_construct(dc, init_params)) { dc_destruct(dc); goto construct_fail; } @@ -1493,7 +1493,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) enum dc_status result = DC_ERROR_UNEXPECTED; int i; - if (false == context_changed(dc, context)) + if (!context_changed(dc, context)) return DC_OK; DC_LOG_DC("%s: %d streams\n", @@ -1540,7 +1540,7 @@ bool dc_acquire_release_mpc_3dlut( if (found_pipe_idx) { if (acquire && pool->funcs->acquire_post_bldn_3dlut) ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); - else if (acquire == false && pool->funcs->release_post_bldn_3dlut) + else if (!acquire && pool->funcs->release_post_bldn_3dlut) ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); } } -- 2.7.4

2 1

[PATCH -next] gpu/drm/radeon: use DIV_ROUND_UP macro to do calculation
by Zheng Yongjun 04 Jan '21

04 Jan '21

Don't open-code DIV_ROUND_UP() kernel macro. Signed-off-by: Zheng Yongjun <zhengyongjun3(a)huawei.com> --- drivers/gpu/drm/radeon/r600_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 390a9621604a..a3aea5329712 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -219,7 +219,7 @@ int r600_fmt_get_nblocksx(u32 format, u32 w) if (bw == 0) return 0; - return (w + bw - 1) / bw; + return DIV_ROUND_UP(w, bw); } int r600_fmt_get_nblocksy(u32 format, u32 h) @@ -233,7 +233,7 @@ int r600_fmt_get_nblocksy(u32 format, u32 h) if (bh == 0) return 0; - return (h + bh - 1) / bh; + return DIV_ROUND_UP(h, bh); } struct array_mode_checker { -- 2.22.0

2 1

[PATCH] drm/amd/display: remove useless else if
by Tian Tao 04 Jan '21

04 Jan '21

Fix the following coccinelle report: drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c:1357:6-8: WARNING: possible condition with no effect (if == else) Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c index 808c4dc..504f2a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c @@ -1354,8 +1354,6 @@ static bool dcn302_resource_construct( if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; - else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) - dc->debug = debug_defaults_diags; else dc->debug = debug_defaults_diags; -- 2.7.4

2 1

[PATCH] drm/amd/display: remove unused including <linux/version.h>
by Tian Tao 04 Jan '21

04 Jan '21

Remove including <linux/version.h> that don't need it. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5675c1f..3255531 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -60,7 +60,6 @@ #include <linux/module.h> #include <linux/moduleparam.h> -#include <linux/version.h> #include <linux/types.h> #include <linux/pm_runtime.h> #include <linux/pci.h> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index f6f487e..3244a6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -25,7 +25,6 @@ #include <linux/string.h> #include <linux/acpi.h> -#include <linux/version.h> #include <linux/i2c.h> #include <drm/drm_probe_helper.h> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 8ab0b90..5b0a4a7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -23,7 +23,6 @@ * */ -#include <linux/version.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_dp_mst_helper.h> -- 2.7.4

2 1

[PATCH v1 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema
by Nick Fan 04 Jan '21

04 Jan '21

Convert the Arm Valhall GPU binding to DT schema format. Define a compatible string for the Mali Valhall GPU for Mediatek's SoC platform. Signed-off-by: Nick Fan <Nick.Fan(a)mediatek.com> --- .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml new file mode 100644 index 000000000000..436294c032ff --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml @@ -0,0 +1,252 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Mali Valhall GPU + +maintainers: + - Rob Herring <robh(a)kernel.org> + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + items: + - enum: + - mediatek,mt8192-mali + - const: arm,mali-valhall + + reg: + maxItems: 1 + + interrupts: + items: + - description: GPU interrupt + - description: MMU interrupt + - description: Job interrupt + + interrupt-names: + items: + - const: gpu + - const: mmu + - const: job + + clocks: + minItems: 1 + + power-domains: + minItems: 1 + maxItems: 5 + + mali-supply: true + sram-supply: true + + operating-points-v2: true + + "#cooling-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-mali + then: + properties: + sram-supply: true + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + minItems: 5 + maxItems: 5 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + - const: core3 + - const: core4 + + required: + - sram-supply + - power-domains + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu@13000000 { + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; + reg = <0x13000000 0x4000>; + interrupts = + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = + "gpu", + "mmu", + "job"; + + clocks = <&mfgcfg 0>; + + power-domains = + <&scpsys 4>, + <&scpsys 5>, + <&scpsys 6>, + <&scpsys 7>, + <&scpsys 8>; + + operating-points-v2 = <&gpu_opp_table>; + mali-supply = <&mt6315_7_vbuck1>; + sram-supply = <&mt6359_vsram_others_ldo_reg>; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + opp-hz-real = /bits/ 64 <358000000>, + /bits/ 64 <358000000>; + opp-microvolt = <606250>, + <750000>; + }; + + opp-399000000 { + opp-hz = /bits/ 64 <399000000>; + opp-hz-real = /bits/ 64 <399000000>, + /bits/ 64 <399000000>; + opp-microvolt = <618750>, + <750000>; + }; + + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-hz-real = /bits/ 64 <440000000>, + /bits/ 64 <440000000>; + opp-microvolt = <631250>, + <750000>; + }; + + opp-482000000 { + opp-hz = /bits/ 64 <482000000>; + opp-hz-real = /bits/ 64 <482000000>, + /bits/ 64 <482000000>; + opp-microvolt = <643750>, + <750000>; + }; + + opp-523000000 { + opp-hz = /bits/ 64 <523000000>; + opp-hz-real = /bits/ 64 <523000000>, + /bits/ 64 <523000000>; + opp-microvolt = <656250>, + <750000>; + }; + + opp-564000000 { + opp-hz = /bits/ 64 <564000000>; + opp-hz-real = /bits/ 64 <564000000>, + /bits/ 64 <564000000>; + opp-microvolt = <668750>, + <750000>; + }; + + opp-605000000 { + opp-hz = /bits/ 64 <605000000>; + opp-hz-real = /bits/ 64 <605000000>, + /bits/ 64 <605000000>; + opp-microvolt = <681250>, + <750000>; + }; + + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-hz-real = /bits/ 64 <647000000>, + /bits/ 64 <647000000>; + opp-microvolt = <693750>, + <750000>; + }; + + opp-688000000 { + opp-hz = /bits/ 64 <688000000>; + opp-hz-real = /bits/ 64 <688000000>, + /bits/ 64 <688000000>; + opp-microvolt = <706250>, + <750000>; + }; + + opp-724000000 { + opp-hz = /bits/ 64 <724000000>; + opp-hz-real = /bits/ 64 <724000000>, + /bits/ 64 <724000000>; + opp-microvolt = <725000>, + <750000>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-hz-real = /bits/ 64 <760000000>, + /bits/ 64 <760000000>; + opp-microvolt = <743750>, + <750000>; + }; + + opp-795000000 { + opp-hz = /bits/ 64 <795000000>; + opp-hz-real = /bits/ 64 <795000000>, + /bits/ 64 <795000000>; + opp-microvolt = <762500>, + <762500>; + }; + + opp-831000000 { + opp-hz = /bits/ 64 <831000000>; + opp-hz-real = /bits/ 64 <831000000>, + /bits/ 64 <831000000>; + opp-microvolt = <781250>, + <781250>; + }; + + opp-855000000 { + opp-hz = /bits/ 64 <855000000>; + opp-hz-real = /bits/ 64 <855000000>, + /bits/ 64 <855000000>; + opp-microvolt = <793750>, + <793750>; + }; + + opp-902000000 { + opp-hz = /bits/ 64 <902000000>; + opp-hz-real = /bits/ 64 <902000000>, + /bits/ 64 <902000000>; + opp-microvolt = <818750>, + <818750>; + }; + + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-hz-real = /bits/ 64 <950000000>, + /bits/ 64 <950000000>; + opp-microvolt = <843750>, + <843750>; + }; + }; +... -- 2.18.0

2 2

amdgpu does not support 3840x2160@30Hz on kaveri apu
by Davide Corrado 04 Jan '21

04 Jan '21

hello, I'd like to report this issue that I am having since I updated my display (samsung U28E590). The amdgpu does not support the native resolution of my new monitor, which is 3840x2160*.* Using a HDMI or DVI connection (I tried both, same results), the maximum supported refresh is 30Hz, so I'm stuck with that (don't have a displayport). The radeon module works fine, I'm having this issue just when I use amdgpu (which I'd like to, because performance is better). Some info of my hardware: cpu: AMD A10-7870K Radeon R7, 12 Compute Cores 4C+8G kernel version (I tried different ones and different linux distros, same results!): 5.9.16-200.fc33.x86_64 #1 SMP Mon Dec 21 14:08:22 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux Monitor: Samsung U28E590. description: If I boot the system using amdgpu and no video mode selection, the system boots but I don't get a screen during boot and in wayland. I can connect using ssh, so the system is running fine, just no display; If I force a full HD resolution with "video:" in the kernel line, I can see the boot process but the screen disappears when wayland starts (because the default resolution is 3840x2160@30Hz). Using a full HD monitor results in no issues, so it must be related to this very 4k resolution. As I have already stated, radeon module works with the same software/hardware configuration. thanks you so much for your time :-) -- Davide Corrado UNIX Team Leader Via Abramo Lincoln, 25 20129 Milano Tel +39 3474259950

5 8

[PATCH] drm/hisilicon: Use simple encoder
by Tian Tao 04 Jan '21

04 Jan '21

The hibmc driver uses empty implementations for its encoders. Replace the code with the generic simple encoder. Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c index d35548d..c76f996 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c @@ -14,6 +14,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_print.h> +#include <drm/drm_simple_kms_helper.h> #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" @@ -90,10 +91,6 @@ static const struct drm_encoder_helper_funcs hibmc_encoder_helper_funcs = { .mode_set = hibmc_encoder_mode_set, }; -static const struct drm_encoder_funcs hibmc_encoder_funcs = { - .destroy = drm_encoder_cleanup, -}; - int hibmc_vdac_init(struct hibmc_drm_private *priv) { struct drm_device *dev = &priv->dev; @@ -109,8 +106,7 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) } encoder->possible_crtcs = 0x1; - ret = drm_encoder_init(dev, encoder, &hibmc_encoder_funcs, - DRM_MODE_ENCODER_DAC, NULL); + ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC); if (ret) { drm_err(dev, "failed to init encoder: %d\n", ret); return ret; -- 2.7.4

2 1

Re: [PATCH v2 1/2] drm/radeon: use writel to avoid gcc optimization
by Christian König 04 Jan '21

04 Jan '21

Am 25.12.20 um 04:54 schrieb Chen Li: > When using e8860(gcn1) on arm64, the kernel crashed on drm/radeon: > > [ 11.240414] pc : __memset+0x4c/0x188 > [ 11.244101] lr : radeon_uvd_get_create_msg+0x114/0x1d0 [radeon] > [ 11.249995] sp : ffff00000d7eb700 > [ 11.253295] x29: ffff00000d7eb700 x28: ffff8001f632a868 > [ 11.258585] x27: 0000000000040000 x26: ffff00000de00000 > [ 11.263875] x25: 0000000000000125 x24: 0000000000000001 > [ 11.269168] x23: 0000000000000000 x22: 0000000000000005 > [ 11.274459] x21: ffff00000df24000 x20: ffff8001f74b4000 > [ 11.279753] x19: 0000000000124000 x18: 0000000000000020 > [ 11.285043] x17: 0000000000000000 x16: 0000000000000000 > [ 11.290336] x15: ffff000009309000 x14: ffffffffffffffff > [ 11.290340] x13: ffff0000094b6f88 x12: ffff0000094b6bd2 > [ 11.290343] x11: ffff00000d7eb700 x10: ffff00000d7eb700 > [ 11.306246] x9 : ffff00000d7eb700 x8 : ffff00000df2402c > [ 11.306254] x7 : 0000000000000000 x6 : ffff0000094b626a > [ 11.306257] x5 : 0000000000000000 x4 : 0000000000000004 > [ 11.306262] x3 : ffffffffffffffff x2 : 0000000000000fd4 > [ 11.306265] x1 : 0000000000000000 x0 : ffff00000df2402c > [ 11.306272] Call trace: > [ 11.306316] __memset+0x4c/0x188 > [ 11.306638] uvd_v1_0_ib_test+0x70/0x1c0 [radeon] > [ 11.306758] radeon_ib_ring_tests+0x54/0xe0 [radeon] > [ 11.309961] IPv6: ADDRCONF(NETDEV_UP): enp5s0f0: link is not ready > [ 11.354628] radeon_device_init+0x53c/0xbdc [radeon] > [ 11.354693] radeon_driver_load_kms+0x6c/0x1b0 [radeon] > [ 11.364788] drm_dev_register+0x130/0x1c0 > [ 11.364794] drm_get_pci_dev+0x8c/0x14c > [ 11.372704] radeon_pci_probe+0xb0/0x110 [radeon] > [ 11.372715] local_pci_probe+0x3c/0xb0 > [ 11.381129] pci_device_probe+0x114/0x1b0 > [ 11.385121] really_probe+0x23c/0x400 > [ 11.388757] driver_probe_device+0xdc/0x130 > [ 11.392921] __driver_attach+0x128/0x150 > [ 11.396826] bus_for_each_dev+0x70/0xbc > [ 11.400643] driver_attach+0x20/0x2c > [ 11.404201] bus_add_driver+0x160/0x260 > [ 11.408019] driver_register+0x74/0x120 > [ 11.411837] __pci_register_driver+0x40/0x50 > [ 11.416149] radeon_init+0x78/0x1000 [radeon] > [ 11.420489] do_one_initcall+0x54/0x154 > [ 11.424310] do_init_module+0x54/0x260 > [ 11.428041] load_module+0x1ccc/0x20b0 > [ 11.431773] __se_sys_finit_module+0xac/0x10c > [ 11.436109] __arm64_sys_finit_module+0x18/0x20 > [ 11.440622] el0_svc_common+0x70/0x164 > [ 11.444353] el0_svc_handler+0x2c/0x80 > [ 11.448084] el0_svc+0x8/0xc > [ 11.450954] Code: d65f03c0 cb0803e4 f2400c84 54000080 (a9001d07) > > Obviously, the __memset call is generated by gcc(8.3.1). It optimizes > this for loop into memset. But this may break on some platforms which > cannot map device memory correctly. So, just invoke `writel` to handle this. > Signed-off-by: chenli <chenli(a)uniontech.com> > --- > v1->v2: > * Convert the other assignments of msg as well. > * Casting types to avoid static checker warnings. > > --- > drivers/gpu/drm/radeon/radeon_uvd.c | 34 ++++++++++++++--------------- > 1 file changed, 17 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c > index 39c1c339be7b..e576470402b9 100644 > --- a/drivers/gpu/drm/radeon/radeon_uvd.c > +++ b/drivers/gpu/drm/radeon/radeon_uvd.c > @@ -791,19 +791,19 @@ int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, > return r; > > /* stitch together an UVD create msg */ > - msg[0] = cpu_to_le32(0x00000de4); > - msg[1] = cpu_to_le32(0x00000000); > - msg[2] = cpu_to_le32(handle); > - msg[3] = cpu_to_le32(0x00000000); > - msg[4] = cpu_to_le32(0x00000000); > - msg[5] = cpu_to_le32(0x00000000); > - msg[6] = cpu_to_le32(0x00000000); > - msg[7] = cpu_to_le32(0x00000780); > - msg[8] = cpu_to_le32(0x00000440); > - msg[9] = cpu_to_le32(0x00000000); > - msg[10] = cpu_to_le32(0x01b37000); > + writel(cpu_to_le32(0x00000de4), (void __iomem *)&msg[0]); I made the minor change to apply the __iomem attribute to the msg definition and avoid the casting here. With that done I've pushed the series to our internal servers. It should show up in 5.12. Thanks for the help, Christian. > + writel(0x0, (void __iomem *)&msg[1]); > + writel(cpu_to_le32(handle), (void __iomem *)&msg[2]); > + writel(0x0, (void __iomem *)&msg[3]); > + writel(0x0, (void __iomem *)&msg[4]); > + writel(0x0, (void __iomem *)&msg[5]); > + writel(0x0, (void __iomem *)&msg[6]); > + writel(cpu_to_le32(0x00000780), (void __iomem *)&msg[7]); > + writel(cpu_to_le32(0x00000440), (void __iomem *)&msg[8]); > + writel(0x0, (void __iomem *)&msg[9]); > + writel(cpu_to_le32(0x01b37000), (void __iomem *)&msg[10]); > for (i = 11; i < 1024; ++i) > - msg[i] = cpu_to_le32(0x0); > + writel(0x0, (void __iomem *)&msg[i]); > > r = radeon_uvd_send_msg(rdev, ring, addr, fence); > radeon_bo_unreserve(rdev->uvd.vcpu_bo); > @@ -827,12 +827,12 @@ int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, > return r; > > /* stitch together an UVD destroy msg */ > - msg[0] = cpu_to_le32(0x00000de4); > - msg[1] = cpu_to_le32(0x00000002); > - msg[2] = cpu_to_le32(handle); > - msg[3] = cpu_to_le32(0x00000000); > + writel(cpu_to_le32(0x00000de4), (void __iomem *)&msg[0]); > + writel(cpu_to_le32(0x00000002), (void __iomem *)&msg[1]); > + writel(cpu_to_le32(handle), (void __iomem *)&msg[2]); > + writel(0x0, (void __iomem *)&msg[3]); > for (i = 4; i < 1024; ++i) > - msg[i] = cpu_to_le32(0x0); > + writel(0x0, (void __iomem *)&msg[i]); > > r = radeon_uvd_send_msg(rdev, ring, addr, fence); > radeon_bo_unreserve(rdev->uvd.vcpu_bo);

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dri-devel January 2021