dri-devel October 2021

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825 discussions

[PATCH 1/2] drm/i915/pmu: Add a name to the execlists stats
by Umesh Nerlige Ramappa 12 Oct '21

12 Oct '21

In preparation for GuC pmu stats, add a name to the execlists stats structure so that it can be differentiated from the GuC stats. Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +++--- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33 +++++++------ drivers/gpu/drm/i915/gt/intel_engine_types.h | 52 +++++++++++--------- 3 files changed, 53 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 2ae57e4656a3..38436f4b5706 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -361,7 +361,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) DRIVER_CAPS(i915)->has_logical_contexts = true; ewma__engine_latency_init(&engine->latency); - seqcount_init(&engine->stats.lock); + seqcount_init(&engine->stats.execlists.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); @@ -1876,15 +1876,16 @@ void intel_engine_dump(struct intel_engine_cs *engine, static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { - ktime_t total = engine->stats.total; + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; + ktime_t total = stats->total; /* * If the engine is executing something at the moment * add it to the total. */ *now = ktime_get(); - if (READ_ONCE(engine->stats.active)) - total = ktime_add(total, ktime_sub(*now, engine->stats.start)); + if (READ_ONCE(stats->active)) + total = ktime_add(total, ktime_sub(*now, stats->start)); return total; } @@ -1898,13 +1899,14 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, */ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned int seq; ktime_t total; do { - seq = read_seqcount_begin(&engine->stats.lock); + seq = read_seqcount_begin(&stats->lock); total = __intel_engine_get_busy_time(engine, now); - } while (read_seqcount_retry(&engine->stats.lock, seq)); + } while (read_seqcount_retry(&stats->lock, seq)); return total; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h index 24fbdd94351a..8e762d683e50 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -15,45 +15,46 @@ static inline void intel_engine_context_in(struct intel_engine_cs *engine) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned long flags; - if (engine->stats.active) { - engine->stats.active++; + if (stats->active) { + stats->active++; return; } /* The writer is serialised; but the pmu reader may be from hardirq */ local_irq_save(flags); - write_seqcount_begin(&engine->stats.lock); + write_seqcount_begin(&stats->lock); - engine->stats.start = ktime_get(); - engine->stats.active++; + stats->start = ktime_get(); + stats->active++; - write_seqcount_end(&engine->stats.lock); + write_seqcount_end(&stats->lock); local_irq_restore(flags); - GEM_BUG_ON(!engine->stats.active); + GEM_BUG_ON(!stats->active); } static inline void intel_engine_context_out(struct intel_engine_cs *engine) { + struct intel_engine_execlists_stats *stats = &engine->stats.execlists; unsigned long flags; - GEM_BUG_ON(!engine->stats.active); - if (engine->stats.active > 1) { - engine->stats.active--; + GEM_BUG_ON(!stats->active); + if (stats->active > 1) { + stats->active--; return; } local_irq_save(flags); - write_seqcount_begin(&engine->stats.lock); + write_seqcount_begin(&stats->lock); - engine->stats.active--; - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); + stats->active--; + stats->total = ktime_add(stats->total, + ktime_sub(ktime_get(), stats->start)); - write_seqcount_end(&engine->stats.lock); + write_seqcount_end(&stats->lock); local_irq_restore(flags); } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 5ae1207c363b..316d8551d22f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -257,6 +257,33 @@ struct intel_engine_execlists { #define INTEL_ENGINE_CS_MAX_NAME 8 +struct intel_engine_execlists_stats { + /** + * @active: Number of contexts currently scheduled in. + */ + unsigned int active; + + /** + * @lock: Lock protecting the below fields. + */ + seqcount_t lock; + + /** + * @total: Total time this engine was busy. + * + * Accumulated time not counting the most recent block in cases where + * engine is currently busy (active > 0). + */ + ktime_t total; + + /** + * @start: Timestamp of the last idle to active transition. + * + * Idle is defined as active == 0, active is active > 0. + */ + ktime_t start; +}; + struct intel_engine_cs { struct drm_i915_private *i915; struct intel_gt *gt; @@ -481,30 +508,7 @@ struct intel_engine_cs { u32 (*get_cmd_length_mask)(u32 cmd_header); struct { - /** - * @active: Number of contexts currently scheduled in. - */ - unsigned int active; - - /** - * @lock: Lock protecting the below fields. - */ - seqcount_t lock; - - /** - * @total: Total time this engine was busy. - * - * Accumulated time not counting the most recent block in cases - * where engine is currently busy (active > 0). - */ - ktime_t total; - - /** - * @start: Timestamp of the last idle to active transition. - * - * Idle is defined as active == 0, active is active > 0. - */ - ktime_t start; + struct intel_engine_execlists_stats execlists; /** * @rps: Utilisation at last RPS sampling. -- 2.20.1

2 4

[PATCH] drm/i915: replacing drm_modeset_lock_all for DRM_MODESET_LOCK_ALL_*
by Maíra Canal 12 Oct '21

12 Oct '21

As requested in GPU Driver Developers Guide TODO list, replaces all drm_lock boilerplates for DRM_MODESET_LOCK_ALL_* helpers. Signed-off-by: Maíra Canal <maira.canal(a)usp.br> --- drivers/gpu/drm/i915/display/intel_display.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 17f44ffea586..71b7ff7b7dea 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13466,22 +13466,13 @@ void intel_display_resume(struct drm_device *dev) if (state) state->acquire_ctx = &ctx; - drm_modeset_acquire_init(&ctx, 0); - - while (1) { - ret = drm_modeset_lock_all_ctx(dev, &ctx); - if (ret != -EDEADLK) - break; - - drm_modeset_backoff(&ctx); - } + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); if (!ret) ret = __intel_display_resume(dev, state, &ctx); intel_enable_ipc(dev_priv); - drm_modeset_drop_locks(&ctx); - drm_modeset_acquire_fini(&ctx); + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); if (ret) drm_err(&dev_priv->drm, -- 2.31.1

2 1

Questions over DSI within DRM.
by Dave Stevenson 12 Oct '21

12 Oct '21

Hi All I'm trying to get DSI devices working reliably on the Raspberry Pi, but I'm hitting a number of places where it isn't clear as to the expected behaviour within DRM. Power on state. Many devices want the DSI clock and/or data lanes in LP-11 state when they are powered up. With the normal calling sequence of: - panel/bridge pre_enable calls from connector towards the encoder. - encoder enable which also enables video. - panel/bridge enable calls from encoder to connector. there is no point at which the DSI tx is initialised but not transmitting video. What DSI states are expected to be adopted at each point? On a similar theme, some devices want the clock lane in HS mode early so they can use it in place of an external oscillator, but the data lanes still in LP-11. There appears to be no way for the display/bridge to signal this requirement or it be achieved. host_transfer calls can supposedly be made at any time, however unless MIPI_DSI_MSG_USE_LPM is set in the message then we're meant to send it in high speed mode. If this is before a mode has been set, what defines the link frequency parameters at this point? Adopting a random default sounds like a good way to get undefined behaviour. DSI burst mode needs to set the DSI link frequency independently of the display mode. How is that meant to be configured? I would have expected it to come from DT due to link frequency often being chosen based on EMC restrictions, but I don't see such a thing in any binding. As a follow on, bridge devices can support burst mode (eg TI's SN65DSI83 that's just been merged), so it needs to know the desired panel timings for the output side of the bridge, but the DSI link timings to set up the bridge's PLL. What's the correct way for signalling that? drm_crtc_state->adjusted_mode vs drm_crtc_state->mode? Except mode is userspace's request, not what has been validated/updated by the panel/bridge. vc4 has constraints that the DSI host interface is fed off an integer divider from a typically 3GHz clock, so the host interface needs to signal that burst mode is in use even if the panel/bridge doesn't need to run in burst mode. (This does mean that displays that require a very precise link frequency can not be supported). It currently updates the adjusted_mode via drm_encoder_helper_funcs mode_fixup, but is that the correct thing to do, or is there a better solution? I'd have expected the DSI tx to be responsible for configuring burst mode parameters anyway, so the mechanism required would seem to be just the normal approach for adopting burst mode if that is defined. Some DSI host interfaces are implemented as bridges, others are encoders. Pro's and con's of each? I suspect I'm just missing the history here. When it comes to the MIPI_DSI_MODE_* flags, which ones are mutually exclusive, or are assumed based on others? Does a burst mode DSI sink set both MIPI_DSI_MODE_VIDEO and MIPI_DSI_MODE_VIDEO_BURST, or just the latter? Presumably !MIPI_DSI_MODE_VIDEO signals the of use command mode for conveying video. So looking at panel-ilitek-ili9881c where it sets just MIPI_DSI_MODE_VIDEO_SYNC_PULSE means command mode video with sync pulses? That sounds unlikely. I have looked for any information that covers this, but failed to find such, hence calling on all your expertise. Many thanks for your time, Dave

6 18

AW: (EXT) Re: [PATCH 1/3] drm/bridge: ti-sn65dsi83: Add vcc supply regulator support
by Alexander Stein 12 Oct '21

12 Oct '21

Hi Sam, On Mon, 11 Oct 2021 22:29:30 +0200, Sam Ravnborg wrote: > > VCC needs to be enabled before releasing the enable GPIO. > > > > Signed-off-by: Alexander Stein <alexander.stein(a)ew.tq-group.com> > > --- > > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 15 ++++++++++++++- > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > index a32f70bc68ea..5fab0fabcd15 100644 > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > @@ -33,6 +33,7 @@ > > #include <linux/of_device.h> > > #include <linux/of_graph.h> > > #include <linux/regmap.h> > > +#include <linux/regulator/consumer.h> > > > > #include <drm/drm_atomic_helper.h> > > #include <drm/drm_bridge.h> > > @@ -143,6 +144,7 @@ struct sn65dsi83 { > > struct mipi_dsi_device *dsi; > > struct drm_bridge *panel_bridge; > > struct gpio_desc *enable_gpio; > > + struct regulator *vcc; > > int dsi_lanes; > > bool lvds_dual_link; > > bool lvds_dual_link_even_odd_swap; > > @@ -647,6 +649,12 @@ static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, > enum sn65dsi83_model model) > > > > ctx->panel_bridge = panel_bridge; > > > > + ctx->vcc = devm_regulator_get(dev, "vcc"); > In the binding the vcc regulator is required, but devm_regulator_get() > will create a dummy regulator if not found. Maybe this is on purpose and > all is good. Thanks for addressing this. I was slightly unsure myself, but IMHO this is all good as this makes the driver backward compatible with older DT which lack the regulator. If there was no vcc regulator necessary and the bridge was working,then a dummy regulator is fine, as the DT fix would be adding a always-on, regulator-fixed without any enable/disable possibility anyway. Best regards, Alexander

1 0

[PATCH v2 1/2] firmware: include drivers/firmware/Kconfig unconditionally
by Arnd Bergmann 12 Oct '21

12 Oct '21

From: Arnd Bergmann <arnd(a)arndb.de> Compile-testing drivers that require access to a firmware layer fails when that firmware symbol is unavailable. This happened twice this week: - My proposed to change to rework the QCOM_SCM firmware symbol broke on ppc64 and others. - The cs_dsp firmware patch added device specific firmware loader into drivers/firmware, which broke on the same set of architectures. We should probably do the same thing for other subsystems as well, but fix this one first as this is a dependency for other patches getting merged. Reviewed-by: Bjorn Andersson <bjorn.andersson(a)linaro.org> Reviewed-by: Charles Keepax <ckeepax(a)opensource.cirrus.com> Acked-by: Will Deacon <will(a)kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson(a)linaro.org> Cc: Mark Brown <broonie(a)kernel.org> Cc: Liam Girdwood <lgirdwood(a)gmail.com> Cc: Charles Keepax <ckeepax(a)opensource.cirrus.com> Cc: Simon Trimmer <simont(a)opensource.cirrus.com> Cc: Michael Ellerman <mpe(a)ellerman.id.au> Reviewed-by: Mark Brown <broonie(a)kernel.org> Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- No changes in v2, but it's now queued in my asm-generic tree for v5.15 arch/arm/Kconfig | 2 -- arch/arm64/Kconfig | 2 -- arch/ia64/Kconfig | 2 -- arch/mips/Kconfig | 2 -- arch/parisc/Kconfig | 2 -- arch/riscv/Kconfig | 2 -- arch/x86/Kconfig | 2 -- drivers/Kconfig | 2 ++ 8 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fc196421b2ce..59baf6c132a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1989,8 +1989,6 @@ config ARCH_HIBERNATION_POSSIBLE endmenu -source "drivers/firmware/Kconfig" - if CRYPTO source "arch/arm/crypto/Kconfig" endif diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 077f2ec4eeb2..407b4addea36 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1931,8 +1931,6 @@ source "drivers/cpufreq/Kconfig" endmenu -source "drivers/firmware/Kconfig" - source "drivers/acpi/Kconfig" source "arch/arm64/kvm/Kconfig" diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 045792cde481..1e33666fa679 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -388,8 +388,6 @@ config CRASH_DUMP help Generate crash dump after being started by kexec. -source "drivers/firmware/Kconfig" - endmenu menu "Power management and ACPI options" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 771ca53af06d..6b8f591c5054 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3316,8 +3316,6 @@ source "drivers/cpuidle/Kconfig" endmenu -source "drivers/firmware/Kconfig" - source "arch/mips/kvm/Kconfig" source "arch/mips/vdso/Kconfig" diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 4742b6f169b7..27a8b49af11f 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -384,6 +384,4 @@ config KEXEC_FILE endmenu -source "drivers/firmware/Kconfig" - source "drivers/parisc/Kconfig" diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c3f3fd583e04..8bc71ab143e3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -561,5 +561,3 @@ menu "Power management options" source "kernel/power/Kconfig" endmenu - -source "drivers/firmware/Kconfig" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4e001bbbb425..4dca39744ee9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2828,8 +2828,6 @@ config HAVE_ATOMIC_IOMAP def_bool y depends on X86_32 -source "drivers/firmware/Kconfig" - source "arch/x86/kvm/Kconfig" source "arch/x86/Kconfig.assembler" diff --git a/drivers/Kconfig b/drivers/Kconfig index 30d2db37cc87..0d399ddaa185 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -17,6 +17,8 @@ source "drivers/bus/Kconfig" source "drivers/connector/Kconfig" +source "drivers/firmware/Kconfig" + source "drivers/gnss/Kconfig" source "drivers/mtd/Kconfig" -- 2.29.2

3 3

[PATCH] drm/msm/dp: do not initialize combo phy until plugin interrupt
by Kuogee Hsieh 12 Oct '21

12 Oct '21

Combo phy support both USB3 and DP simultaneously. USB3 is the master of combo phy so that USB3 should initialize and power on its phy before DP initialize its phy. At current implementation, DP driver initialize its phy happen earlier than USB3 initialize its phy which cause timeout error at procedure of power up USB3 phy which prevent USB3 from working. To avoid confliction of phy initialization between USB3 and DP, this patch have DP driver postpone phy initialization until plugin interrupt handler. DP driver only enable regulator, configure its HPD controller and enable interrupt so that it is able to receive HPD interrupts after completion of the initialization phase. DP driver will initialize and power up phy at plugin interrupt handler during normal operation so that both USB3 and DP are work simultaneously. Signed-off-by: Kuogee Hsieh <khsieh(a)codeaurora.org> --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 68 ++++++++++++++++++++++--------------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 9 +++-- drivers/gpu/drm/msm/dp/dp_display.c | 51 +++++++++++++++++++++------- 3 files changed, 84 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 5551a8d..4c5d507 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1378,7 +1378,25 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) return ret; } -int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset) +void dp_ctrl_irq_enable(struct dp_ctrl *dp_ctrl, bool flip) +{ + struct dp_ctrl_private *ctrl; + + if (!dp_ctrl) { + DRM_ERROR("Invalid input data\n"); + return; + } + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + ctrl->dp_ctrl.orientation = flip; + + dp_catalog_ctrl_reset(ctrl->catalog); + + dp_catalog_ctrl_enable_irq(ctrl->catalog, true); +} + +void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; struct dp_io *dp_io; @@ -1386,33 +1404,44 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset) if (!dp_ctrl) { DRM_ERROR("Invalid input data\n"); - return -EINVAL; + return; } ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); dp_io = &ctrl->parser->io; phy = dp_io->phy; - ctrl->dp_ctrl.orientation = flip; - - if (reset) - dp_catalog_ctrl_reset(ctrl->catalog); - dp_catalog_ctrl_phy_reset(ctrl->catalog); phy_init(phy); - dp_catalog_ctrl_enable_irq(ctrl->catalog, true); +} - return 0; +void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; + + if (!dp_ctrl) { + DRM_ERROR("Invalid input data\n"); + return; + } + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; + + dp_catalog_ctrl_phy_reset(ctrl->catalog); + phy_exit(phy); } /** - * dp_ctrl_host_deinit() - Uninitialize DP controller + * dp_ctrl_irq_phy_exit() - disable dp irq and exit phy * @dp_ctrl: Display Port Driver data * * Perform required steps to uninitialize DP controller * and its resources. */ -void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl) +void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; struct dp_io *dp_io; @@ -1866,23 +1895,6 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) return ret; } -void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl) -{ - struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; - struct phy *phy; - - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; - - dp_catalog_ctrl_reset(ctrl->catalog); - - phy_exit(phy); - - DRM_DEBUG_DP("DP off phy done\n"); -} - int dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 2363a2d..c1e4b1b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,12 +19,9 @@ struct dp_ctrl { u32 pixel_rate; }; -int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset); -void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl); int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl); -void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl); int dp_ctrl_off(struct dp_ctrl *dp_ctrl); void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl); void dp_ctrl_isr(struct dp_ctrl *dp_ctrl); @@ -34,4 +31,10 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, struct dp_power *power, struct dp_catalog *catalog, struct dp_parser *parser); +void dp_ctrl_irq_enable(struct dp_ctrl *dp_ctrl, bool flip); +void dp_ctrl_irq_disable(struct dp_ctrl *dp_ctrl); +void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl); +void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl); +void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cad25dd..44032ae 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -62,6 +62,11 @@ enum { EV_DISCONNECT_PENDING_TIMEOUT, }; +enum { + TYPE_eDP = 1, + TYPE_DP, +}; + #define EVENT_TIMEOUT (HZ/10) /* 100ms */ #define DP_EVENT_Q_MAX 8 @@ -81,6 +86,7 @@ struct dp_display_private { int irq; int id; + int type; /* state variables */ bool core_initialized; @@ -121,31 +127,37 @@ struct dp_display_private { struct msm_dp_config { phys_addr_t io_start[3]; + int type; size_t num_dp; }; static const struct msm_dp_config sc7180_dp_cfg = { .io_start = { 0x0ae90000 }, + .type = TYPE_DP, .num_dp = 1, }; static const struct msm_dp_config sc8180x_dp_cfg = { .io_start = { 0xae90000, 0xae98000, 0 }, + .type = TYPE_DP, .num_dp = 3, }; static const struct msm_dp_config sc8180x_edp_cfg = { .io_start = { 0, 0, 0xae9a000 }, .num_dp = 3, + .type = TYPE_eDP, }; static const struct msm_dp_config sc7280_edp_cfg = { .io_start = { 0xaea0000, 0 }, + .type = TYPE_eDP, .num_dp = 2, }; static const struct msm_dp_config sc7280_dp_cfg = { .io_start = { 0, 0xae90000 }, + .type = TYPE_DP, .num_dp = 2, }; @@ -392,7 +404,7 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) return rc; } -static void dp_display_host_init(struct dp_display_private *dp, int reset) +static void dp_display_host_init(struct dp_display_private *dp) { bool flip = false; @@ -404,12 +416,21 @@ static void dp_display_host_init(struct dp_display_private *dp, int reset) if (dp->usbpd->orientation == ORIENTATION_CC2) flip = true; - dp_power_init(dp->power, flip); - dp_ctrl_host_init(dp->ctrl, flip, reset); + dp_power_init(dp->power, false); + dp_ctrl_irq_enable(dp->ctrl, flip); + + if (dp->type == TYPE_eDP) + dp_ctrl_phy_init(dp->ctrl); + dp_aux_init(dp->aux); dp->core_initialized = true; } +static void dp_display_host_phy_init(struct dp_display_private *dp) +{ + dp_ctrl_phy_init(dp->ctrl); +} + static void dp_display_host_deinit(struct dp_display_private *dp) { if (!dp->core_initialized) { @@ -417,7 +438,7 @@ static void dp_display_host_deinit(struct dp_display_private *dp) return; } - dp_ctrl_host_deinit(dp->ctrl); + dp_ctrl_irq_phy_exit(dp->ctrl); dp_aux_deinit(dp->aux); dp_power_deinit(dp->power); @@ -435,7 +456,7 @@ static int dp_display_usbpd_configure_cb(struct device *dev) goto end; } - dp_display_host_init(dp, false); + dp_display_host_phy_init(dp); rc = dp_display_process_hpd_high(dp); end: @@ -646,9 +667,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) if (state == ST_DISCONNECTED) { /* triggered by irq_hdp with sink_count = 0 */ if (dp->link->sink_count == 0) { - dp_ctrl_off_phy(dp->ctrl); + dp_ctrl_phy_exit(dp->ctrl); hpd->hpd_high = 0; - dp->core_initialized = false; } mutex_unlock(&dp->event_mutex); return 0; @@ -1040,7 +1060,7 @@ int dp_display_get_test_bpp(struct msm_dp *dp) static void dp_display_config_hpd(struct dp_display_private *dp) { - dp_display_host_init(dp, true); + dp_display_host_init(dp); dp_catalog_ctrl_hpd_config(dp->catalog); /* Enable interrupt first time @@ -1222,7 +1242,8 @@ int dp_display_request_irq(struct msm_dp *dp_display) return 0; } -static int dp_display_get_id(struct platform_device *pdev) +static int dp_display_get_id(struct platform_device *pdev, + struct msm_dp_config *dp_cfg) { const struct msm_dp_config *cfg = of_device_get_match_data(&pdev->dev); struct resource *res; @@ -1234,8 +1255,10 @@ static int dp_display_get_id(struct platform_device *pdev) return -EINVAL; for (i = 0; i < cfg->num_dp; i++) { - if (cfg->io_start[i] == res->start) + if (cfg->io_start[i] == res->start) { + *dp_cfg = *cfg; return i; + } } dev_err(&pdev->dev, "unknown displayport instance\n"); @@ -1246,6 +1269,7 @@ static int dp_display_probe(struct platform_device *pdev) { int rc = 0; struct dp_display_private *dp; + struct msm_dp_config dp_cfg; if (!pdev || !pdev->dev.of_node) { DRM_ERROR("pdev not found\n"); @@ -1256,12 +1280,13 @@ static int dp_display_probe(struct platform_device *pdev) if (!dp) return -ENOMEM; - dp->id = dp_display_get_id(pdev); + dp->id = dp_display_get_id(pdev, &dp_cfg); if (dp->id < 0) return -EINVAL; dp->pdev = pdev; dp->name = "drm_dp"; + dp->type = dp_cfg.type; rc = dp_init_sub_modules(dp); if (rc) { @@ -1314,7 +1339,7 @@ static int dp_pm_resume(struct device *dev) dp->hpd_state = ST_DISCONNECTED; /* turn on dp ctrl/phy */ - dp_display_host_init(dp, true); + dp_display_host_init(dp); dp_catalog_ctrl_hpd_config(dp->catalog); @@ -1531,7 +1556,7 @@ int msm_dp_display_enable(struct msm_drm_private *priv, struct drm_encoder *enco state = dp_display->hpd_state; if (state == ST_DISPLAY_OFF) - dp_display_host_init(dp_display, true); + dp_display_host_phy_init(dp_display); dp_display_enable(dp_display, 0); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

2 1

BUG: KASAN: use-after-free in enqueue_timer+0x4f/0x1e0
by Kim Phillips 12 Oct '21

12 Oct '21

Hi, I occasionally see the below trace with Linus' master on an AMD Milan system: [ 25.657322] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 25.665097] #PF: supervisor instruction fetch in kernel mode [ 25.671448] #PF: error_code(0x0010) - not-present page [ 25.677178] PGD 0 P4D 0 [ 25.680000] Oops: 0010 [#1] PREEMPT SMP NOPTI [ 25.684857] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.0-rc3+ #71 [ 25.692043] Hardware name: AMD Corporation ETHANOL_X/ETHANOL_X, BIOS RXM1006B 08/20/2021 [ 25.701069] RIP: 0010:0x0 [ 25.703993] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 25.711661] RSP: 0018:ffffc90000003eb8 EFLAGS: 00010002 [ 25.717488] RAX: 0000000000000101 RBX: 0000000000000101 RCX: 0000000000000000 [ 25.725449] RDX: 00000000fffef080 RSI: 0000000000000000 RDI: ffff88817751e350 [ 25.733408] RBP: ffffc90000003ed8 R08: 0000000000000000 R09: 00000000000002e6 [ 25.741368] R10: ffff88810dc8b2d0 R11: ffff88bf4de290b0 R12: ffff88817751e350 [ 25.749327] R13: 0000000000000000 R14: ffff88bf4de18dc0 R15: ffff88817751e350 [ 25.757286] FS: 0000000000000000(0000) GS:ffff88bf4de00000(0000) knlGS:0000000000000000 [ 25.766312] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 25.772720] CR2: ffffffffffffffd6 CR3: 0000000166650002 CR4: 0000000000770ef0 [ 25.780754] PKRU: 55555554 [ 25.783768] Call Trace: [ 25.786492] <IRQ> [ 25.788729] call_timer_fn+0x2e/0x130 [ 25.792814] run_timer_softirq+0x361/0x4a0 [ 25.797381] ? lapic_next_event+0x21/0x30 [ 25.801852] ? clockevents_program_event+0x8f/0xe0 [ 25.807195] __do_softirq+0xfb/0x2db [ 25.811183] irq_exit_rcu+0x98/0xd0 [ 25.815073] sysvec_apic_timer_interrupt+0xac/0xd0 [ 25.820415] </IRQ> [ 25.822751] asm_sysvec_apic_timer_interrupt+0x12/0x20 [ 25.828481] RIP: 0010:native_safe_halt+0xb/0x10 [ 25.833533] Code: 08 74 81 eb c0 cc cc cc cc cc cc cc cc cc cc eb 07 0f 00 2d 69 68 60 00 f4 c3 0f 1f 44 00 00 eb 07 0f 00 2d 59 68 60 00 fb f4 <c3> cc cc cc cc 0f 1f 44 00 00 55 48 89 e5 53 e8 b1 17 ff ff 66 90 [ 25.854485] RSP: 0018:ffffffff82803e10 EFLAGS: 00000206 [ 25.860311] RAX: ffffffff81c06c60 RBX: 0000000000000000 RCX: 0000000000000000 [ 25.868270] RDX: 0000000000000000 RSI: ffffffff825afb2f RDI: ffffffff825bda91 [ 25.876229] RBP: ffffffff82803e18 R08: 00000066a1710f94 R09: 0000000000000001 [ 25.884188] R10: 0000000000000001 R11: 0000000000000000 R12: ffffffff82813940 [ 25.892146] R13: ffffffff82813940 R14: 0000000000000000 R15: 0000000000000000 [ 25.900098] ? __sched_text_end+0x6/0x6 [ 25.904462] ? default_idle+0xe/0x20 [ 25.908446] arch_cpu_idle+0x15/0x20 [ 25.912432] default_idle_call+0x33/0xf0 [ 25.916804] do_idle+0x209/0x270 [ 25.920402] cpu_startup_entry+0x20/0x30 [ 25.924774] rest_init+0xd4/0xe0 [ 25.928370] arch_call_rest_init+0xe/0x1b [ 25.932840] start_kernel+0x6bc/0x6e2 [ 25.936922] x86_64_start_reservations+0x24/0x26 [ 25.942069] x86_64_start_kernel+0x75/0x79 [ 25.946635] secondary_startup_64_no_verify+0xb0/0xbb [ 25.952270] Modules linked in: intel_rapl_msr intel_rapl_common amd64_edac edac_mce_amd kvm_amd kvm ipmi_si(+) ipmi_devintf wmi_bmof rapl ipmi_msghandler input_leds ccp k10temp mac_hid sch_fq_codel msr ip_tables x_tables autofs4 btrfs blake2b_generic zstd_compress raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq libcrc32c raid1 raid0 multipath linear ast i2c_algo_bit drm_vram_helper drm_ttm_helper ttm crct10dif_pclmul drm_kms_helper crc32_pclmul ghash_clmulni_intel syscopyarea sysfillrect hid_generic aesni_intel sysimgblt crypto_simd fb_sys_fops cryptd cec usbhid nvme ahci drm e1000e nvme_core libahci hid i2c_piix4 wmi [ 26.017199] CR2: 0000000000000000 [ 26.020893] ---[ end trace 4ffc93f5c298732e ]--- [ 26.026040] RIP: 0010:0x0 [ 26.028958] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 26.036626] RSP: 0018:ffffc90000003eb8 EFLAGS: 00010002 [ 26.042557] RAX: 0000000000000101 RBX: 0000000000000101 RCX: 0000000000000000 [ 26.050506] RDX: 00000000fffef080 RSI: 0000000000000000 RDI: ffff88817751e350 [ 26.058464] RBP: ffffc90000003ed8 R08: 0000000000000000 R09: 00000000000002e6 [ 26.066423] R10: ffff88810dc8b2d0 R11: ffff88bf4de290b0 R12: ffff88817751e350 [ 26.074380] R13: 0000000000000000 R14: ffff88bf4de18dc0 R15: ffff88817751e350 [ 26.082330] FS: 0000000000000000(0000) GS:ffff88bf4de00000(0000) knlGS:0000000000000000 [ 26.091356] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 26.097765] CR2: ffffffffffffffd6 CR3: 0000000166650002 CR4: 0000000000770ef0 [ 26.105722] PKRU: 55555554 [ 26.108736] Kernel panic - not syncing: Fatal exception in interrupt [ 26.116349] Kernel Offset: disabled [ 26.120237] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- Adding 'nokaslr' and CONFIG_DEBUG_OBJECTS_TIMERS=y didn't make it more reproducible, but CONFIG_KASAN=y changed the signature to this use-after-free that I used to drive bisect: [ 40.503396] ================================================================== [ 40.514471] input: HID 0b1f:03e9 as /devices/pci0000:20/0000:20:08.1/0000:22:00.3/usb1/1-2/1-2.2/1-2.2:1.1/0003:0B1F:03E9.0004/input/input6 [ 40.521823] BUG: KASAN: use-after-free in enqueue_timer+0x4f/0x1e0 [ 40.536634] hid-generic 0003:0B1F:03E9.0004: input,hidraw1: USB HID v1.00 Mouse [HID 0b1f:03e9] on usb-0000:22:00.3-2.2/input1 [ 40.542696] Write of size 8 at addr ffff8881feb80358 by task kworker/0:2/786 [ 40.542705] CPU: 0 PID: 786 Comm: kworker/0:2 Not tainted 5.15.0-rc4+ #105 [ 40.572608] Hardware name: AMD Corporation ETHANOL_X/ETHANOL_X, BIOS RXM1006B 08/20/2021 [ 40.581639] Workqueue: events work_for_cpu_fn [ 40.586507] Call Trace: [ 40.589234] dump_stack_lvl+0x4a/0x5f [ 40.593324] print_address_description.constprop.0+0x28/0x150 [ 40.599750] ? enqueue_timer+0x4f/0x1e0 [ 40.604032] kasan_report.cold+0x82/0xdb [ 40.608435] ? ast_pci_probe+0xb1/0x100 [ast] [ 40.613305] ? enqueue_timer+0x4f/0x1e0 [ 40.617582] __asan_store8+0x6c/0x90 [ 40.621570] enqueue_timer+0x4f/0x1e0 [ 40.625654] internal_add_timer+0x9b/0xd0 [ 40.630127] ? enqueue_timer+0x1e0/0x1e0 [ 40.634501] ? debug_smp_processor_id+0x17/0x20 [ 40.639557] ? get_nohz_timer_target+0x6f/0x290 [ 40.644610] ? lock_timer_base+0xb6/0xe0 [ 40.648986] add_timer+0x29a/0x3a0 [ 40.652781] ? run_timer_softirq+0xa40/0xa40 [ 40.657547] ? preempt_count_sub+0x18/0xc0 [ 40.662120] ? _raw_spin_unlock_irqrestore+0x22/0x40 [ 40.667670] ? drm_connector_list_iter_next+0x1bb/0x230 [drm] [ 40.674163] __queue_delayed_work+0xdc/0x140 [ 40.678932] queue_delayed_work_on+0x6c/0x90 [ 40.683698] drm_kms_helper_poll_enable.part.0+0xf5/0x140 [drm_kms_helper] [ 40.691411] ? drm_kms_helper_poll_fini+0x40/0x40 [drm_kms_helper] [ 40.698344] ? __queue_work+0x640/0x640 [ 40.702623] ? debug_object_init+0x16/0x20 [ 40.707195] drm_kms_helper_poll_init+0xb8/0xc0 [drm_kms_helper] [ 40.713968] ast_mode_config_init+0x5f8/0x800 [ast] [ 40.719419] ? ast_crtc_reset+0xa0/0xa0 [ast] [ 40.724287] ast_device_create.cold+0xab6/0xbdd [ast] [ 40.729931] ast_pci_probe+0xba/0x100 [ast] [ 40.734602] ? __pm_runtime_resume+0x65/0xb0 [ 40.739366] ? ast_pm_suspend+0x70/0x70 [ast] [ 40.739887] ata7: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 40.744231] local_pci_probe+0x80/0xd0 [ 40.744237] ? pci_device_shutdown+0x90/0x90 [ 40.753180] ata7.00: supports DRM functions and may not be fully accessible [ 40.755316] work_for_cpu_fn+0x2e/0x50 [ 40.760086] ata7.00: ATA-11: Samsung SSD 860 PRO 256GB, RVM01B6Q, max UDMA/133 [ 40.767845] process_one_work+0x4b9/0x7f0 [ 40.767852] worker_thread+0x47a/0x6b0 [ 40.772971] ata7.00: disabling queued TRIM support [ 40.780081] kthread+0x209/0x240 [ 40.780085] ? process_one_work+0x7f0/0x7f0 [ 40.780089] ? set_kthread_struct+0x80/0x80 [ 40.784562] ata7.00: 500118192 sectors, multi 1: LBA48 NCQ (depth 32), AA [ 40.788736] ret_from_fork+0x22/0x30 [ 40.796196] ata7.00: Features: Trust Dev-Sleep NCQ-sndrcv [ 40.802735] ata7.00: supports DRM functions and may not be fully accessible [ 40.807011] Allocated by task 786: [ 40.807015] kasan_save_stack+0x23/0x50 [ 40.815459] ata7.00: disabling queued TRIM support [ 40.818577] __kasan_kmalloc+0x83/0xa0 [ 40.818581] __kmalloc+0x2f7/0x4c0 [ 40.818585] __devm_drm_dev_alloc+0x2f/0xb0 [drm] [ 40.826718] ata7.00: configured for UDMA/133 [ 40.834032] ast_device_create+0x32/0x2c0 [ast] [ 40.838646] scsi 6:0:0:0: Direct-Access ATA Samsung SSD 860 1B6Q PQ: 0 ANSI: 5 [ 40.842107] ast_pci_probe+0xba/0x100 [ast] [ 40.842117] local_pci_probe+0x80/0xd0 [ 40.842121] work_for_cpu_fn+0x2e/0x50 [ 40.848592] ata7.00: Enabling discard_zeroes_data [ 40.851648] process_one_work+0x4b9/0x7f0 [ 40.855629] sd 6:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB) [ 40.860689] worker_thread+0x47a/0x6b0 [ 40.860694] kthread+0x209/0x240 [ 40.860696] ret_from_fork+0x22/0x30 [ 40.865913] sd 6:0:0:0: Attached scsi generic sg0 type 0 [ 40.870516] Freed by task 1190: [ 40.870519] kasan_save_stack+0x23/0x50 [ 40.870523] kasan_set_track+0x20/0x30 [ 40.871945] sd 6:0:0:0: [sda] Write Protect is off [ 40.871968] sd 6:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 40.872098] sd 6:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 40.879881] ata7.00: disabled [ 40.884218] kasan_set_free_info+0x24/0x40 [ 40.884222] __kasan_slab_free+0xef/0x120 [ 40.884227] kfree+0xa1/0x3e0 [ 40.978619] drm_dev_release+0x58/0x60 [drm] [ 40.983446] devm_drm_dev_init_release+0x46/0x60 [drm] [ 40.989235] devm_action_release+0x2c/0x40 [ 40.993803] release_nodes+0x62/0x150 [ 40.997887] devres_release_all+0x10a/0x150 [ 41.002551] really_probe+0x177/0x660 [ 41.006636] __driver_probe_device+0x19e/0x230 [ 41.011592] driver_probe_device+0x4e/0xf0 [ 41.016161] __driver_attach+0x102/0x1d0 [ 41.020536] bus_for_each_dev+0xfb/0x150 [ 41.024911] driver_attach+0x2d/0x40 [ 41.028898] bus_add_driver+0x23f/0x300 [ 41.033177] driver_register+0xdc/0x170 [ 41.037455] __pci_register_driver+0xfc/0x110 [ 41.042314] ast_init+0x48/0x1000 [ast] [ 41.046598] do_one_initcall+0x99/0x2d0 [ 41.050877] do_init_module+0x10f/0x3c0 [ 41.055154] load_module+0x43fa/0x4710 [ 41.059336] __do_sys_finit_module+0x12a/0x1b0 [ 41.064291] __x64_sys_finit_module+0x43/0x50 [ 41.069149] do_syscall_64+0x3b/0xc0 [ 41.073137] entry_SYSCALL_64_after_hwframe+0x44/0xae [ 41.080433] Last potentially related work creation: [ 41.085873] kasan_save_stack+0x23/0x50 [ 41.090151] kasan_record_aux_stack+0xac/0xc0 [ 41.095010] insert_work+0x37/0x170 [ 41.098899] __queue_work+0x208/0x640 [ 41.102982] queue_work_on+0x62/0x80 [ 41.106969] __drm_connector_put_safe+0x80/0xa0 [drm] [ 41.112675] drm_connector_list_iter_next+0x1a0/0x230 [drm] [ 41.118961] drm_mode_config_cleanup+0x12e/0x500 [drm] [ 41.124760] drm_mode_config_init_release+0xe/0x10 [drm] [ 41.130753] drm_managed_release+0x11c/0x240 [drm] [ 41.136164] drm_dev_release+0x46/0x60 [drm] [ 41.140992] devm_drm_dev_init_release+0x46/0x60 [drm] [ 41.146790] devm_action_release+0x2c/0x40 [ 41.151358] release_nodes+0x62/0x150 [ 41.155441] devres_release_all+0x10a/0x150 [ 41.160106] really_probe+0x177/0x660 [ 41.164190] __driver_probe_device+0x19e/0x230 [ 41.169147] driver_probe_device+0x4e/0xf0 [ 41.173716] __driver_attach+0x102/0x1d0 [ 41.178091] bus_for_each_dev+0xfb/0x150 [ 41.182466] driver_attach+0x2d/0x40 [ 41.186452] bus_add_driver+0x23f/0x300 [ 41.190729] driver_register+0xdc/0x170 [ 41.195006] __pci_register_driver+0xfc/0x110 [ 41.199868] ast_init+0x48/0x1000 [ast] [ 41.204151] do_one_initcall+0x99/0x2d0 [ 41.208429] do_init_module+0x10f/0x3c0 [ 41.212707] load_module+0x43fa/0x4710 [ 41.216888] __do_sys_finit_module+0x12a/0x1b0 [ 41.221843] __x64_sys_finit_module+0x43/0x50 [ 41.226704] do_syscall_64+0x3b/0xc0 [ 41.230691] entry_SYSCALL_64_after_hwframe+0x44/0xae [ 41.237985] The buggy address belongs to the object at ffff8881feb80000 which belongs to the cache kmalloc-8k of size 8192 [ 41.251959] The buggy address is located 856 bytes inside of 8192-byte region [ffff8881feb80000, ffff8881feb82000) [ 41.265157] The buggy address belongs to the page: [ 41.270501] page:00000000eecae4f9 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x1feb80 [ 41.280985] head:00000000eecae4f9 order:3 compound_mapcount:0 compound_pincount:0 [ 41.289336] flags: 0x17ffffc0010200(slab|head|node=0|zone=2|lastcpupid=0x1fffff) [ 41.297595] raw: 0017ffffc0010200 0000000000000000 dead000000000122 ffff88810004d180 [ 41.306236] raw: 0000000000000000 0000000000020002 00000001ffffffff 0000000000000000 [ 41.314875] page dumped because: kasan: bad access detected [ 41.322749] Memory state around the buggy address: [ 41.328093] ffff8881feb80200: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 41.336152] ffff8881feb80280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 41.344211] >ffff8881feb80300: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 41.352267] ^ [ 41.359066] ffff8881feb80380: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 41.367123] ffff8881feb80400: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 41.375181] ================================================================== That bisection led to this commit: commit aae74ff9caa8de9a45ae2e46068c417817392a26 Author: Ainux <ainux.wang(a)gmail.com> Date: Wed May 26 19:15:15 2021 +0800 drm/ast: Add detect function support The existence of the connector cannot be detected, so add the detect function to support. Signed-off-by: Ainux <ainux.wang(a)gmail.com> Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210526111515.40015-1-ainux.… drivers/gpu/drm/ast/ast_mode.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) I confirmed that if I revert it from v5.15-rc4 (after reverting its dependent 572994bf18ff "drm/ast: Zero is missing in detect function"), the problem goes away. Full .config, dmesg attached. I can test any possible fixes... Thanks, Kim

2 2

[PATCH 0/5] Revert series "CMDQ refinement of Mediatek DRM driver"
by Chun-Kuang Hu 12 Oct '21

12 Oct '21

Commit c1ec54b7b5af ("drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb") would cause numerous mtk cmdq mailbox driver warning: WARNING: CPU: 0 PID: 0 at drivers/mailbox/mtk-cmdq-mailbox.c:198 cmdq_task_exec_done+0xb8/0xe0 So revert that patch and all the patches depend on that patch. Chun-Kuang Hu (5): Revert "drm/mediatek: Clear pending flag when cmdq packet is done" Revert "drm/mediatek: Add cmdq_handle in mtk_crtc" Revert "drm/mediatek: Detect CMDQ execution timeout" Revert "drm/mediatek: Remove struct cmdq_client" Revert "drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb" drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 157 ++++-------------------- 1 file changed, 24 insertions(+), 133 deletions(-) -- 2.25.1

2 7

[PATCH] [v5] dt-bindings: drm/msm/gpu: convert to YAML
by David Heidelberg 11 Oct '21

11 Oct '21

Conversion of text binding for Adreno GPU to the YAML format. Signed-off-by: David Heidelberg <david(a)ixit.cz> --- v2: - added compatbile description from Rob Clark - dropped reg description - reg numbers increased to 3 (since we also have uncommon cx_dbgc) - specified interconnect-names items range - defined zap-shader as an object and added it's properties - enforce 0 clocks for Andreno >= 6xx since it's defined in GMU node v3: - fix patterns (add backslash before dot) - add additional clocks - adreno@ -> gpu@ - add few const and change enum to anyOf - added clock & clock-names placeholder in non-conditional part (description) v4: - clock & clock-names - true,false instead maxItems - impl. #stream-id-cells, nvmem-cell-names, nvmem-cells - dropped requirement on firmware-name in zap_shader v5: - maxOtems -> maxItems typo fix .../devicetree/bindings/display/msm/gpu.txt | 157 --------- .../devicetree/bindings/display/msm/gpu.yaml | 302 ++++++++++++++++++ 2 files changed, 302 insertions(+), 157 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/gpu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/gpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt deleted file mode 100644 index 090dcb3fc34d..000000000000 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ /dev/null @@ -1,157 +0,0 @@ -Qualcomm adreno/snapdragon GPU - -Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or - "amd,imageon-XYZ.W", "amd,imageon" - for example: "qcom,adreno-306.0", "qcom,adreno" - Note that you need to list the less specific "qcom,adreno" (since this - is what the device is matched on), in addition to the more specific - with the chip-id. - If "amd,imageon" is used, there should be no top level msm device. -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the gpu. -- clocks: device clocks (if applicable) - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required by a3xx, a4xx and a5xx - cores: - * "core" - * "iface" - * "mem_iface" - For GMU attached devices the GPU clocks are not used and are not required. The - following devices should not list clocks: - - qcom,adreno-630.2 -- iommus: optional phandle to an adreno iommu instance -- operating-points-v2: optional phandle to the OPP operating points -- interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms - will have two paths; all others will have one path. -- interconnect-names: The names of the interconnect paths that correspond to the - interconnects property. Values must be gfx-mem and ocmem. -- qcom,gmu: For GMU attached devices a phandle to the GMU device that will - control the power for the GPU. Applicable targets: - - qcom,adreno-630.2 -- zap-shader: For a5xx and a6xx devices this node contains a memory-region that - points to reserved memory to store the zap shader that can be used to help - bring the GPU out of secure mode. -- firmware-name: optional property of the 'zap-shader' node, listing the - relative path of the device specific zap firmware. -- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and - a4xx Snapdragon SoCs. See - Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. - -Optional properties: -- #cooling-cells: The value must be 2. For details, please refer - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. - -Example 3xx/4xx: - -/ { - ... - - gpu: adreno@fdb00000 { - compatible = "qcom,adreno-330.2", - "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; - clock-names = "core", - "iface", - "mem_iface"; - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - sram = <&gpu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 0>; - #cooling-cells = <2>; - }; - - gpu_sram: ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gpu_sram: gpu-sram@0 { - reg = <0x0 0x100000>; - ranges = <0 0 0xfec00000 0x100000>; - }; - }; -}; - -Example a6xx (with GMU): - -/ { - ... - - gpu@5000000 { - compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0x5000000 0x40000>, <0x509e000 0x10>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; - - #cooling-cells = <2>; - - /* - * Look ma, no clocks! The GPU clocks and power are - * controlled entirely by the GMU - */ - - interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; - - iommus = <&adreno_smmu 0>; - - operating-points-v2 = <&gpu_opp_table>; - - interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; - interconnect-names = "gfx-mem"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-430000000 { - opp-hz = /bits/ 64 <430000000>; - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - opp-peak-kBps = <5412000>; - }; - - opp-355000000 { - opp-hz = /bits/ 64 <355000000>; - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - opp-peak-kBps = <3072000>; - }; - - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - opp-peak-kBps = <3072000>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - opp-peak-kBps = <1804000>; - }; - }; - - qcom,gmu = <&gmu>; - - zap-shader { - memory-region = <&zap_shader_region>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml new file mode 100644 index 000000000000..544e7568a35e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -0,0 +1,302 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Devicetree bindings for the Adreno or Snapdragon GPUs + +maintainers: + - Rob Clark <robdclark(a)gmail.com> + +properties: + compatible: + oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the gpu-id and patch level. + items: + - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' + - const: qcom,adreno + - description: | + The driver is parsing the compat string for Imageon to + figure out the gpu-id and patch level. + items: + - pattern: '^amd,imageon-200\.[0-1]$' + - const: amd,imageon + + clocks: true + + clock-names: true + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + maxItems: 3 + items: + enum: + - kgsl_3d0_reg_memory + - cx_mem + - cx_dbgc + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + interconnects: + minItems: 1 + maxItems: 2 + description: | + Optional phandle to an interconnect provider. See + ../interconnect/interconnect.txt for details. + Some A3xx and all A4xx platforms will have two paths; + all others will have one path. + + interconnect-names: + minItems: 1 + maxItems: 2 + items: + enum: + - gfx-mem + - ocmem + description: | + the names of the interconnect paths that correspond to + the interconnects property + + iommus: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 4 + description: | + phandles to one or more reserved on-chip SRAM regions. + phandle to the On Chip Memory (OCMEM) that's present on some a3xx and + a4xx Snapdragon SoCs. See + Documentation/devicetree/bindings/sram/qcom,ocmem.yaml + + operating-points-v2: true + opp-table: true + + power-domains: + maxItems: 1 + + zap-shader: + type: object + description: | + For a5xx and a6xx devices this node contains a memory-region that + points to reserved memory to store the zap shader that can be used to + help bring the GPU out of secure mode. + properties: + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + + firmware-name: + description: | + Default name of the firmware to load to the remote processor. + + "#cooling-cells": + const: 2 + + "#stream-id-cells": + const: 16 + + nvmem-cell-names: + maxItems: 1 + + nvmem-cells: + description: efuse registers + maxItems: 1 + + qcom,gmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + For GMU attached devices a phandle to the GMU device that will + control the power for the GPU. + + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + + then: + properties: + clocks: + minItems: 2 + maxItems: 7 + + clock-names: + items: + anyOf: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + minItems: 2 + maxItems: 7 + + required: + - clocks + - clock-names + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Since Adreno 6xx series clocks should be defined in GMU + properties: + clocks: false + clock-names: false + +examples: + - | + + // Example a3xx/4xx: + + #include <dt-bindings/clock/qcom,mmcc-msm8974.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu: gpu@fdb00000 { + compatible = "qcom,adreno-330.2", "qcom,adreno"; + + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + + clock-names = "core", "iface", "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + sram = <&gpu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 0>; + #cooling-cells = <2>; + }; + + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfec00000 0x100000>; + + gpu_sram: gpu-sram@0 { + reg = <0x0 0x100000>; + }; + }; + - | + + // Example a6xx (with GMU): + + #include <dt-bindings/clock/qcom,gpucc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; + }; + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + #cooling-cells = <2>; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <5412000>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <3072000>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3072000>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + opp-peak-kBps = <1804000>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; + }; + }; -- 2.33.0

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[PATCH 00/13] Make some spi device drivers return zero in .remove()
by Uwe Kleine-König 11 Oct '21

11 Oct '21

Hello, this series is part of my new quest to make spi remove callbacks return void. Today they return an int, but the only result of returning a non-zero value is a warning message. So it's a bad idea to return an error code in the expectation that not freeing some resources is ok then. The same holds true for i2c and platform devices which benefit en passant for a few drivers. The patches in this series address some of the spi drivers that might return non-zero and adapt them accordingly to return zero instead. For most drivers it's just about not hiding the fact that they already return zero. Given that there are quite some more patches of this type to create before I can change the spi remove callback, I suggest the respecive subsystem maintainers pick up these patches. There are no interdependencies in this series. Uwe Kleine-König (13): drm/panel: s6e63m0: Make s6e63m0_remove() return void hwmon: adt7x10: Make adt7x10_remove() return void hwmon: max31722: Warn about failure to put device in stand-by in .remove() input: adxl34xx: Make adxl34x_remove() return void input: touchscreen: tsc200x: Make tsc200x_remove() return void media: cxd2880: Eliminate dead code mfd: mc13xxx: Make mc13xxx_common_exit() return void mfd: stmpe: Make stmpe_remove() return void mfd: tps65912: Make tps65912_device_exit() return void serial: max310x: Make max310x_remove() return void serial: sc16is7xx: Make sc16is7xx_remove() return void staging: fbtft: Make fbtft_remove_common() return void tpm: st33zp24: Make st33zp24_remove() return void drivers/char/tpm/st33zp24/i2c.c | 5 +---- drivers/char/tpm/st33zp24/spi.c | 5 +---- drivers/char/tpm/st33zp24/st33zp24.c | 3 +-- drivers/char/tpm/st33zp24/st33zp24.h | 2 +- drivers/gpu/drm/panel/panel-samsung-s6e63m0-dsi.c | 3 ++- drivers/gpu/drm/panel/panel-samsung-s6e63m0-spi.c | 3 ++- drivers/gpu/drm/panel/panel-samsung-s6e63m0.c | 4 +--- drivers/gpu/drm/panel/panel-samsung-s6e63m0.h | 2 +- drivers/hwmon/adt7310.c | 3 ++- drivers/hwmon/adt7410.c | 3 ++- drivers/hwmon/adt7x10.c | 3 +-- drivers/hwmon/adt7x10.h | 2 +- drivers/hwmon/max31722.c | 8 +++++++- drivers/input/misc/adxl34x-i2c.c | 4 +++- drivers/input/misc/adxl34x-spi.c | 4 +++- drivers/input/misc/adxl34x.c | 4 +--- drivers/input/misc/adxl34x.h | 2 +- drivers/input/touchscreen/tsc2004.c | 4 +++- drivers/input/touchscreen/tsc2005.c | 4 +++- drivers/input/touchscreen/tsc200x-core.c | 4 +--- drivers/input/touchscreen/tsc200x-core.h | 2 +- drivers/media/spi/cxd2880-spi.c | 13 +------------ drivers/mfd/mc13xxx-core.c | 4 +--- drivers/mfd/mc13xxx-i2c.c | 3 ++- drivers/mfd/mc13xxx-spi.c | 3 ++- drivers/mfd/mc13xxx.h | 2 +- drivers/mfd/stmpe-i2c.c | 4 +++- drivers/mfd/stmpe-spi.c | 4 +++- drivers/mfd/stmpe.c | 4 +--- drivers/mfd/stmpe.h | 2 +- drivers/mfd/tps65912-core.c | 4 +--- drivers/mfd/tps65912-i2c.c | 4 +++- drivers/mfd/tps65912-spi.c | 4 +++- drivers/staging/fbtft/fbtft-core.c | 8 +------- drivers/staging/fbtft/fbtft.h | 6 ++++-- drivers/tty/serial/max310x.c | 7 +++---- drivers/tty/serial/sc16is7xx.c | 10 +++++++--- include/linux/mfd/tps65912.h | 2 +- 38 files changed, 77 insertions(+), 81 deletions(-) base-commit: 9e1ff307c779ce1f0f810c7ecce3d95bbae40896 -- 2.30.2

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dri-devel October 2021