dri-devel February 2021

dri-devel@lists.freedesktop.org

314 participants
684 discussions

[PATCH 1/2] drm/bridge: dw-hdmi: Add DT binding to disable hotplug detect
by Mykyta Poturai 08 Feb '21

08 Feb '21

Add "disable-hpd" boolean binding for the device tree. When this option is turned on HPD-related IRQ is disabled and it is assumed that the HDMI connector is connected all the time. This may be useful in systems where it is impossible or undesirable to connect the HPD pin, or the connection is broken. Signed-off-by: Mykyta Poturai <ddone(a)aruko.org> --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 0c79a9ba48bb..4ca0ac130beb 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -194,6 +194,7 @@ struct dw_hdmi { unsigned int audio_cts; unsigned int audio_n; bool audio_enable; + bool disable_hpd; unsigned int reg_shift; struct regmap *regm; @@ -1559,7 +1560,7 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) { - return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? + return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD || hdmi->disable_hpd ? connector_status_connected : connector_status_disconnected; } EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); @@ -1585,6 +1586,10 @@ void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) * Configure the PHY RX SENSE and HPD interrupts polarities and clear * any pending interrupt. */ + + if (hdmi->disable_hpd) + return; + hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, HDMI_IH_PHY_STAT0); @@ -3212,6 +3217,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, mutex_init(&hdmi->cec_notifier_mutex); spin_lock_init(&hdmi->audio_lock); + if (of_property_read_bool(np, "disable-hpd")) { + dev_info(hdmi->dev, "Disabling HPD\n"); + hdmi->disable_hpd = true; + } ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); if (ddc_node) { hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); -- 2.30.0

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[PATCH v2 0/3] Add check for max clock rate in mode_valid
by Jitao Shi 08 Feb '21

08 Feb '21

Changes since v1: - fix build err. Jitao Shi (3): drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid drm/mediatek: mtk_dpi: Add dpi config for mt8192 dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi .../display/mediatek/mediatek,dpi.yaml | 1 + drivers/gpu/drm/mediatek/mtk_dpi.c | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) -- 2.25.1

1 3

[pull] drm/msm: msm-next for 5.12
by Rob Clark 07 Feb '21

07 Feb '21

Hi Dave, This time around: * a6xx speedbin support * a508, a509, a512 support * various a5xx fixes * various dpu fixes * qseed3lite support for sm8250 * dsi fix for msm8994 * mdp5 fix for framerate bug with cmd mode panels * a6xx GMU OOB race fixes that were showing up in CI * various addition and removal of semicolons * gem submit fix for legacy userspace relocs path The following changes since commit 6ee1d745b7c9fd573fba142a2efdad76a9f1cb04: Linux 5.11-rc5 (2021-01-24 16:47:14 -0800) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-next-2021-02-07 for you to fetch changes up to 182b4a2d251305201b6f9cae29067f7112f05835: drm/msm/dp: Add a missing semi-colon (2021-02-07 09:57:04 -0800) ---------------------------------------------------------------- Akhil P Oommen (1): drm/msm: Add speed-bin support to a618 gpu AngeloGioacchino Del Regno (16): drm/msm/a5xx: Allow all patchid for A540 chip drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs drm/msm/a5xx: Reset VBIF before PC only on A510 and A530 drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks drm/msm/dpu: Add prog_fetch_lines_worst_case to INTF_BLK macro drm/msm/dpu: Allow specifying features and sblk in DSPP_BLK macro drm/msm/dpu: Disable autorefresh in command mode drm/msm/dpu: Correctly configure vsync tearcheck for command mode drm/msm/dpu: Remove unused call in wait_for_commit_done drm/msm/dsi_pll_10nm: Fix dividing the same numbers twice drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits assignment drm/msm/dsi_pll_10nm: Fix variable usage for pll_lockdet_rate drm/msm/dsi_pll_10nm: Convert pr_err prints to DRM_DEV_ERROR Bernard Zhao (1): drm/msm: remove unneeded variable: "rc" Dmitry Baryshkov (1): drm/msm/dpu1: add support for qseed3lite used on sm8250 Eric Anholt (3): drm/msm: Fix race of GPU init vs timestamp power management. drm/msm: Fix races managing the OOB state for timestamp vs timestamps. drm/msm: Clean up GMU OOB set/clear handling. Iskren Chernev (2): drm/msm: Fix MSM_INFO_GET_IOVA with carveout drm/msm/mdp5: Fix wait-for-commit for cmd panels Jiapeng Zhong (1): drm/msm: remove redundant NULL check Judy Hsiao (1): drm/msm/dp: trigger unplug event in msm_dp_display_disable Konrad Dybcio (5): drm/msm/a5xx: Fix VPC protect value in gpu_write() drm/msm/a5xx: Disable flat shading optimization drm/msm/a5xx: Disable UCHE global filter drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY) drm/msm/disp/mdp5: mdp5_cfg: Fix msm8974v2 max_clk Kuogee Hsieh (2): drm/msm/dp: unplug interrupt missed after irq_hpd handler drm/msm/dp: reset dp controller only at boot up and pm_resume Rob Clark (1): drm/msm: Fix legacy relocs path Sai Prakash Ranjan (2): drm/msm: Add proper checks for GPU LLCC support drm/msm/a6xx: Create an A6XX GPU specific address space Stephen Boyd (2): drm/msm/kms: Make a lock_class_key for each crtc mutex drm/msm/dp: Add a missing semi-colon Xu Wang (2): drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c: Remove unneeded semicolon drm/msm/dp/dp_ctrl: Remove unneeded semicolon drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 195 ++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a5xx_power.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 105 ++++++----- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 49 ++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 139 ++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 + drivers/gpu/drm/msm/adreno/adreno_device.c | 54 +++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 ++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 90 ++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 ++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 26 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 73 +++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1 + drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +- drivers/gpu/drm/msm/dp/dp_aux.c | 7 - drivers/gpu/drm/msm/dp/dp_catalog.c | 24 +++ drivers/gpu/drm/msm/dp/dp_ctrl.c | 15 +- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++- drivers/gpu/drm/msm/dp/dp_panel.c | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 2 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 21 +-- drivers/gpu/drm/msm/msm_drv.c | 3 +- drivers/gpu/drm/msm/msm_gem.c | 3 +- drivers/gpu/drm/msm/msm_gem_submit.c | 2 + drivers/gpu/drm/msm/msm_kms.h | 8 +- 36 files changed, 803 insertions(+), 219 deletions(-)

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[PATCH v15] staging: fbtft: add tearing signal detect
by Carlis 07 Feb '21

07 Feb '21

From: Carlis <zhangxuezhi1(a)yulong.com> For st7789v IC, when we need continuous full screen refresh, it is best to wait for the tearing effect line signal to arrive to avoid screen tearing. Signed-off-by: Carlis <zhangxuezhi1(a)yulong.com> --- v15: change ret value return logic in write_vmem. v14: change to define TE completion and TE irq only in st7789v. v13: change TE completion to par data struct member and add a new function to deal te gpio request, add new write_vmem function. v12: change dev_err to dev_err_probe and add space in comments start, and delete te_mutex, change te wait logic. v11: remove devm_gpio_put and change a dev_err to dev_info. v10: additional notes. v9: change pr_* to dev_*. v8: delete a log line. v7: return error value when request fail. v6: add te gpio request fail deal logic. v5: fix log print. v4: modify some code style and change te irq set function name. v3: modify author and signed-off-by name. v2: add release te gpio after irq request fail. --- drivers/staging/fbtft/fb_st7789v.c | 115 +++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/staging/fbtft/fb_st7789v.c b/drivers/staging/fbtft/fb_st7789v.c index 3a280cc..abe9395 100644 --- a/drivers/staging/fbtft/fb_st7789v.c +++ b/drivers/staging/fbtft/fb_st7789v.c @@ -7,9 +7,13 @@ #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/completion.h> #include <linux/module.h> + #include <video/mipi_display.h> #include "fbtft.h" @@ -66,6 +70,62 @@ enum st7789v_command { #define MADCTL_MX BIT(6) /* bitmask for column address order */ #define MADCTL_MY BIT(7) /* bitmask for page address order */ +/* 60Hz for 16.6ms, configured as 2*16.6ms */ +#define PANEL_TE_TIMEOUT_MS 33 + +static struct completion panel_te; /* completion for panel TE line */ +static int irq_te; /* Linux IRQ for LCD TE line */ + +static irqreturn_t panel_te_handler(int irq, void *data) +{ + complete(&panel_te); + return IRQ_HANDLED; +} + +/* + * init_tearing_effect_line() - init tearing effect line. + * @par: FBTFT parameter object. + * + * Return: 0 on success, or a negative error code otherwise. + */ +static int init_tearing_effect_line(struct fbtft_par *par) +{ + struct device *dev = par->info->device; + struct gpio_desc *te; + int rc, irq; + + te = gpiod_get_optional(dev, "te", GPIOD_IN); + if (IS_ERR(te)) + return dev_err_probe(dev, PTR_ERR(te), "Failed to request te GPIO\n"); + + /* if te is NULL, indicating no configuration, directly return success */ + if (!te) { + irq_te = 0; + return 0; + } + + irq = gpiod_to_irq(te); + + /* GPIO is locked as an IRQ, we may drop the reference */ + gpiod_put(te); + + if (irq < 0) + return irq; + + irq_te = irq; + init_completion(&panel_te); + + /* The effective state is high and lasts no more than 1000 microseconds */ + rc = devm_request_irq(dev, irq_te, panel_te_handler, + IRQF_TRIGGER_RISING, "TE_GPIO", par); + if (rc) + return dev_err_probe(dev, rc, "TE IRQ request failed.\n"); + + disable_irq_nosync(irq_te); + + return 0; +} + /** * init_display() - initialize the display controller * @@ -82,6 +142,12 @@ enum st7789v_command { */ static int init_display(struct fbtft_par *par) { + int rc; + + rc = init_tearing_effect_line(par); + if (rc) + return rc; + /* turn off sleep mode */ write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); mdelay(120); @@ -137,6 +203,10 @@ static int init_display(struct fbtft_par *par) */ write_reg(par, PWCTRL1, 0xA4, 0xA1); + /* TE line output is off by default when powering on */ + if (irq_te) + write_reg(par, MIPI_DCS_SET_TEAR_ON, 0x00); + write_reg(par, MIPI_DCS_SET_DISPLAY_ON); if (HSD20_IPS) @@ -145,6 +215,50 @@ static int init_display(struct fbtft_par *par) return 0; } +/* + * write_vmem() - write data to display. + * @par: FBTFT parameter object. + * @offset: offset from screen_buffer. + * @len: the length of data to be writte. + * + * Return: 0 on success, or a negative error code otherwise. + */ +static int write_vmem(struct fbtft_par *par, size_t offset, size_t len) +{ + struct device *dev = par->info->device; + int ret; + + if (irq_te) { + enable_irq(irq_te); + reinit_completion(&panel_te); + ret = wait_for_completion_timeout(&panel_te, + msecs_to_jiffies(PANEL_TE_TIMEOUT_MS)); + if (ret == 0) + dev_err(dev, "wait panel TE timeout\n"); + + disable_irq(irq_te); + } + + switch (par->pdata->display.buswidth) { + case 8: + ret = fbtft_write_vmem16_bus8(par, offset, len); + break; + case 9: + ret = fbtft_write_vmem16_bus9(par, offset, len); + break; + case 16: + ret = fbtft_write_vmem16_bus16(par, offset, len); + break; + default: + dev_err(dev, "Unsupported buswidth %d\n", + par->pdata->display.buswidth); + ret = 0; + break; + } + + return ret; +} + /** * set_var() - apply LCD properties like rotation and BGR mode * @@ -259,6 +373,7 @@ static int blank(struct fbtft_par *par, bool on) .gamma = HSD20_IPS_GAMMA, .fbtftops = { .init_display = init_display, + .write_vmem = write_vmem, .set_var = set_var, .set_gamma = set_gamma, .blank = blank, -- 1.9.1

1 0

Re: [Nouveau] [PATCH] drm/nouveau: bail out of nouveau_channel_new if channel init fails
by Karol Herbst 07 Feb '21

07 Feb '21

On Sun, Nov 15, 2020 at 6:43 PM Salvatore Bonaccorso <carnil(a)debian.org> wrote: > > Hi, > > On Fri, Aug 28, 2020 at 11:28:46AM +0200, Frantisek Hrbata wrote: > > Unprivileged user can crash kernel by using DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC > > ioctl. This was reported by trinity[1] fuzzer. > > > > [ 71.073906] nouveau 0000:01:00.0: crashme[1329]: channel failed to initialise, -17 > > [ 71.081730] BUG: kernel NULL pointer dereference, address: 00000000000000a0 > > [ 71.088928] #PF: supervisor read access in kernel mode > > [ 71.094059] #PF: error_code(0x0000) - not-present page > > [ 71.099189] PGD 119590067 P4D 119590067 PUD 1054f5067 PMD 0 > > [ 71.104842] Oops: 0000 [#1] SMP NOPTI > > [ 71.108498] CPU: 2 PID: 1329 Comm: crashme Not tainted 5.8.0-rc6+ #2 > > [ 71.114993] Hardware name: AMD Pike/Pike, BIOS RPK1506A 09/03/2014 > > [ 71.121213] RIP: 0010:nouveau_abi16_ioctl_channel_alloc+0x108/0x380 [nouveau] > > [ 71.128339] Code: 48 89 9d f0 00 00 00 41 8b 4c 24 04 41 8b 14 24 45 31 c0 4c 8d 4b 10 48 89 ee 4c 89 f7 e8 10 11 00 00 85 c0 75 78 48 8b 43 10 <8b> 90 a0 00 00 00 41 89 54 24 08 80 7d 3d 05 0f 86 bb 01 00 00 41 > > [ 71.147074] RSP: 0018:ffffb4a1809cfd38 EFLAGS: 00010246 > > [ 71.152526] RAX: 0000000000000000 RBX: ffff98cedbaa1d20 RCX: 00000000000003bf > > [ 71.159651] RDX: 00000000000003be RSI: 0000000000000000 RDI: 0000000000030160 > > [ 71.166774] RBP: ffff98cee776de00 R08: ffffdc0144198a08 R09: ffff98ceeefd4000 > > [ 71.173901] R10: ffff98cee7e81780 R11: 0000000000000001 R12: ffffb4a1809cfe08 > > [ 71.181214] R13: ffff98cee776d000 R14: ffff98cec519e000 R15: ffff98cee776def0 > > [ 71.188339] FS: 00007fd926250500(0000) GS:ffff98ceeac80000(0000) knlGS:0000000000000000 > > [ 71.196418] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > > [ 71.202155] CR2: 00000000000000a0 CR3: 0000000106622000 CR4: 00000000000406e0 > > [ 71.209297] Call Trace: > > [ 71.211777] ? nouveau_abi16_ioctl_getparam+0x1f0/0x1f0 [nouveau] > > [ 71.218053] drm_ioctl_kernel+0xac/0xf0 [drm] > > [ 71.222421] drm_ioctl+0x211/0x3c0 [drm] > > [ 71.226379] ? nouveau_abi16_ioctl_getparam+0x1f0/0x1f0 [nouveau] > > [ 71.232500] nouveau_drm_ioctl+0x57/0xb0 [nouveau] > > [ 71.237285] ksys_ioctl+0x86/0xc0 > > [ 71.240595] __x64_sys_ioctl+0x16/0x20 > > [ 71.244340] do_syscall_64+0x4c/0x90 > > [ 71.248110] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > [ 71.253162] RIP: 0033:0x7fd925d4b88b > > [ 71.256731] Code: Bad RIP value. > > [ 71.259955] RSP: 002b:00007ffc743592d8 EFLAGS: 00000206 ORIG_RAX: 0000000000000010 > > [ 71.267514] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fd925d4b88b > > [ 71.274637] RDX: 0000000000601080 RSI: 00000000c0586442 RDI: 0000000000000003 > > [ 71.281986] RBP: 00007ffc74359340 R08: 00007fd926016ce0 R09: 00007fd926016ce0 > > [ 71.289111] R10: 0000000000000003 R11: 0000000000000206 R12: 0000000000400620 > > [ 71.296235] R13: 00007ffc74359420 R14: 0000000000000000 R15: 0000000000000000 > > [ 71.303361] Modules linked in: rfkill sunrpc snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hda_core edac_mce_amd snd_hwdep kvm_amd snd_seq ccp snd_seq_device snd_pcm kvm snd_timer snd irqbypass soundcore sp5100_tco pcspkr crct10dif_pclmul crc32_pclmul ghash_clmulni_intel wmi_bmof joydev i2c_piix4 fam15h_power k10temp acpi_cpufreq ip_tables xfs libcrc32c sd_mod t10_pi sg nouveau video mxm_wmi i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm broadcom bcm_phy_lib ata_generic ahci drm e1000 crc32c_intel libahci serio_raw tg3 libata firewire_ohci firewire_core wmi crc_itu_t dm_mirror dm_region_hash dm_log dm_mod > > [ 71.365269] CR2: 00000000000000a0 > > > > simplified reproducer > > ---------------------------------8<---------------------------------------- > > /* > > * gcc -o crashme crashme.c > > * ./crashme /dev/dri/renderD128 > > */ > > > > struct drm_nouveau_channel_alloc { > > uint32_t fb_ctxdma_handle; > > uint32_t tt_ctxdma_handle; > > > > int channel; > > uint32_t pushbuf_domains; > > > > /* Notifier memory */ > > uint32_t notifier_handle; > > > > /* DRM-enforced subchannel assignments */ > > struct { > > uint32_t handle; > > uint32_t grclass; > > } subchan[8]; > > uint32_t nr_subchan; > > }; > > > > static struct drm_nouveau_channel_alloc channel; > > > > int main(int argc, char *argv[]) { > > int fd; > > int rv; > > > > if (argc != 2) > > die("usage: %s <dev>", 0, argv[0]); > > > > if ((fd = open(argv[1], O_RDONLY)) == -1) > > die("open %s", errno, argv[1]); > > > > if (ioctl(fd, DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC, &channel) == -1 && > > errno == EACCES) > > die("ioctl %s", errno, argv[1]); > > > > close(fd); > > > > printf("PASS\n"); > > > > return 0; > > } > > ---------------------------------8<---------------------------------------- > > > > [1] https://github.com/kernelslacker/trinity > > > > Fixes: eeaf06ac1a55 ("drm/nouveau/svm: initial support for shared virtual memory") > > Signed-off-by: Frantisek Hrbata <frantisek at hrbata.com> > > --- > > drivers/gpu/drm/nouveau/nouveau_chan.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c > > index b80e4ebf1..a7a47b325 100644 > > --- a/drivers/gpu/drm/nouveau/nouveau_chan.c > > +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c > > @@ -533,6 +533,7 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, > > if (ret) { > > NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); > > nouveau_channel_del(pchan); > > + goto done; > > } > > > > ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); > > -- > > Frantisek Hrbata > > Is this still planned to be applied? AFAICS this is the fix for > CVE-2020-25639. > If it's urgent to get it fixed, I suggest going through the Linux kernel or drm stable path. CCing dri-devel, Dave, Daniel and Ben. > Regards, > Salvatore > _______________________________________________ > Nouveau mailing list > Nouveau(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau >

3 2

[PATCH] drm/lima: Use delayed timer as default in devfreq profile
by Lukasz Luba 07 Feb '21

07 Feb '21

Devfreq framework supports 2 modes for monitoring devices. Use delayed timer as default instead of deferrable timer in order to monitor the GPU status regardless of CPU idle. Signed-off-by: Lukasz Luba <lukasz.luba(a)arm.com> --- Hi all, I've missed the Lima driver while working on Panfrost patch for fixing the issue with default devfreq framework polling mode. More about this and the patch, can be found here [1]. Regards, Lukasz Luba [1] https://lore.kernel.org/lkml/20210105164111.30122-1-lukasz.luba@arm.com/ drivers/gpu/drm/lima/lima_devfreq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c index 5686ad4aaf7c..f1c9eb3e71bd 100644 --- a/drivers/gpu/drm/lima/lima_devfreq.c +++ b/drivers/gpu/drm/lima/lima_devfreq.c @@ -81,6 +81,7 @@ static int lima_devfreq_get_dev_status(struct device *dev, } static struct devfreq_dev_profile lima_devfreq_profile = { + .timer = DEVFREQ_TIMER_DELAYED, .polling_ms = 50, /* ~3 frames */ .target = lima_devfreq_target, .get_dev_status = lima_devfreq_get_dev_status, -- 2.17.1

3 8

[PATCH v2] drm/lima: add governor data with pre-defined thresholds
by Christian Hewitt 07 Feb '21

07 Feb '21

This patch adapts the panfrost pre-defined thresholds change [0] to the lima driver to improve real-world performance. The upthreshold value has been set to ramp GPU frequency to max freq faster (compared to panfrost) to compensate for the lower overall performance of utgard devices. [0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1… Signed-off-by: Christian Hewitt <christianshewitt(a)gmail.com> --- Change since v1: increased upthreshold from 20 to 30, with a soft dependency on Lukasz delayed timer patch [0] [0] https://lore.kernel.org/lkml/20210127105121.20345-1-lukasz.luba@arm.com/ drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c index 5686ad4aaf7c..c9854315a0b5 100644 --- a/drivers/gpu/drm/lima/lima_devfreq.c +++ b/drivers/gpu/drm/lima/lima_devfreq.c @@ -163,8 +163,16 @@ int lima_devfreq_init(struct lima_device *ldev) lima_devfreq_profile.initial_freq = cur_freq; dev_pm_opp_put(opp); + /* + * Setup default thresholds for the simple_ondemand governor. + * The values are chosen based on experiments. + */ + ldevfreq->gov_data.upthreshold = 30; + ldevfreq->gov_data.downdifferential = 5; + devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, - DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &ldevfreq->gov_data); if (IS_ERR(devfreq)) { dev_err(dev, "Couldn't initialize GPU devfreq\n"); ret = PTR_ERR(devfreq); diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h index 2d9b3008ce77..b0c7c736e81a 100644 --- a/drivers/gpu/drm/lima/lima_devfreq.h +++ b/drivers/gpu/drm/lima/lima_devfreq.h @@ -4,6 +4,7 @@ #ifndef __LIMA_DEVFREQ_H__ #define __LIMA_DEVFREQ_H__ +#include <linux/devfreq.h> #include <linux/spinlock.h> #include <linux/ktime.h> @@ -18,6 +19,7 @@ struct lima_devfreq { struct opp_table *clkname_opp_table; struct opp_table *regulators_opp_table; struct thermal_cooling_device *cooling; + struct devfreq_simple_ondemand_data gov_data; ktime_t busy_time; ktime_t idle_time; -- 2.17.1

3 5

[PATCH] I was wondering why I can't set the resolution to 2560x1080, while in windows 7 I can without a problem. I looked at the radeon driver code and found it doesn't support this resolution. So I made some changes. I added the hdmi_mhz parameter. In cmdline I set radeon.hdmi_mhz=190 Only tested on the Radeon HD 5830
by Marcin Raszka 07 Feb '21

07 Feb '21

--- drivers/gpu/drm/radeon/radeon_benchmark.c | 5 ++-- drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++++++++++++++-------- drivers/gpu/drm/radeon/radeon_drv.c | 5 ++++ drivers/gpu/drm/radeon/radeon_encoders.c | 6 +++-- 4 files changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c index ac9a5ec481c3..c283b6b15925 100644 --- a/drivers/gpu/drm/radeon/radeon_benchmark.c +++ b/drivers/gpu/drm/radeon/radeon_benchmark.c @@ -30,7 +30,7 @@ #define RADEON_BENCHMARK_COPY_DMA 0 #define RADEON_BENCHMARK_ITERATIONS 1024 -#define RADEON_BENCHMARK_COMMON_MODES_N 17 +#define RADEON_BENCHMARK_COMMON_MODES_N 18 static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size, uint64_t saddr, uint64_t daddr, @@ -184,7 +184,8 @@ void radeon_benchmark(struct radeon_device *rdev, int test_number) 1680 * 1050 * 4, 1600 * 1200 * 4, 1920 * 1080 * 4, - 1920 * 1200 * 4 + 1920 * 1200 * 4, + 2560 * 1080 * 4 }; switch (test_number) { diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 607ad5620bd9..37927222f5b3 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -37,6 +37,8 @@ #include <linux/pm_runtime.h> #include <linux/vga_switcheroo.h> +extern int hdmimhz; + static int radeon_dp_handle_hpd(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); @@ -503,7 +505,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn struct mode_size { int w; int h; - } common_modes[17] = { + } common_modes[18] = { { 640, 480}, { 720, 480}, { 800, 600}, @@ -520,10 +522,11 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn {1680, 1050}, {1600, 1200}, {1920, 1080}, - {1920, 1200} + {1920, 1200}, + {2560, 1080} }; - for (i = 0; i < 17; i++) { + for (i = 0; i < 18; i++) { if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { if (common_modes[i].w > 1024 || common_modes[i].h > 768) @@ -1491,25 +1494,32 @@ static enum drm_mode_status radeon_dvi_mode_valid(struct drm_connector *connecto (mode->clock > 135000)) return MODE_CLOCK_HIGH; - if (radeon_connector->use_digital && (mode->clock > 165000)) { + if (radeon_connector->use_digital && (mode->clock > (hdmimhz * 1000))) { if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || - (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) + (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)){ + printk("MODE_CLOCK_HIHG0 %d", hdmimhz); return MODE_OK; - else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { + }else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { /* HDMI 1.3+ supports max clock of 340 Mhz */ - if (mode->clock > 340000) + if (mode->clock > 340000){ + printk("MODE_CLOCK_HIHG1 %d", hdmimhz); return MODE_CLOCK_HIGH; - else + }else{ + printk("MODE_OK1"); return MODE_OK; + } } else { + printk("MODE_CLOCK_HIHG2 %d", hdmimhz); return MODE_CLOCK_HIGH; } } /* check against the max pixel clock */ - if ((mode->clock / 10) > rdev->clock.max_pixel_clock) + if ((mode->clock / 10) > rdev->clock.max_pixel_clock){ + printk("MODE_CLOCK_HIHG3 %d", hdmimhz); return MODE_CLOCK_HIGH; + } return MODE_OK; } @@ -1809,7 +1819,7 @@ static enum drm_mode_status radeon_dp_mode_valid(struct drm_connector *connector if (mode->clock > 340000) return MODE_CLOCK_HIGH; } else { - if (mode->clock > 165000) + if (mode->clock > (hdmimhz * 1000)) return MODE_CLOCK_HIGH; } } diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index e45d7344ac2b..fce8f9ab8018 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -281,6 +281,11 @@ int radeon_cik_support = 1; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); module_param_named(cik_support, radeon_cik_support, int, 0444); +int hdmimhz = 165; +MODULE_PARM_DESC(hdmi_mhz, "set HDMI max frequency, default is 165"); +module_param_named(hdmi_mhz, hdmimhz, int, 0444); + + static struct pci_device_id pciidlist[] = { radeon_PCI_IDS }; diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 46549d5179ee..6b805bcd5726 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -35,6 +35,8 @@ #include "radeon_legacy_encoders.h" #include "atom.h" +extern int hdmimhz; + static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; @@ -389,7 +391,7 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, else return false; } else { - if (pixel_clock > 165000) + if (pixel_clock > (hdmimhz * 1000)) return true; else return false; @@ -414,7 +416,7 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, else return false; } else { - if (pixel_clock > 165000) + if (pixel_clock > (hdmimhz * 1000)) return true; else return false; -- 2.30.0

2 1

[PATCH 0/3] Add check for max clock rate in mode_valid
by Jitao Shi 07 Feb '21

07 Feb '21

Jitao Shi (3): drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid drm/mediatek: mtk_dpi: Add dpi config for mt8192 dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi .../display/mediatek/mediatek,dpi.yaml | 1 + drivers/gpu/drm/mediatek/mtk_dpi.c | 27 +++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.25.1

1 3

[PATCH] drm/amd/pm: Remove unnecessary conversion to bool
by Jiapeng Chong 07 Feb '21

07 Feb '21

Fix the following coccicheck warning: ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:907:47-52: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot<abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index d68d3df..b364862 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -904,7 +904,7 @@ static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ - return dpm_desc->SnapToDiscrete == 0 ? true : false; + return dpm_desc->SnapToDiscrete != 0; } static int sienna_cichlid_print_clk_levels(struct smu_context *smu, -- 1.8.3.1

2 1

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dri-devel February 2021