dri-devel March 2021

dri-devel@lists.freedesktop.org

326 participants
867 discussions

[PATCH i-g-t 1/5] benchmarks: Build gem_exec_tracer with meson
by Arkadiusz Hiler 25 Mar '21

25 Mar '21

Seems it has been overlooked during mesonification. It's a shared module that's meant to be LD_PRELOAD-ed to intercept EXECBUFFER2 calls for the purpose of replaying them later. Signed-off-by: Arkadiusz Hiler <arek(a)hiler.eu> --- benchmarks/meson.build | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/benchmarks/meson.build b/benchmarks/meson.build index c70e1aac..bede51dc 100644 --- a/benchmarks/meson.build +++ b/benchmarks/meson.build @@ -35,3 +35,11 @@ foreach prog : benchmark_progs install_dir : benchmarksdir, dependencies : igt_deps) endforeach + +lib_gem_exec_tracer = shared_module( + 'gem_exec_tracer', + 'gem_exec_tracer.c', + dependencies : dlsym, + include_directories : inc, + install_dir : benchmarksdir, + install: true) -- 2.31.0

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[pull] drm/msm: drm-msm-next-2021-02-07 for v5.12-rc5
by Rob Clark 25 Mar '21

25 Mar '21

Hi Dave & Daniel, (resend without missing list cc's) A few fixes for v5.12 The following changes since commit 182b4a2d251305201b6f9cae29067f7112f05835: drm/msm/dp: Add a missing semi-colon (2021-02-07 09:57:04 -0800) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git drm-msm-next-2021-02-07 for you to fetch changes up to 627dc55c273dab308303a5217bd3e767d7083ddb: drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume (2021-03-22 18:52:34 -0700) ---------------------------------------------------------------- Dmitry Baryshkov (4): drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code drm/msm/dsi_pll_7nm: Solve TODO for multiplier frac_bits assignment drm/msm/dsi_pll_7nm: Fix variable usage for pll_lockdet_rate drm/msm: fix shutdown hook in case GPU components failed to bind Douglas Anderson (1): drm/msm: Fix speed-bin support not to access outside valid memory Fabio Estevam (1): drm/msm: Fix suspend/resume on i.MX5 Jonathan Marek (1): drm/msm: fix a6xx_gmu_clear_oob Jordan Crouse (1): drm/msm: a6xx: Make sure the SQE microcode is safe Kalyan Thota (1): drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume Konrad Dybcio (1): drm/msm/adreno: a5xx_power: Don't apply A540 lm_setup to other GPUs Rob Clark (1): drm/msm: Ratelimit invalid-fence message Stephen Boyd (2): drm/msm/kms: Use nested locking for crtc lock instead of custom classes drm/msm/dp: Restore aux retry tuning logic drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 108 ++++++++++++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++-- drivers/gpu/drm/msm/dp/dp_aux.c | 7 ++ drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 2 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 6 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 11 +-- drivers/gpu/drm/msm/msm_atomic.c | 7 +- drivers/gpu/drm/msm/msm_drv.c | 12 ++++ drivers/gpu/drm/msm/msm_fence.c | 2 +- drivers/gpu/drm/msm/msm_kms.h | 8 +-- 12 files changed, 119 insertions(+), 60 deletions(-)

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[PATCH] drm/amd: Fix a typo in two different sentences
by Bhaskar Chowdhury 25 Mar '21

25 Mar '21

s/defintion/definition/ .....two different places. Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> --- drivers/gpu/drm/amd/include/atombios.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index c1d7b1d0b952..47eb84598b96 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -1987,9 +1987,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 -#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 -#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 -- 2.31.0

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[PATCH] drm/amd/amdgpu/gfx_v7_0: Trivial typo fixes
by Bhaskar Chowdhury 25 Mar '21

25 Mar '21

s/acccess/access/ s/inferface/interface/ s/sequnce/sequence/ .....two different places. s/retrive/retrieve/ s/sheduling/scheduling/ s/independant/independent/ s/wether/whether/ ......two different places. s/emmit/emit/ s/synce/sync/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index a368724c3dfc..4502b95ddf6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -1877,7 +1877,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); /* Initialize all compute VMIDs to have no GDS, GWS, or OA - acccess. These should be enabled by FW for target VMIDs. */ + access. These should be enabled by FW for target VMIDs. */ for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); @@ -2058,7 +2058,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev) * @adev: amdgpu_device pointer * * Set up the number and offset of the CP scratch registers. - * NOTE: use of CP scratch registers is a legacy inferface and + * NOTE: use of CP scratch registers is a legacy interface and * is not used by default on newer asics (r6xx+). On newer asics, * memory buffers are used for fences rather than scratch regs. */ @@ -2172,7 +2172,7 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) * @seq: sequence number * @flags: fence related flags * - * Emits a fence sequnce number on the gfx ring and flushes + * Emits a fence sequence number on the gfx ring and flushes * GPU caches. */ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, @@ -2215,7 +2215,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, * @seq: sequence number * @flags: fence related flags * - * Emits a fence sequnce number on the compute ring and flushes + * Emits a fence sequence number on the compute ring and flushes * GPU caches. */ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, @@ -2245,14 +2245,14 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring * * @ring: amdgpu_ring structure holding ring information - * @job: job to retrive vmid from + * @job: job to retrieve vmid from * @ib: amdgpu indirect buffer object * @flags: options (AMDGPU_HAVE_CTX_SWITCH) * * Emits an DE (drawing engine) or CE (constant engine) IB * on the gfx ring. IBs are usually generated by userspace * acceleration drivers and submitted to the kernel for - * sheduling on the ring. This function schedules the IB + * scheduling on the ring. This function schedules the IB * on the gfx ring for execution by the GPU. */ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, @@ -2402,7 +2402,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) /* * CP. - * On CIK, gfx and compute now have independant command processors. + * On CIK, gfx and compute now have independent command processors. * * GFX * Gfx consists of a single ring and can process both gfx jobs and @@ -2630,7 +2630,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) ring->wptr = 0; WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); @@ -2985,7 +2985,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; mqd->cp_hqd_pq_rptr_report_addr_hi = @@ -3198,7 +3198,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) /** * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP * - * @ring: the ring to emmit the commands to + * @ring: the ring to emit the commands to * * Sync the command pipeline with the PFP. E.g. wait for everything * to be completed. @@ -3220,7 +3220,7 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 4); /* poll interval */ if (usepfp) { - /* synce CE with ME to prevent CE fetch CEIB before context switch done */ + /* sync CE with ME to prevent CE fetch CEIB before context switch done */ amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); -- 2.30.1

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[PATCH V2] drm/radeon/r600_cs: Few typo fixes
by Bhaskar Chowdhury 25 Mar '21

25 Mar '21

s/miror/mirror/ s/needind/needing/ s/informations/information/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> --- Changes from V1: Randy's finding incorporated ,i.e in one place,informations->information Adjusted the subject line accordingly drivers/gpu/drm/radeon/r600_cs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 34b7c6f16479..8be4799a98ef 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -38,7 +38,7 @@ extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, struct r600_cs_track { - /* configuration we miror so that we use same code btw kms/ums */ + /* configuration we mirror so that we use same code btw kms/ums */ u32 group_size; u32 nbanks; u32 npipes; @@ -963,7 +963,7 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p, * * This function will test against r600_reg_safe_bm and return 0 * if register is safe. If register is not flag as safe this function - * will test it against a list of register needind special handling. + * will test it against a list of register needing special handling. */ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) { @@ -2336,7 +2336,7 @@ int r600_cs_parse(struct radeon_cs_parser *p) /** * r600_dma_cs_next_reloc() - parse next reloc * @p: parser structure holding parsing context. - * @cs_reloc: reloc informations + * @cs_reloc: reloc information * * Return the next reloc, do bo validation and compute * GPU offset using the provided start. -- 2.30.1

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[PATCH] amdgpu: securedisplay: simplify i2c hexdump output
by Arnd Bergmann 25 Mar '21

25 Mar '21

From: Arnd Bergmann <arnd(a)arndb.de> A previous fix I did left a rather complicated loop in amdgpu_securedisplay_debugfs_write() for what could be expressed in a simple sprintf, as Rasmus pointed out. This drops the leading 0x for each byte, but is otherwise much nicer. Suggested-by: Rasmus Villemoes <linux(a)rasmusvillemoes.dk> Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c index 69d7f6bff5d4..fc3ddd7aa6f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c @@ -92,9 +92,7 @@ static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __u struct drm_device *dev = adev_to_drm(adev); uint32_t phy_id; uint32_t op; - int i; char str[64]; - char i2c_output[256]; int ret; if (*pos || size > sizeof(str) - 1) @@ -136,12 +134,9 @@ static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __u ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); if (!ret) { if (securedisplay_cmd->status == TA_SECUREDISPLAY_STATUS__SUCCESS) { - int pos = 0; - memset(i2c_output, 0, sizeof(i2c_output)); - for (i = 0; i < TA_SECUREDISPLAY_I2C_BUFFER_SIZE; i++) - pos += sprintf(i2c_output + pos, " 0x%X", - securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf[i]); - dev_info(adev->dev, "SECUREDISPLAY: I2C buffer out put is :%s\n", i2c_output); + dev_info(adev->dev, "SECUREDISPLAY: I2C buffer out put is: %*ph\n", + TA_SECUREDISPLAY_I2C_BUFFER_SIZE, + securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf); } else { psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); } -- 2.29.2

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[PATCH v5 1/2] dt-bindings: display: bridge: Add Chipone ICN6211 bindings
by Jagan Teki 25 Mar '21

25 Mar '21

ICN6211 is MIPI-DSI to RGB Converter bridge from Chipone. It has a flexible configuration of MIPI DSI signal input and produces RGB565, RGB666, RGB888 output format. Add dt-bingings for it. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> Reviewed-by: Robert Foss <robert.foss(a)linaro.org> Reviewed-by: Rob Herring <robh(a)kernel.org> --- Changes for v5: - rebase drm-misc-next - collect Rob, Robert review tags Changes for v4: - fixed Laurent comments - added regulators - replace reset with EN - fixed warnings pointed by Robert Changes for v3: - updated to new dt-bindings style .../display/bridge/chipone,icn6211.yaml | 99 +++++++++++++++++++ MAINTAINERS | 5 + 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml new file mode 100644 index 000000000000..62c3bd4cb28d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge + +maintainers: + - Jagan Teki <jagan(a)amarulasolutions.com> + +description: | + ICN6211 is MIPI-DSI to RGB Converter bridge from chipone. + + It has a flexible configuration of MIPI DSI signal input and + produce RGB565, RGB666, RGB888 output format. + +properties: + compatible: + enum: + - chipone,icn6211 + + reg: + maxItems: 1 + description: virtual channel number of a DSI peripheral + + enable-gpios: + description: Bridge EN pin, chip is reset when EN is low. + + vdd1-supply: + description: A 1.8V/2.5V/3.3V supply that power the MIPI RX. + + vdd2-supply: + description: A 1.8V/2.5V/3.3V supply that power the PLL. + + vdd3-supply: + description: A 1.8V/2.5V/3.3V supply that power the RGB output. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DSI input + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DPI output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + bridge@0 { + compatible = "chipone,icn6211"; + reg = <0>; + enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 4b705ba51c54..b9d11101d060 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5568,6 +5568,11 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml F: drivers/gpu/drm/panel/panel-boe-himax8279d.c +DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml + DRM DRIVER FOR FARADAY TVE200 TV ENCODER M: Linus Walleij <linus.walleij(a)linaro.org> S: Maintained -- 2.25.1

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[PATCH] drm: bridge: convert sysfs sprintf/snprintf family to sysfs_emit
by Jiapeng Chong 25 Mar '21

25 Mar '21

Fix the following coccicheck warning: drivers/gpu/drm/bridge/lontium-lt9611uxc.c:858:8-16: WARNING: use scnprintf or sprintf. Reported-by: Abaci Robot<abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index fee2795..3cac16d 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -855,7 +855,7 @@ static ssize_t lt9611uxc_firmware_show(struct device *dev, struct device_attribu { struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev); - return snprintf(buf, PAGE_SIZE, "%02x\n", lt9611uxc->fw_version); + return sysfs_emit(buf, "%02x\n", lt9611uxc->fw_version); } static DEVICE_ATTR_RW(lt9611uxc_firmware); -- 1.8.3.1

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[PATCH drm/amdgpu 0/2] Convert sysfs sprintf/snprintf family to sysfs_emit
by Tian Tao 25 Mar '21

25 Mar '21

Use the generic sysfs_emit() function to take place of snprintf/scnprintf, to avoid buffer overrun. Tian Tao (2): drm/amdgpu: Convert sysfs sprintf/snprintf family to sysfs_emit drm/amd/pm: Convert sysfs sprintf/snprintf family to sysfs_emit drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 32 +++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 +- drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 2 +- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 88 ++++++++++++++-------------- 9 files changed, 73 insertions(+), 79 deletions(-) -- 2.7.4

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[PATCH] drm/radeon/radeon_pm: Convert sysfs sprintf/snprintf family to sysfs_emit
by Tian Tao 25 Mar '21

25 Mar '21

Fix the following coccicheck warning: drivers/gpu//drm/radeon/radeon_pm.c:521:9-17: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:475:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:418:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:363:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:734:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:688:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:704:8-16: WARNING: use scnprintf or sprintf drivers/gpu//drm/radeon/radeon_pm.c:755:8-16: WARNING: use scnprintf or sprintf Signed-off-by: Tian Tao <tiantao6(a)hisilicon.com> --- drivers/gpu/drm/radeon/radeon_pm.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 1995dad..dd56fcd 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -361,11 +361,10 @@ static ssize_t radeon_get_pm_profile(struct device *dev, struct radeon_device *rdev = ddev->dev_private; int cp = rdev->pm.profile; - return snprintf(buf, PAGE_SIZE, "%s\n", - (cp == PM_PROFILE_AUTO) ? "auto" : - (cp == PM_PROFILE_LOW) ? "low" : - (cp == PM_PROFILE_MID) ? "mid" : - (cp == PM_PROFILE_HIGH) ? "high" : "default"); + return sysfs_emit(buf, "%s\n", (cp == PM_PROFILE_AUTO) ? "auto" : + (cp == PM_PROFILE_LOW) ? "low" : + (cp == PM_PROFILE_MID) ? "mid" : + (cp == PM_PROFILE_HIGH) ? "high" : "default"); } static ssize_t radeon_set_pm_profile(struct device *dev, @@ -416,9 +415,8 @@ static ssize_t radeon_get_pm_method(struct device *dev, struct radeon_device *rdev = ddev->dev_private; int pm = rdev->pm.pm_method; - return snprintf(buf, PAGE_SIZE, "%s\n", - (pm == PM_METHOD_DYNPM) ? "dynpm" : - (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); + return sysfs_emit(buf, "%s\n", (pm == PM_METHOD_DYNPM) ? "dynpm" : + (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); } static ssize_t radeon_set_pm_method(struct device *dev, @@ -473,9 +471,9 @@ static ssize_t radeon_get_dpm_state(struct device *dev, struct radeon_device *rdev = ddev->dev_private; enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; - return snprintf(buf, PAGE_SIZE, "%s\n", - (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : - (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); + return sysfs_emit(buf, "%s\n", + (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : + (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); } static ssize_t radeon_set_dpm_state(struct device *dev, @@ -519,11 +517,11 @@ static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, if ((rdev->flags & RADEON_IS_PX) && (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) - return snprintf(buf, PAGE_SIZE, "off\n"); + return sysfs_emit(buf, "off\n"); - return snprintf(buf, PAGE_SIZE, "%s\n", - (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : - (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); + return sysfs_emit(buf, "%s\n", + (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : + (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); } static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, @@ -686,7 +684,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev, else temp = 0; - return snprintf(buf, PAGE_SIZE, "%d\n", temp); + return sysfs_emit(buf, "%d\n", temp); } static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, @@ -702,7 +700,7 @@ static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, else temp = rdev->pm.dpm.thermal.max_temp; - return snprintf(buf, PAGE_SIZE, "%d\n", temp); + return sysfs_emit(buf, "%d\n", temp); } static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); @@ -732,7 +730,7 @@ static ssize_t radeon_hwmon_show_sclk(struct device *dev, for hwmon */ sclk *= 10000; - return snprintf(buf, PAGE_SIZE, "%u\n", sclk); + return sysfs_emit(buf, "%u\n", sclk); } static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL, @@ -753,7 +751,7 @@ static ssize_t radeon_hwmon_show_vddc(struct device *dev, if (rdev->asic->dpm.get_current_vddc) vddc = rdev->asic->dpm.get_current_vddc(rdev); - return snprintf(buf, PAGE_SIZE, "%u\n", vddc); + return sysfs_emit(buf, "%u\n", vddc); } static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL, -- 2.7.4

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dri-devel March 2021