dri-devel March 2021

dri-devel@lists.freedesktop.org

326 participants
867 discussions

Re: [v3] drm: rockchip: hdmi: enable higher resolutions than FHD
by Yann Dirson 11 Mar '21

11 Mar '21

Vicente wrote: > This patch series enable a QHD HDMI monitor to work at native resolution. > Tested on a Sapphire board with RK3399 connected to a Q27q-10 monitor at 2560x1440@60 Which kernel did you test this patch series on ? I am trying to get this to work on our rk3999 hardware, with a Dell s2719dgf with 2560x1440@60 and 2560x1440@144, both of which do work with Rockchip's 4.4 branch. If I'm applying this patch to 5.10.18, everything breaks: - the newly-shown 2560x1440 mode is selected by default, but dclk_vop0 is set to 200000 not 241500, and screen stays black - if I switch to 1920x1080 with xrandr I get no video output either - if then I request to switch back to 2560x1440, I can see dclk_vop0 getting set back to 200000, and after a couple of seconds get something like the following, freezing the board: [ 97.504469] rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1 [ 98.528471] rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1 [ 99.552469] rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1 [ 100.576469] rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1 [ 101.600468] rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1 [ 101.601011] cpu cpu4: _set_opp_voltage: failed to set voltage (1200000 1200000 1200000 mV): -110 [ 101.601793] cpufreq: __target_index: Failed to change cpu frequency: -110 [ 117.496429] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [ 117.496975] rcu: 0-...0: (10 ticks this GP) idle=bf6/1/0x4000000000000002 softirq=716/718 fqs=415 [ 117.497765] rcu: 5-...0: (6 ticks this GP) idle=916/1/0x4000000000000000 softirq=613/614 fqs=415 [ 117.498547] (detected by 2, t=5252 jiffies, g=677, q=6) It also tends to cause timeouts right on boot afterwards if I don't leave the board unplugged for a few seconds. If I apply the same patch to 5.4.88, the clock rate when switching to 1080p gets a value you may have seen yourself given your previous patches, and the screen does not get the signal (and I don't even need to switch back to 1440p to hang the platform): root@shadow-ghost:~# cat /sys/kernel/debug/clk/dclk_vop0/clk_rate 148500999 root@shadow-ghost:~# [ 60.986455] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [ 60.987001] rcu: 0-...0: (4 ticks this GP) idle=2ce/1/0x4000000000000002 softirq=513/513 fqs=2625 [ 60.987791] rcu: 2-...0: (4 ticks this GP) idle=862/1/0x4000000000000000 softirq=519/520 fqs=2625 [ 60.988579] (detected by 1, t=5252 jiffies, g=529, q=1) [ 60.989043] Task dump for CPU 0: [ 60.989327] irq/40-ff940000 R running task 0 161 2 0x0000002a [ 60.989945] Call trace: [ 60.990172] __switch_to+0xd8/0x120 [ 60.990482] __wake_up_common_lock+0x78/0xc0 [ 60.990857] __wake_up+0x14/0x20 [ 60.991143] netlink_broadcast_filtered+0x2f4/0x3dc [ 60.991570] netlink_broadcast+0x14/0x20 [ 60.991914] 0xffff80001180bae0 [ 60.992190] Task dump for CPU 2: [ 60.992472] udevd R running task 0 170 1 0x00000002 [ 60.993088] Call trace: [ 60.993306] __switch_to+0xd8/0x120 [ 60.993612] 0xffff000079a60c80 [ 60.993889] 0xaaaafc79fcf8 [ 60.994135] 0x65 OTOH, if I apply the same patch to 4.19.177, I have no trouble switching to 1080p, and when I ask to switch back to 1440p the screen does get a signal, although it reports 1903x1440 50Hz, probably due to the clock rate getting capped to 200000. Any idea where those hangs with kernels 5.x would come from ? That could help cutting down bisect time on this :) Other experiments show that dclk_vop0 on 4.4rk gets its 241500 rate from vpll (via dclk_vop0_div), but on mainline vpll apparently refuses to provide this (proposing just 148500 instead) so it is cpll of gpll which gets to provide a 200000 kHz clock. What could be the reason for this ? Best regards, -- Yann Dirson <yann(a)blade-group.com> Blade / Shadow -- http://shadow.tech

1 0

[PULL] drm-misc-fixes
by Maarten Lankhorst 11 Mar '21

11 Mar '21

drm-misc-fixes-2021-03-11: drm-misc-fixes for rc3, rebased on rc2: - Fix oops in drm_fbdev_cleanup() - unpin qxl bos created as pinned when freeing them, and make ttm only warn once on this behavior. - Use LCD management for atyfb on PPC_MAC. - Use gitlab for drm bugzilla now. - Fix ttm page pool accounting. - Zero head.surface_id correctly in qxl. - Assorted fixes for shmem helpers. - Shutdown kms poll helper in meson correctly. - Clear holes when converting compat ioctl's between 32-bits and 64-bits. The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-03-11 for you to fetch changes up to de066e116306baf3a6a62691ac63cfc0b1dabddb: drm/compat: Clear bounce structures (2021-03-11 11:11:33 +0100) ---------------------------------------------------------------- drm-misc-fixes for rc3, rebased on rc2: - Fix oops in drm_fbdev_cleanup() - unpin qxl bos created as pinned when freeing them, and make ttm only warn once on this behavior. - Use LCD management for atyfb on PPC_MAC. - Use gitlab for drm bugzilla now. - Fix ttm page pool accounting. - Zero head.surface_id correctly in qxl. - Assorted fixes for shmem helpers. - Shutdown kms poll helper in meson correctly. - Clear holes when converting compat ioctl's between 32-bits and 64-bits. ---------------------------------------------------------------- Anthony DeRossi (1): drm/ttm: Fix TTM page pool accounting Artem Lapkin (1): drm: meson_drv add shutdown function Christian König (1): drm/ttm: soften TTM warnings Colin Ian King (1): qxl: Fix uninitialised struct field head.surface_id Daniel Vetter (1): drm/compat: Clear bounce structures Gerd Hoffmann (2): drm/qxl: unpin release objects drm/qxl: fix lockdep issue in qxl_alloc_release_reserved Neil Roberts (2): drm/shmem-helper: Check for purged buffers in fault handler drm/shmem-helper: Don't remove the offset in vm_area_struct pgoff Noralf Trønnes (1): drm/shmem-helpers: vunmap: Don't put pages for dma-buf Pavel Turinský (1): MAINTAINERS: update drm bug reporting URL Randy Dunlap (2): fbdev: atyfb: always declare aty_{ld,st}_lcd() fbdev: atyfb: use LCD management functions for PPC_PMAC also Thomas Zimmermann (1): drm: Use USB controller's DMA mask when importing dmabufs Tong Zhang (1): drm/fb-helper: only unmap if buffer not null Documentation/gpu/todo.rst | 21 ++++++++++++++++ MAINTAINERS | 2 +- drivers/gpu/drm/drm_fb_helper.c | 2 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 32 +++++++++++++++++-------- drivers/gpu/drm/drm_ioc32.c | 11 +++++++++ drivers/gpu/drm/meson/meson_drv.c | 11 +++++++++ drivers/gpu/drm/qxl/qxl_display.c | 1 + drivers/gpu/drm/qxl/qxl_release.c | 12 ++++++++-- drivers/gpu/drm/tiny/gm12u320.c | 44 +++++++++++++++++++++++++++------- drivers/gpu/drm/ttm/ttm_bo.c | 8 +++++-- drivers/gpu/drm/ttm/ttm_pool.c | 4 ++-- drivers/gpu/drm/udl/udl_drv.c | 17 +++++++++++++ drivers/gpu/drm/udl/udl_drv.h | 1 + drivers/gpu/drm/udl/udl_main.c | 10 ++++++++ drivers/usb/core/usb.c | 32 +++++++++++++++++++++++++ drivers/video/fbdev/aty/atyfb.h | 3 --- drivers/video/fbdev/aty/atyfb_base.c | 9 +++---- include/linux/usb.h | 2 ++ 18 files changed, 189 insertions(+), 33 deletions(-)

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[PATCH] [variant b] drm/amdkfd: fix build error with missing AMD_IOMMU_V2
by Arnd Bergmann 11 Mar '21

11 Mar '21

From: Arnd Bergmann <arnd(a)arndb.de> Using 'imply AMD_IOMMU_V2' does not guarantee that the driver can link against the exported functions. If the GPU driver is built-in but the IOMMU driver is a loadable module, the kfd_iommu.c file is indeed built but does not work: x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_bind_process_to_device': kfd_iommu.c:(.text+0x516): undefined reference to `amd_iommu_bind_pasid' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_unbind_process': kfd_iommu.c:(.text+0x691): undefined reference to `amd_iommu_unbind_pasid' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_suspend': kfd_iommu.c:(.text+0x966): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0x97f): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0x9a4): undefined reference to `amd_iommu_free_device' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_resume': kfd_iommu.c:(.text+0xa9a): undefined reference to `amd_iommu_init_device' x86_64-linux-ld: kfd_iommu.c:(.text+0xadc): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xaff): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xc72): undefined reference to `amd_iommu_bind_pasid' x86_64-linux-ld: kfd_iommu.c:(.text+0xe08): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xe26): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xe42): undefined reference to `amd_iommu_free_device' Change the 'imply' to a weak dependency that still allows compiling in all other configurations but disallows the configuration that causes a link failure. Fixes: 64d1c3a43a6f ("drm/amdkfd: Centralize IOMMUv2 code and make it conditional") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig index f02c938f75da..d01dba2af3bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/Kconfig +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig @@ -6,7 +6,7 @@ config HSA_AMD bool "HSA kernel driver for AMD GPU devices" depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64) - imply AMD_IOMMU_V2 if X86_64 + depends on AMD_IOMMU_V2=y || DRM_AMDGPU=m select HMM_MIRROR select MMU_NOTIFIER select DRM_AMDGPU_USERPTR -- 2.29.2

6 11

[pull] amdgpu, radeon drm-fixes-5.12
by Alex Deucher 10 Mar '21

10 Mar '21

Hi Dave, Daniel, Fixes for 5.12. The following changes since commit 1aa46901ee51c1c5779b3b239ea0374a50c6d9ff: drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie (2021-03-03 23:05:16 -0500) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.12-2021-03-10 for you to fetch changes up to a5cb3c1a36376c25cd25fd3e99918dc48ac420bb: drm/amdgpu: fix S0ix handling when the CONFIG_AMD_PMC=m (2021-03-10 16:23:26 -0500) ---------------------------------------------------------------- amd-drm-fixes-5.12-2021-03-10: amdgpu: - Fix aux backlight control - Add a backlight override parameter - Various display fixes - PCIe DPM fix for vega - Polaris watermark fixes - Additional S0ix fix radeon: - Fix GEM regression - Fix AGP dependency handling ---------------------------------------------------------------- Alex Deucher (4): drm/amdgpu/display: simplify backlight setting drm/amdgpu/display: don't assert in set backlight function drm/amdgpu/display: handle aux backlight in backlight_get_brightness drm/amdgpu: fix S0ix handling when the CONFIG_AMD_PMC=m Christian König (2): drm/radeon: also init GEM funcs in radeon_gem_prime_import_sg_table drm/radeon: fix AGP dependency Dillon Varone (1): drm/amd/display: Enabled pipe harvesting in dcn30 Evan Quan (1): drm/amd/pm: correct the watermark settings for Polaris Holger Hoffstätte (2): drm/amd/display: Fix nested FPU context in dcn21_validate_bandwidth() drm/amdgpu/display: use GFP_ATOMIC in dcn21_validate_bandwidth_fp() Kenneth Feng (1): drm/amd/pm: bug fix for pcie dpm Nirmoy Das (1): drm/amdgpu: fb BO should be ttm_bo_type_device Qingqing Zhuo (1): drm/amd/display: Enable pflip interrupt upon pipe enable Sung Lee (1): drm/amd/display: Revert dram_clock_change_latency for DCN2.1 Takashi Iwai (1): drm/amd/display: Add a backlight module option Zhan Liu (1): drm/amdgpu/display: Use wm_table.entries for dcn301 calculate_wm drivers/gpu/drm/Kconfig | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 ++++++----- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 - drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 11 +++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 6 ++ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 1 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 31 +++++++ .../drm/amd/display/dc/dcn301/dcn301_resource.c | 96 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 + .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 8 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 48 +++++++++++ .../gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 66 +++++++++++++++ .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 48 ++++++----- drivers/gpu/drm/radeon/radeon.h | 2 + drivers/gpu/drm/radeon/radeon_gem.c | 4 +- drivers/gpu/drm/radeon/radeon_prime.c | 2 + 26 files changed, 353 insertions(+), 57 deletions(-)

1 0

[RFC v1 0/6] drm/edid: overhaul displayid iterator
by Jani Nikula 10 Mar '21

10 Mar '21

Iterating DisplayID is overcomplicated as it is, and it's not getting easier when we eventually add support for DisplayID from DDC 0xA4 instead of EDID extensions. Prepare by abstracting the complexities away from EDID code. Untested, let's see what our CI thinks. ;) Jani Nikula (6): drm/edid: make a number of functions, parameters and variables const drm/displayid: add separate drm_displayid.c drm/displayid: add new displayid section/block iterators drm/edid: use the new displayid iterator for detailed modes drm/edid: use the new displayid iterator for finding CEA extension drm/edid: use the new displayid iterator for tile info drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_displayid.c | 133 +++++++++++++++++++++++++ drivers/gpu/drm/drm_edid.c | 171 +++++++------------------------- include/drm/drm_displayid.h | 28 ++++-- include/drm/drm_edid.h | 3 + 5 files changed, 196 insertions(+), 141 deletions(-) create mode 100644 drivers/gpu/drm/drm_displayid.c -- 2.20.1

2 12

[PATCH] fb_defio: Remove custom address_space_operations
by Matthew Wilcox (Oracle) 10 Mar '21

10 Mar '21

There's no need to give the page an address_space. Leaving the page->mapping as NULL will cause the VM to handle set_page_dirty() the same way that it's set now, and that was the only reason to set the address_space in the first place. Signed-off-by: Matthew Wilcox (Oracle) <willy(a)infradead.org> --- drivers/video/fbdev/core/fb_defio.c | 33 ----------------------------- drivers/video/fbdev/core/fbmem.c | 4 ---- include/linux/fb.h | 3 --- 3 files changed, 40 deletions(-) diff --git a/drivers/video/fbdev/core/fb_defio.c b/drivers/video/fbdev/core/fb_defio.c index a591d291b231..1bb208b3c4bb 100644 --- a/drivers/video/fbdev/core/fb_defio.c +++ b/drivers/video/fbdev/core/fb_defio.c @@ -52,13 +52,6 @@ static vm_fault_t fb_deferred_io_fault(struct vm_fault *vmf) return VM_FAULT_SIGBUS; get_page(page); - - if (vmf->vma->vm_file) - page->mapping = vmf->vma->vm_file->f_mapping; - else - printk(KERN_ERR "no mapping available\n"); - - BUG_ON(!page->mapping); page->index = vmf->pgoff; vmf->page = page; @@ -151,17 +144,6 @@ static const struct vm_operations_struct fb_deferred_io_vm_ops = { .page_mkwrite = fb_deferred_io_mkwrite, }; -static int fb_deferred_io_set_page_dirty(struct page *page) -{ - if (!PageDirty(page)) - SetPageDirty(page); - return 0; -} - -static const struct address_space_operations fb_deferred_io_aops = { - .set_page_dirty = fb_deferred_io_set_page_dirty, -}; - int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma) { vma->vm_ops = &fb_deferred_io_vm_ops; @@ -212,14 +194,6 @@ void fb_deferred_io_init(struct fb_info *info) } EXPORT_SYMBOL_GPL(fb_deferred_io_init); -void fb_deferred_io_open(struct fb_info *info, - struct inode *inode, - struct file *file) -{ - file->f_mapping->a_ops = &fb_deferred_io_aops; -} -EXPORT_SYMBOL_GPL(fb_deferred_io_open); - void fb_deferred_io_cleanup(struct fb_info *info) { struct fb_deferred_io *fbdefio = info->fbdefio; @@ -228,13 +202,6 @@ void fb_deferred_io_cleanup(struct fb_info *info) BUG_ON(!fbdefio); cancel_delayed_work_sync(&info->deferred_work); - - /* clear out the mapping that we setup */ - for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) { - page = fb_deferred_io_page(info, i); - page->mapping = NULL; - } - mutex_destroy(&fbdefio->lock); } EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup); diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 06f5805de2de..372b52a2befa 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -1415,10 +1415,6 @@ __releases(&info->lock) if (res) module_put(info->fbops->owner); } -#ifdef CONFIG_FB_DEFERRED_IO - if (info->fbdefio) - fb_deferred_io_open(info, inode, file); -#endif out: unlock_fb_info(info); if (res) diff --git a/include/linux/fb.h b/include/linux/fb.h index ecfbcc0553a5..a8dccd23c249 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -659,9 +659,6 @@ static inline void __fb_pad_aligned_buffer(u8 *dst, u32 d_pitch, /* drivers/video/fb_defio.c */ int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma); extern void fb_deferred_io_init(struct fb_info *info); -extern void fb_deferred_io_open(struct fb_info *info, - struct inode *inode, - struct file *file); extern void fb_deferred_io_cleanup(struct fb_info *info); extern int fb_deferred_io_fsync(struct file *file, loff_t start, loff_t end, int datasync); -- 2.30.0

3 2

Re: [PATCH 14/17] iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
by Robin Murphy 10 Mar '21

10 Mar '21

On 2021-03-10 09:25, Christoph Hellwig wrote: > On Wed, Mar 10, 2021 at 10:15:01AM +0100, Christoph Hellwig wrote: >> On Thu, Mar 04, 2021 at 03:25:27PM +0000, Robin Murphy wrote: >>> On 2021-03-01 08:42, Christoph Hellwig wrote: >>>> Use explicit methods for setting and querying the information instead. >>> >>> Now that everyone's using iommu-dma, is there any point in bouncing this >>> through the drivers at all? Seems like it would make more sense for the x86 >>> drivers to reflect their private options back to iommu_dma_strict (and >>> allow Intel's caching mode to override it as well), then have >>> iommu_dma_init_domain just test !iommu_dma_strict && >>> domain->ops->flush_iotlb_all. >> >> Hmm. I looked at this, and kill off ->dma_enable_flush_queue for >> the ARM drivers and just looking at iommu_dma_strict seems like a >> very clear win. >> >> OTOH x86 is a little more complicated. AMD and intel defaul to lazy >> mode, so we'd have to change the global iommu_dma_strict if they are >> initialized. Also Intel has not only a "static" option to disable >> lazy mode, but also a "dynamic" one where it iterates structure. So >> I think on the get side we're stuck with the method, but it still >> simplifies the whole thing. > > Actually... Just mirroring the iommu_dma_strict value into > struct iommu_domain should solve all of that with very little > boilerplate code. Yes, my initial thought was to directly replace the attribute with a common flag at iommu_domain level, but since in all cases the behaviour is effectively global rather than actually per-domain, it seemed reasonable to take it a step further. This passes compile-testing for arm64 and x86, what do you think? Robin. ----->8----- Subject: [PATCH] iommu: Consolidate strict invalidation handling Now that everyone is using iommu-dma, the global invalidation policy really doesn't need to be woven through several parts of the core API and individual drivers, we can just look it up directly at the one point that we now make the flush queue decision. If the x86 drivers reflect their internal options and overrides back to iommu_dma_strict, that can become the canonical source. Signed-off-by: Robin Murphy <robin.murphy(a)arm.com> --- drivers/iommu/amd/iommu.c | 2 ++ drivers/iommu/dma-iommu.c | 8 +------- drivers/iommu/intel/iommu.c | 12 ++++++++++++ drivers/iommu/iommu.c | 35 +++++++++++++++++++++++++++-------- include/linux/iommu.h | 2 ++ 5 files changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a69a8b573e40..1db29e59d468 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1856,6 +1856,8 @@ int __init amd_iommu_init_dma_ops(void) else pr_info("Lazy IO/TLB flushing enabled\n"); + iommu_set_dma_strict(amd_iommu_unmap_flush); + return 0; } diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index af765c813cc8..789a950cc125 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -304,10 +304,6 @@ static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) cookie = container_of(iovad, struct iommu_dma_cookie, iovad); domain = cookie->fq_domain; - /* - * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE - * implies that ops->flush_iotlb_all must be non-NULL. - */ domain->ops->flush_iotlb_all(domain); } @@ -334,7 +330,6 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, struct iommu_dma_cookie *cookie = domain->iova_cookie; unsigned long order, base_pfn; struct iova_domain *iovad; - int attr; if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) return -EINVAL; @@ -371,8 +366,7 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, init_iova_domain(iovad, 1UL << order, base_pfn); if (!cookie->fq_domain && (!dev || !dev_is_untrusted(dev)) && - !iommu_domain_get_attr(domain, DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && - attr) { + domain->ops->flush_iotlb_all && !iommu_get_dma_strict()) { if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, iommu_dma_entry_dtor)) pr_warn("iova flush queue initialization failed\n"); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index b5c746f0f63b..f5b452cd1266 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4377,6 +4377,17 @@ int __init intel_iommu_init(void) down_read(&dmar_global_lock); for_each_active_iommu(iommu, drhd) { + if (!intel_iommu_strict && cap_caching_mode(iommu->cap)) { + /* + * The flush queue implementation does not perform page-selective + * invalidations that are required for efficient TLB flushes in + * virtual environments. The benefit of batching is likely to be + * much lower than the overhead of synchronizing the virtual and + * physical IOMMU page-tables. + */ + pr_warn("IOMMU batching is disabled due to virtualization"); + intel_iommu_strict = 1; + } iommu_device_sysfs_add(&iommu->iommu, NULL, intel_iommu_groups, "%s", iommu->name); @@ -4384,6 +4395,7 @@ int __init intel_iommu_init(void) } up_read(&dmar_global_lock); + iommu_set_dma_strict(intel_iommu_strict); bus_set_iommu(&pci_bus_type, &intel_iommu_ops); if (si_domain && !hw_pass_through) register_memory_notifier(&intel_iommu_memory_nb); diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 2f3399203813..80afcf50cd3c 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -69,6 +69,7 @@ static const char * const iommu_group_resv_type_string[] = { }; #define IOMMU_CMD_LINE_DMA_API BIT(0) +#define IOMMU_CMD_LINE_STRICT BIT(1) static void iommu_set_cmd_line_dma_api(void) { @@ -80,6 +81,16 @@ static bool iommu_cmd_line_dma_api(void) return !!(iommu_cmd_line & IOMMU_CMD_LINE_DMA_API); } +static void iommu_set_cmd_line_strict(void) +{ + iommu_cmd_line |= IOMMU_CMD_LINE_STRICT; +} + +static bool iommu_cmd_line_strict(void) +{ + return !!(iommu_cmd_line & IOMMU_CMD_LINE_STRICT); +} + static int iommu_alloc_default_domain(struct iommu_group *group, struct device *dev); static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, @@ -337,10 +348,25 @@ early_param("iommu.passthrough", iommu_set_def_domain_type); static int __init iommu_dma_setup(char *str) { - return kstrtobool(str, &iommu_dma_strict); + int ret = kstrtobool(str, &iommu_dma_strict); + + if (!ret) + iommu_set_cmd_line_strict(); + return ret; } early_param("iommu.strict", iommu_dma_setup); +void iommu_set_dma_strict(bool val) +{ + if (val || !iommu_cmd_line_strict()) + iommu_dma_strict = val; +} + +bool iommu_get_dma_strict(void) +{ + return iommu_dma_strict; +} + static ssize_t iommu_group_attr_show(struct kobject *kobj, struct attribute *__attr, char *buf) { @@ -1520,13 +1546,6 @@ static int iommu_group_alloc_default_domain(struct bus_type *bus, if (!group->domain) group->domain = dom; - if (!iommu_dma_strict) { - int attr = 1; - iommu_domain_set_attr(dom, - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, - &attr); - } - return 0; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index eb5e3f14c5ad..11bbfa273d98 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -495,6 +495,8 @@ extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, void *data); extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, void *data); +extern void iommu_set_dma_strict(bool val); +extern bool iommu_get_dma_strict(void); /* Window handling function prototypes */ extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, -- 2.21.0.dirty

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Re: [PATCH 4/9] drm: remove the drm file system
by Al Viro 10 Mar '21

10 Mar '21

On Tue, Mar 09, 2021 at 04:53:43PM +0100, Christoph Hellwig wrote: > Just use the generic anon_inode file system. Are you changing the lifetime rules for that module?

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Re: [PATCH 3/9] powerpc/pseries: remove the ppc-cmm file system
by Al Viro 10 Mar '21

10 Mar '21

On Tue, Mar 09, 2021 at 04:53:42PM +0100, Christoph Hellwig wrote: > Just use the generic anon_inode file system. Umm... The only problem I see here is the lifetime rules for that module, and that's not something introduced in this patchset. Said that, looks like the logics around that place is duplicated in cmm.c, vmw_balloon.c and virtion_balloon.c and I wonder if it would be better off with a helper in mm/balloon.c to be used for that setup...

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Re: dri-devel Digest, Vol 132, Issue 198
by chatzem 10 Mar '21

10 Mar '21

Sent from ProtonMail mobile -------- Original Message -------- On Mar 10, 2021, 12:10, wrote: > Send dri-devel mailing list submissions to > dri-devel(a)lists.freedesktop.org > > To subscribe or unsubscribe via the World Wide Web, visit > https://lists.freedesktop.org/mailman/listinfo/dri-devel > or, via email, send a message with subject or body 'help' to > dri-devel-request(a)lists.freedesktop.org > > You can reach the person managing the list at > dri-devel-owner(a)lists.freedesktop.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of dri-devel digest..." > > Today's Topics: > > 1. [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm > (Liu Ying) > 2. [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge > drivers for i.MX SoCs (Liu Ying) > > ---------------------------------------------------------------------- > > Message: 1 > Date: Wed, 10 Mar 2021 17:55:37 +0800 > From: Liu Ying <victor.liu(a)nxp.com> > To: dri-devel(a)lists.freedesktop.org, devicetree(a)vger.kernel.org, > linux-arm-kernel(a)lists.infradead.org, linux-kernel(a)vger.kernel.org, > linux-media(a)vger.kernel.org > Cc: airlied(a)linux.ie, daniel(a)ffwll.ch, robh+dt(a)kernel.org, > shawnguo(a)kernel.org, s.hauer(a)pengutronix.de, kernel(a)pengutronix.de, > festevam(a)gmail.com, linux-imx(a)nxp.com, mchehab(a)kernel.org, > a.hajda(a)samsung.com, narmstrong(a)baylibre.com, > Laurent.pinchart(a)ideasonboard.com, jonas(a)kwiboo.se, > jernej.skrabec(a)siol.net, kishon(a)ti.com, vkoul(a)kernel.org, > robert.foss(a)linaro.org, lee.jones(a)linaro.org > Subject: [PATCH v5 13/14] drm/bridge: imx: Add LDB support for i.MX8qm > Message-ID: <1615370138-5673-14-git-send-email-victor.liu(a)nxp.com> > Content-Type: text/plain > > This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB) > which is officially named as pixel mapper. The LDB has two channels. > Each of them supports up to 30bpp parallel input color format and can > map the input to VESA or JEIDA standards. The two channels can be used > simultaneously, either in dual mode or split mode. In dual mode, the > two channels output identical data. In split mode, channel0 outputs > odd pixels and channel1 outputs even pixels. This patch supports the > LDB single mode and split mode. > > Signed-off-by: Liu Ying <victor.liu(a)nxp.com> > --- > Note that this patch depends on the patch 'phy: Add LVDS configuration options', > which has already been sent with the following series to add Mixel combo PHY > found in i.MX8qxp: > https://www.spinics.net/lists/arm-kernel/msg879957.html > > v4->v5: > * Link with the imx-ldb-helper object. (Robert) > * Correspondingly, rename 'imx8qm-ldb.c' to 'imx8qm-ldb-drv.c'. > > v3->v4: > * No change. > > v2->v3: > * No change. > > v1->v2: > * Drop unnecessary check for maximum available LDB channels. > * Mention i.MX8qm LDB official name 'pixel mapper' in the bridge driver > and Kconfig help message. > > drivers/gpu/drm/bridge/imx/Kconfig | 9 + > drivers/gpu/drm/bridge/imx/Makefile | 3 + > drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 586 ++++++++++++++++++++++++++++ > 3 files changed, 598 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig > index 94f8db4d..3a8683f 100644 > --- a/drivers/gpu/drm/bridge/imx/Kconfig > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > @@ -1,3 +1,12 @@ > +config DRM_IMX8QM_LDB > + tristate "Freescale i.MX8QM LVDS display bridge" > + depends on OF > + depends on COMMON_CLK > + select DRM_KMS_HELPER > + help > + Choose this to enable the internal LVDS Display Bridge(LDB) found in > + Freescale i.MX8qm processor. Official name of LDB is pixel mapper. > + > config DRM_IMX8QXP_LDB > tristate "Freescale i.MX8QXP LVDS display bridge" > depends on OF > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile > index 96d5d1e..aa90ec8 100644 > --- a/drivers/gpu/drm/bridge/imx/Makefile > +++ b/drivers/gpu/drm/bridge/imx/Makefile > @@ -1,3 +1,6 @@ > +imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o > +obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o > + > imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o > obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o > > diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c > new file mode 100644 > index 00000000..6c92636 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c > @@ -0,0 +1,586 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright 2020 NXP > + */ > + > +#include <linux/clk.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_graph.h> > +#include <linux/phy/phy.h> > +#include <linux/pm_runtime.h> > +#include <linux/regmap.h> > + > +#include <drm/drm_atomic_state_helper.h> > +#include <drm/drm_bridge.h> > +#include <drm/drm_connector.h> > +#include <drm/drm_fourcc.h> > +#include <drm/drm_of.h> > +#include <drm/drm_print.h> > + > +#include "imx-ldb-helper.h" > + > +#define LDB_CH0_10BIT_EN (1 << 22) > +#define LDB_CH1_10BIT_EN (1 << 23) > +#define LDB_CH0_DATA_WIDTH_24BIT (1 << 24) > +#define LDB_CH1_DATA_WIDTH_24BIT (1 << 26) > +#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24) > +#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26) > + > +#define SS_CTRL 0x20 > +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) > +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) > +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) > +#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) > + > +#define DRIVER_NAME "imx8qm-ldb" > + > +struct imx8qm_ldb_channel { > + struct ldb_channel base; > + struct phy *phy; > +}; > + > +struct imx8qm_ldb { > + struct ldb base; > + struct device *dev; > + struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM]; > + struct clk *clk_pixel; > + struct clk *clk_bypass; > + int active_chno; > +}; > + > +static inline struct imx8qm_ldb_channel * > +base_to_imx8qm_ldb_channel(struct ldb_channel *base) > +{ > + return container_of(base, struct imx8qm_ldb_channel, base); > +} > + > +static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base) > +{ > + return container_of(base, struct imx8qm_ldb, base); > +} > + > +static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb, > + unsigned long di_clk, > + bool is_split, bool is_slave, > + struct phy_configure_opts_lvds *phy_cfg) > +{ > + phy_cfg->bits_per_lane_and_dclk_cycle = 7; > + phy_cfg->lanes = 4; > + phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk; > + phy_cfg->is_slave = is_slave; > +} > + > +static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state) > +{ > + struct ldb_channel *ldb_ch = bridge->driver_private; > + struct ldb *ldb = ldb_ch->ldb; > + struct imx8qm_ldb_channel *imx8qm_ldb_ch = > + base_to_imx8qm_ldb_channel(ldb_ch); > + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); > + struct drm_display_mode *adj = &crtc_state->adjusted_mode; > + unsigned long di_clk = adj->clock * 1000; > + bool is_split = ldb_channel_is_split_link(ldb_ch); > + union phy_configure_opts opts = { }; > + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; > + int ret; > + > + ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, > + crtc_state, conn_state); > + if (ret) > + return ret; > + > + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); > + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); > + if (ret < 0) { > + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, > + "failed to validate PHY: %d\n", ret); > + return ret; > + } > + > + if (is_split) { > + imx8qm_ldb_ch = > + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; > + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, > + phy_cfg); > + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); > + if (ret < 0) { > + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, > + "failed to validate slave PHY: %d\n", ret); > + return ret; > + } > + } > + > + return ret; > +} > + > +static void > +imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + const struct drm_display_mode *adjusted_mode) > +{ > + struct ldb_channel *ldb_ch = bridge->driver_private; > + struct ldb *ldb = ldb_ch->ldb; > + struct imx8qm_ldb_channel *imx8qm_ldb_ch = > + base_to_imx8qm_ldb_channel(ldb_ch); > + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); > + struct device *dev = imx8qm_ldb->dev; > + unsigned long di_clk = adjusted_mode->clock * 1000; > + bool is_split = ldb_channel_is_split_link(ldb_ch); > + union phy_configure_opts opts = { }; > + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; > + u32 chno = ldb_ch->chno; > + int ret; > + > + ret = pm_runtime_get_sync(dev); > + if (ret < 0) > + DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); > + > + ret = phy_init(imx8qm_ldb_ch->phy); > + if (ret < 0) > + DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); > + > + clk_set_rate(imx8qm_ldb->clk_bypass, di_clk); > + clk_set_rate(imx8qm_ldb->clk_pixel, di_clk); > + > + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); > + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); > + if (ret < 0) > + DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); > + > + if (is_split) { > + imx8qm_ldb_ch = > + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; > + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, > + phy_cfg); > + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); > + if (ret < 0) > + DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n", > + ret); > + } > + > + /* input VSYNC signal from pixel link is active low */ > + if (ldb_ch->chno == 0 || is_split) > + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; > + if (ldb_ch->chno == 1 || is_split) > + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; > + > + switch (ldb_ch->out_bus_format) { > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: > + break; > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: > + if (ldb_ch->chno == 0 || is_split) > + ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT; > + if (ldb_ch->chno == 1 || is_split) > + ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT; > + break; > + } > + > + ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); > + > + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) > + regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); > + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) > + regmap_update_bits(ldb->regmap, SS_CTRL, > + CH_VSYNC_M(chno), CH_PVSYNC(chno)); > + > + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) > + regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); > + else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) > + regmap_update_bits(ldb->regmap, SS_CTRL, > + CH_HSYNC_M(chno), CH_PHSYNC(chno)); > +} > + > +static void > +imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, > + struct drm_bridge_state *old_bridge_state) > +{ > + struct ldb_channel *ldb_ch = bridge->driver_private; > + struct ldb *ldb = ldb_ch->ldb; > + struct imx8qm_ldb_channel *imx8qm_ldb_ch = > + base_to_imx8qm_ldb_channel(ldb_ch); > + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); > + struct device *dev = imx8qm_ldb->dev; > + bool is_split = ldb_channel_is_split_link(ldb_ch); > + int ret; > + > + clk_prepare_enable(imx8qm_ldb->clk_pixel); > + clk_prepare_enable(imx8qm_ldb->clk_bypass); > + > + /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */ > + if (ldb_ch->chno == 0 || is_split) { > + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; > + ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; > + } > + if (ldb_ch->chno == 1 || is_split) { > + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; > + ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; > + } > + > + if (is_split) { > + ret = phy_power_on(imx8qm_ldb->channel[0].phy); > + if (ret) > + DRM_DEV_ERROR(dev, > + "failed to power on channel0 PHY: %d\n", > + ret); > + > + ret = phy_power_on(imx8qm_ldb->channel[1].phy); > + if (ret) > + DRM_DEV_ERROR(dev, > + "failed to power on channel1 PHY: %d\n", > + ret); > + } else { > + ret = phy_power_on(imx8qm_ldb_ch->phy); > + if (ret) > + DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); > + } > + > + ldb_bridge_enable_helper(bridge); > +} > + > +static void > +imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge, > + struct drm_bridge_state *old_bridge_state) > +{ > + struct ldb_channel *ldb_ch = bridge->driver_private; > + struct ldb *ldb = ldb_ch->ldb; > + struct imx8qm_ldb_channel *imx8qm_ldb_ch = > + base_to_imx8qm_ldb_channel(ldb_ch); > + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); > + struct device *dev = imx8qm_ldb->dev; > + bool is_split = ldb_channel_is_split_link(ldb_ch); > + int ret; > + > + ldb_bridge_disable_helper(bridge); > + > + if (is_split) { > + ret = phy_power_off(imx8qm_ldb->channel[0].phy); > + if (ret) > + DRM_DEV_ERROR(dev, > + "failed to power off channel0 PHY: %d\n", > + ret); > + ret = phy_power_off(imx8qm_ldb->channel[1].phy); > + if (ret) > + DRM_DEV_ERROR(dev, > + "failed to power off channel1 PHY: %d\n", > + ret); > + } else { > + ret = phy_power_off(imx8qm_ldb_ch->phy); > + if (ret) > + DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); > + } > + > + clk_disable_unprepare(imx8qm_ldb->clk_bypass); > + clk_disable_unprepare(imx8qm_ldb->clk_pixel); > + > + ret = pm_runtime_put(dev); > + if (ret < 0) > + DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); > +} > + > +static const u32 imx8qm_ldb_bus_output_fmts[] = { > + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, > + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, > + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, > + MEDIA_BUS_FMT_FIXED, > +}; > + > +static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) { > + if (imx8qm_ldb_bus_output_fmts[i] == fmt) > + return true; > + } > + > + return false; > +} > + > +static u32 * > +imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state, > + u32 output_fmt, > + unsigned int *num_input_fmts) > +{ > + struct drm_display_info *di; > + const struct drm_format_info *finfo; > + u32 *input_fmts; > + > + if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt)) > + return NULL; > + > + *num_input_fmts = 1; > + > + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); > + if (!input_fmts) > + return NULL; > + > + switch (output_fmt) { > + case MEDIA_BUS_FMT_FIXED: > + di = &conn_state->connector->display_info; > + > + /* > + * Look at the first bus format to determine input format. > + * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match. > + */ > + if (di->num_bus_formats) { > + finfo = drm_format_info(di->bus_formats[0]); > + > + input_fmts[0] = finfo->depth == 18 ? > + MEDIA_BUS_FMT_RGB666_1X36_CPADLO : > + MEDIA_BUS_FMT_RGB888_1X36_CPADLO; > + } else { > + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; > + } > + break; > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: > + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; > + break; > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: > + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; > + break; > + default: > + kfree(input_fmts); > + input_fmts = NULL; > + break; > + } > + > + return input_fmts; > +} > + > +static u32 * > +imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state, > + unsigned int *num_output_fmts) > +{ > + *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); > + return kmemdup(imx8qm_ldb_bus_output_fmts, > + sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL); > +} > + > +static enum drm_mode_status > +imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + struct ldb_channel *ldb_ch = bridge->driver_private; > + bool is_single = ldb_channel_is_single_link(ldb_ch); > + > + if (mode->clock > 300000) > + return MODE_CLOCK_HIGH; > + > + if (mode->clock > 150000 && is_single) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = { > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, > + .atomic_reset = drm_atomic_helper_bridge_reset, > + .mode_valid = imx8qm_ldb_bridge_mode_valid, > + .attach = ldb_bridge_attach_helper, > + .atomic_check = imx8qm_ldb_bridge_atomic_check, > + .mode_set = imx8qm_ldb_bridge_mode_set, > + .atomic_enable = imx8qm_ldb_bridge_atomic_enable, > + .atomic_disable = imx8qm_ldb_bridge_atomic_disable, > + .atomic_get_input_bus_fmts = > + imx8qm_ldb_bridge_atomic_get_input_bus_fmts, > + .atomic_get_output_bus_fmts = > + imx8qm_ldb_bridge_atomic_get_output_bus_fmts, > +}; > + > +static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb) > +{ > + struct imx8qm_ldb_channel *imx8qm_ldb_ch; > + struct ldb_channel *ldb_ch; > + struct device *dev = imx8qm_ldb->dev; > + int i, ret; > + > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { > + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; > + ldb_ch = &imx8qm_ldb_ch->base; > + > + if (!ldb_ch->is_available) > + continue; > + > + imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, > + "lvds_phy"); > + if (IS_ERR(imx8qm_ldb_ch->phy)) { > + ret = PTR_ERR(imx8qm_ldb_ch->phy); > + if (ret != -EPROBE_DEFER) > + DRM_DEV_ERROR(dev, > + "failed to get channel%d PHY: %d\n", > + i, ret); > + return ret; > + } > + } > + > + return 0; > +} > + > +static int imx8qm_ldb_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct imx8qm_ldb *imx8qm_ldb; > + struct imx8qm_ldb_channel *imx8qm_ldb_ch; > + struct ldb *ldb; > + struct ldb_channel *ldb_ch; > + struct device_node *port1, *port2; > + int pixel_order; > + int ret, i; > + > + imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL); > + if (!imx8qm_ldb) > + return -ENOMEM; > + > + imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel"); > + if (IS_ERR(imx8qm_ldb->clk_pixel)) { > + ret = PTR_ERR(imx8qm_ldb->clk_pixel); > + if (ret != -EPROBE_DEFER) > + DRM_DEV_ERROR(dev, > + "failed to get pixel clock: %d\n", ret); > + return ret; > + } > + > + imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass"); > + if (IS_ERR(imx8qm_ldb->clk_bypass)) { > + ret = PTR_ERR(imx8qm_ldb->clk_bypass); > + if (ret != -EPROBE_DEFER) > + DRM_DEV_ERROR(dev, > + "failed to get bypass clock: %d\n", ret); > + return ret; > + } > + > + imx8qm_ldb->dev = dev; > + > + ldb = &imx8qm_ldb->base; > + ldb->dev = dev; > + ldb->ctrl_reg = 0xe0; > + > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) > + ldb->channel[i] = &imx8qm_ldb->channel[i].base; > + > + ret = ldb_init_helper(ldb); > + if (ret) > + return ret; > + > + if (ldb->available_ch_cnt == 0) { > + DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); > + return 0; > + } > + > + if (ldb->available_ch_cnt == 2) { > + port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1); > + port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1); > + pixel_order = > + drm_of_lvds_get_dual_link_pixel_order(port1, port2); > + of_node_put(port1); > + of_node_put(port2); > + > + if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { > + DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n", > + pixel_order); > + return -EINVAL; > + } > + > + imx8qm_ldb->active_chno = 0; > + imx8qm_ldb_ch = &imx8qm_ldb->channel[0]; > + ldb_ch = &imx8qm_ldb_ch->base; > + ldb_ch->link_type = pixel_order; > + } else { > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { > + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; > + ldb_ch = &imx8qm_ldb_ch->base; > + > + if (ldb_ch->is_available) { > + imx8qm_ldb->active_chno = ldb_ch->chno; > + break; > + } > + } > + } > + > + ret = imx8qm_ldb_get_phy(imx8qm_ldb); > + if (ret) > + return ret; > + > + ret = ldb_find_next_bridge_helper(ldb); > + if (ret) > + return ret; > + > + platform_set_drvdata(pdev, imx8qm_ldb); > + pm_runtime_enable(dev); > + > + ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs); > + > + return ret; > +} > + > +static int imx8qm_ldb_remove(struct platform_device *pdev) > +{ > + struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev); > + struct ldb *ldb = &imx8qm_ldb->base; > + > + ldb_remove_bridge_helper(ldb); > + > + pm_runtime_disable(&pdev->dev); > + > + return 0; > +} > + > +static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev) > +{ > + return 0; > +} > + > +static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev) > +{ > + struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev); > + struct ldb *ldb = &imx8qm_ldb->base; > + > + /* disable LDB by resetting the control register to POR default */ > + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); > + > + return 0; > +} > + > +static const struct dev_pm_ops imx8qm_ldb_pm_ops = { > + SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend, > + imx8qm_ldb_runtime_resume, NULL) > +}; > + > +static const struct of_device_id imx8qm_ldb_dt_ids[] = { > + { .compatible = "fsl,imx8qm-ldb" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids); > + > +static struct platform_driver imx8qm_ldb_driver = { > + .probe = imx8qm_ldb_probe, > + .remove = imx8qm_ldb_remove, > + .driver = { > + .pm = &imx8qm_ldb_pm_ops, > + .name = DRIVER_NAME, > + .of_match_table = imx8qm_ldb_dt_ids, > + }, > +}; > +module_platform_driver(imx8qm_ldb_driver); > + > +MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); > +MODULE_AUTHOR("Liu Ying <victor.liu(a)nxp.com>"); > +MODULE_LICENSE("GPL v2"); > +MODULE_ALIAS("platform:" DRIVER_NAME); > -- > 2.7.4 > > ------------------------------ > > Message: 2 > Date: Wed, 10 Mar 2021 17:55:38 +0800 > From: Liu Ying <victor.liu(a)nxp.com> > To: dri-devel(a)lists.freedesktop.org, devicetree(a)vger.kernel.org, > linux-arm-kernel(a)lists.infradead.org, linux-kernel(a)vger.kernel.org, > linux-media(a)vger.kernel.org > Cc: airlied(a)linux.ie, daniel(a)ffwll.ch, robh+dt(a)kernel.org, > shawnguo(a)kernel.org, s.hauer(a)pengutronix.de, kernel(a)pengutronix.de, > festevam(a)gmail.com, linux-imx(a)nxp.com, mchehab(a)kernel.org, > a.hajda(a)samsung.com, narmstrong(a)baylibre.com, > Laurent.pinchart(a)ideasonboard.com, jonas(a)kwiboo.se, > jernej.skrabec(a)siol.net, kishon(a)ti.com, vkoul(a)kernel.org, > robert.foss(a)linaro.org, lee.jones(a)linaro.org > Subject: [PATCH v5 14/14] MAINTAINERS: add maintainer for DRM bridge > drivers for i.MX SoCs > Message-ID: <1615370138-5673-15-git-send-email-victor.liu(a)nxp.com> > Content-Type: text/plain > > Add myself as the maintainer of DRM bridge drivers for i.MX SoCs. > > Signed-off-by: Liu Ying <victor.liu(a)nxp.com> > --- > v4->v5: > * No change. > > v3->v4: > * No change. > > v2->v3: > * No change. > > v1->v2: > * No change. > > MAINTAINERS | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 63bd69c..6e0c019 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5892,6 +5892,16 @@ F: Documentation/devicetree/bindings/display/imx/ > F: drivers/gpu/drm/imx/ > F: drivers/gpu/ipu-v3/ > > +DRM DRIVERS FOR FREESCALE IMX BRIDGE > +M: Liu Ying <victor.liu(a)nxp.com> > +L: dri-devel(a)lists.freedesktop.org > +S: Maintained > +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml > +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml > +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml > +F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml > +F: drivers/gpu/drm/bridge/imx/ > + > DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets) > M: Patrik Jakobsson <patrik.r.jakobsson(a)gmail.com> > L: dri-devel(a)lists.freedesktop.org > -- > 2.7.4 > > ------------------------------ > > Subject: Digest Footer > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > ------------------------------ > > End of dri-devel Digest, Vol 132, Issue 198 > *******************************************

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dri-devel March 2021