dri-devel May 2021

dri-devel@lists.freedesktop.org

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807 discussions

Re: dri-devel Digest, Vol 134, Issue 221
by chatzem 10 May '21

10 May '21

Sent from ProtonMail mobile -------- Original Message -------- On May 10, 2021, 10:49, wrote: > Send dri-devel mailing list submissions to > dri-devel(a)lists.freedesktop.org > > To subscribe or unsubscribe via the World Wide Web, visit > https://lists.freedesktop.org/mailman/listinfo/dri-devel > or, via email, send a message with subject or body 'help' to > dri-devel-request(a)lists.freedesktop.org > > You can reach the person managing the list at > dri-devel-owner(a)lists.freedesktop.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of dri-devel digest..." > > Today's Topics: > > 1. Re: [v3, 4/5] drm/connector: Add a helper to attach the > colorspace property (Jernej ?krabec) > 2. Re: [PATCH v2] drm/amdgpu: Ensure that the modifier requested > is supported by plane. (youling257) > 3. Re: [PATCH V4 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 > and SN65DSI84 driver (Frieder Schrempf) > > ---------------------------------------------------------------------- > > Message: 1 > Date: Fri, 07 May 2021 16:57:04 +0200 > From: Jernej ?krabec <jernej.skrabec(a)gmail.com> > To: dri-devel(a)lists.freedesktop.org, Daniel Vetter > <daniel.vetter(a)intel.com>, David Airlie <airlied(a)linux.ie>, Maarten > Lankhorst <maarten.lankhorst(a)linux.intel.com>, Thomas Zimmermann > <tzimmermann(a)suse.de>, Maxime Ripard <maxime(a)cerno.tech>, Maxime > Ripard <maxime(a)cerno.tech> > Cc: Tim Gover <tim.gover(a)raspberrypi.com>, Neil Armstrong > <narmstrong(a)baylibre.com>, Andrzej Hajda <a.hajda(a)samsung.com>, > Laurent Pinchart <Laurent.pinchart(a)ideasonboard.com>, Phil Elwell > <phil(a)raspberrypi.com>, Dave Stevenson > <dave.stevenson(a)raspberrypi.com>, amd-gfx(a)lists.freedesktop.org, Jonas > Karlman <jonas(a)kwiboo.se>, Leo Li <sunpeng.li(a)amd.com>, > intel-gfx(a)lists.freedesktop.org, Rodrigo Vivi > <rodrigo.vivi(a)intel.com>, Jernej Skrabec <jernej.skrabec(a)siol.net>, > Dom Cobley <dom(a)raspberrypi.com>, linux-kernel(a)vger.kernel.org, Robert > Foss <robert.foss(a)linaro.org>, Alex Deucher > <alexander.deucher(a)amd.com>, Christian K?nig > <christian.koenig(a)amd.com> > Subject: Re: [v3, 4/5] drm/connector: Add a helper to attach the > colorspace property > Message-ID: <2190160.Z2YBaczauS@jernej-laptop> > Content-Type: text/plain; charset="us-ascii" > > Hi! > > Dne petek, 30. april 2021 ob 11:44:50 CEST je Maxime Ripard napisal(a): >> The intel driver uses the same logic to attach the Colorspace property >> in multiple places and we'll need it in vc4 too. Let's move that common >> code in a helper. >> >> Signed-off-by: Maxime Ripard <maxime(a)cerno.tech> >> --- >> >> Changes from v2: >> - Rebased on current drm-misc-next >> >> Changes from v1: >> - New patch >> --- > > Reviewed-by: Jernej Skrabec <jernej.skrabec(a)gmail.com> > > Best regards, > Jernej > > ------------------------------ > > Message: 2 > Date: Sun, 9 May 2021 20:17:41 +0800 > From: youling257 <youling257(a)gmail.com> > To: markyacoub(a)chromium.org > Cc: amd-gfx(a)lists.freedesktop.org, dri-devel(a)lists.freedesktop.org, > michel(a)daenzer.net, daniel(a)fooishbar.org, bas(a)basnieuwenhuizen.nl, > alexander.deucher(a)amd.com, markyacoub(a)google.com > Subject: Re: [PATCH v2] drm/amdgpu: Ensure that the modifier requested > is supported by plane. > Message-ID: <20210509121741.25858-1-youling257(a)gmail.com> > > I using amd 3400g running with android-x86, this patch is a bad commit when i use android-x86 on amdgpu. > > ------------------------------ > > Message: 3 > Date: Mon, 10 May 2021 10:48:52 +0200 > From: Frieder Schrempf <frieder.schrempf(a)kontron.de> > To: Marek Vasut <marex(a)denx.de>, dri-devel(a)lists.freedesktop.org > Cc: ch(a)denx.de, Linus Walleij <linus.walleij(a)linaro.org>, Douglas > Anderson <dianders(a)chromium.org>, Jagan Teki > <jagan(a)amarulasolutions.com>, Laurent Pinchart > <laurent.pinchart(a)ideasonboard.com>, Loic Poulain > <loic.poulain(a)linaro.org>, Philippe Schenker > <philippe.schenker(a)toradex.com>, Sam Ravnborg <sam(a)ravnborg.org>, > Stephen Boyd <swboyd(a)chromium.org>, Valentin Raevsky > <valentin(a)compulab.co.il> > Subject: Re: [PATCH V4 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 > and SN65DSI84 driver > Message-ID: <645eb495-e30e-ed70-f01a-9f3f382f2a20(a)kontron.de> > Content-Type: text/plain; charset=utf-8 > > On 08.05.21 22:22, Marek Vasut wrote: >> Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge >> and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS >> bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, >> but easy to add. >> >> The driver operates the chip via I2C bus. Currently the LVDS clock are >> always derived from DSI clock lane, which is the usual mode of operation. >> Support for clock from external oscillator is not implemented, but it is >> easy to add if ever needed. Only RGB888 pixel format is implemented, the >> LVDS666 is not supported, but could be added if needed. >> >> Reviewed-by: Linus Walleij <linus.walleij(a)linaro.org> >> Reviewed-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> >> Tested-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> Cc: Douglas Anderson <dianders(a)chromium.org> >> Cc: Jagan Teki <jagan(a)amarulasolutions.com> >> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> >> Cc: Linus Walleij <linus.walleij(a)linaro.org> >> Cc: Loic Poulain <loic.poulain(a)linaro.org> >> Cc: Philippe Schenker <philippe.schenker(a)toradex.com> >> Cc: Sam Ravnborg <sam(a)ravnborg.org> >> Cc: Stephen Boyd <swboyd(a)chromium.org> >> Cc: Valentin Raevsky <valentin(a)compulab.co.il> >> To: dri-devel(a)lists.freedesktop.org >> --- >> V2: - Use dev_err_probe() >> - Set REG_RC_RESET as volatile >> - Wait for PLL stabilization by polling REG_RC_LVDS_PLL >> - Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set >> - Add tested DSI84 support in dual-link mode >> - Correctly set VCOM >> - Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 >> datasheets, with that all the reserved bits make far more sense >> as the DSI83 and DSI84 seems to be reduced version of DSI85 >> V3: - Handle the dual-link LVDS with two port panel or bridge >> V4: - Add RB from Linus Walleij >> - Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to >> REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining >> DSI link options from DSI85 datasheet. DSI85 can do dual and 2x >> single DSI mode, but DSI85 is currently unsupported by the >> driver. Add a comment about DSI85, so that all the places which >> need to be adjusted for DSI85 are marked accordingly. >> - Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI >> - Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 >> as fallback on output bridges until they are all fixed. >> - Patch DSI bus format to fixed RGB888_1X24 instead of passing >> through the LVDS bus format. > > I just want to report that v4 now handles my panel with MEDIA_BUS_FMT_RGB888_1X7X4_SPWG correctly. Thanks for coming up with this solution. Looks good to me. > >> --- >> drivers/gpu/drm/bridge/Kconfig | 10 + >> drivers/gpu/drm/bridge/Makefile | 1 + >> drivers/gpu/drm/bridge/ti-sn65dsi83.c | 698 ++++++++++++++++++++++++++ >> 3 files changed, 709 insertions(+) >> create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c >> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig >> index e83b8ad0d71b..32204c5f25b7 100644 >> --- a/drivers/gpu/drm/bridge/Kconfig >> +++ b/drivers/gpu/drm/bridge/Kconfig >> @@ -278,6 +278,16 @@ config DRM_TI_TFP410 >> help >> Texas Instruments TFP410 DVI/HDMI Transmitter driver >> >> +config DRM_TI_SN65DSI83 >> + tristate "TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge" >> + depends on OF >> + select DRM_KMS_HELPER >> + select REGMAP_I2C >> + select DRM_PANEL >> + select DRM_MIPI_DSI >> + help >> + Texas Instruments SN65DSI83 and SN65DSI84 DSI to LVDS Bridge driver >> + >> config DRM_TI_SN65DSI86 >> tristate "TI SN65DSI86 DSI to eDP bridge" >> depends on OF >> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile >> index b00f3b2ad572..7bb4c9df0415 100644 >> --- a/drivers/gpu/drm/bridge/Makefile >> +++ b/drivers/gpu/drm/bridge/Makefile >> @@ -24,6 +24,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o >> obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o >> obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o >> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ >> +obj-$(CONFIG_DRM_TI_SN65DSI83) += ti-sn65dsi83.o >> obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o >> obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o >> obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o >> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c >> new file mode 100644 >> index 000000000000..1a0a71fbe91d >> --- /dev/null >> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c >> @@ -0,0 +1,698 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * TI SN65DSI83,84,85 driver >> + * >> + * Currently supported: >> + * - SN65DSI83 >> + * = 1x Single-link DSI ~ 1x Single-link LVDS >> + * - Supported >> + * - Single-link LVDS mode tested >> + * - SN65DSI84 >> + * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS >> + * - Supported >> + * - Dual-link LVDS mode tested >> + * - 2x Single-link LVDS mode unsupported >> + * (should be easy to add by someone who has the HW) >> + * - SN65DSI85 >> + * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS >> + * - Unsupported >> + * (should be easy to add by someone who has the HW) >> + * >> + * Copyright (C) 2021 Marek Vasut <marex(a)denx.de> >> + * >> + * Based on previous work of: >> + * Valentin Raevsky <valentin(a)compulab.co.il> >> + * Philippe Schenker <philippe.schenker(a)toradex.com> >> + */ >> + >> +#include <linux/bits.h> >> +#include <linux/clk.h> >> +#include <linux/gpio/consumer.h> >> +#include <linux/i2c.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/of_graph.h> >> +#include <linux/regmap.h> >> + >> +#include <drm/drm_atomic_helper.h> >> +#include <drm/drm_bridge.h> >> +#include <drm/drm_mipi_dsi.h> >> +#include <drm/drm_of.h> >> +#include <drm/drm_panel.h> >> +#include <drm/drm_print.h> >> +#include <drm/drm_probe_helper.h> >> + >> +/* ID registers */ >> +#define REG_ID(n) (0x00 + (n)) >> +/* Reset and clock registers */ >> +#define REG_RC_RESET 0x09 >> +#define REG_RC_RESET_SOFT_RESET BIT(0) >> +#define REG_RC_LVDS_PLL 0x0a >> +#define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) >> +#define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) >> +#define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) >> +#define REG_RC_DSI_CLK 0x0b >> +#define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) >> +#define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) >> +#define REG_RC_PLL_EN 0x0d >> +#define REG_RC_PLL_EN_PLL_EN BIT(0) >> +/* DSI registers */ >> +#define REG_DSI_LANE 0x10 >> +#define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ >> +#define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ >> +#define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ >> +#define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) >> +#define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) >> +#define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) >> +#define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) >> +#define REG_DSI_EQ 0x11 >> +#define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) >> +#define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) >> +#define REG_DSI_CLK 0x12 >> +#define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) >> +/* LVDS registers */ >> +#define REG_LVDS_FMT 0x18 >> +#define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) >> +#define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) >> +#define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) >> +#define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ >> +#define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) >> +#define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) >> +#define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) >> +#define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) >> +#define REG_LVDS_VCOM 0x19 >> +#define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) >> +#define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) >> +#define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) >> +#define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) >> +#define REG_LVDS_LANE 0x1a >> +#define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) >> +#define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) >> +#define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) >> +#define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) >> +#define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) >> +#define REG_LVDS_CM 0x1b >> +#define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) >> +#define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) >> +/* Video registers */ >> +#define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 >> +#define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 >> +#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 >> +#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 >> +#define REG_VID_CHA_SYNC_DELAY_LOW 0x28 >> +#define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 >> +#define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c >> +#define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d >> +#define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 >> +#define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 >> +#define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 >> +#define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 >> +#define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 >> +#define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a >> +#define REG_VID_CHA_TEST_PATTERN 0x3c >> +/* IRQ registers */ >> +#define REG_IRQ_GLOBAL 0xe0 >> +#define REG_IRQ_GLOBAL_IRQ_EN BIT(0) >> +#define REG_IRQ_EN 0xe1 >> +#define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) >> +#define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) >> +#define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) >> +#define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) >> +#define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) >> +#define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) >> +#define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) >> +#define REG_IRQ_STAT 0xe5 >> +#define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) >> +#define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) >> +#define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) >> +#define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) >> +#define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) >> +#define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) >> +#define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) >> + >> +enum sn65dsi83_model { >> + MODEL_SN65DSI83, >> + MODEL_SN65DSI84, >> +}; >> + >> +struct sn65dsi83 { >> + struct drm_bridge bridge; >> + struct drm_display_mode mode; >> + struct device *dev; >> + struct regmap *regmap; >> + struct device_node *host_node; >> + struct mipi_dsi_device *dsi; >> + struct drm_bridge *panel_bridge; >> + struct gpio_desc *enable_gpio; >> + int dsi_lanes; >> + bool lvds_dual_link; >> + bool lvds_dual_link_even_odd_swap; >> + bool lvds_format_24bpp; >> + bool lvds_format_jeida; >> +}; >> + >> +static const struct regmap_range sn65dsi83_readable_ranges[] = { >> + regmap_reg_range(REG_ID(0), REG_ID(8)), >> + regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), >> + regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), >> + regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), >> + regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), >> + regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, >> + REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, >> + REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), >> + regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, >> + REG_VID_CHA_SYNC_DELAY_HIGH), >> + regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, >> + REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, >> + REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, >> + REG_VID_CHA_HORIZONTAL_BACK_PORCH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, >> + REG_VID_CHA_VERTICAL_BACK_PORCH), >> + regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, >> + REG_VID_CHA_HORIZONTAL_FRONT_PORCH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, >> + REG_VID_CHA_VERTICAL_FRONT_PORCH), >> + regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), >> + regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), >> + regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), >> +}; >> + >> +static const struct regmap_access_table sn65dsi83_readable_table = { >> + .yes_ranges = sn65dsi83_readable_ranges, >> + .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), >> +}; >> + >> +static const struct regmap_range sn65dsi83_writeable_ranges[] = { >> + regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), >> + regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), >> + regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), >> + regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), >> + regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, >> + REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, >> + REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), >> + regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, >> + REG_VID_CHA_SYNC_DELAY_HIGH), >> + regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, >> + REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, >> + REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), >> + regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, >> + REG_VID_CHA_HORIZONTAL_BACK_PORCH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, >> + REG_VID_CHA_VERTICAL_BACK_PORCH), >> + regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, >> + REG_VID_CHA_HORIZONTAL_FRONT_PORCH), >> + regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, >> + REG_VID_CHA_VERTICAL_FRONT_PORCH), >> + regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), >> + regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), >> + regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), >> +}; >> + >> +static const struct regmap_access_table sn65dsi83_writeable_table = { >> + .yes_ranges = sn65dsi83_writeable_ranges, >> + .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), >> +}; >> + >> +static const struct regmap_range sn65dsi83_volatile_ranges[] = { >> + regmap_reg_range(REG_RC_RESET, REG_RC_RESET), >> + regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), >> + regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), >> +}; >> + >> +static const struct regmap_access_table sn65dsi83_volatile_table = { >> + .yes_ranges = sn65dsi83_volatile_ranges, >> + .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), >> +}; >> + >> +static const struct regmap_config sn65dsi83_regmap_config = { >> + .reg_bits = 8, >> + .val_bits = 8, >> + .rd_table = &sn65dsi83_readable_table, >> + .wr_table = &sn65dsi83_writeable_table, >> + .volatile_table = &sn65dsi83_volatile_table, >> + .cache_type = REGCACHE_RBTREE, >> + .max_register = REG_IRQ_STAT, >> +}; >> + >> +static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) >> +{ >> + return container_of(bridge, struct sn65dsi83, bridge); >> +} >> + >> +static int sn65dsi83_attach(struct drm_bridge *bridge, >> + enum drm_bridge_attach_flags flags) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + struct device *dev = ctx->dev; >> + struct mipi_dsi_device *dsi; >> + struct mipi_dsi_host *host; >> + int ret = 0; >> + >> + const struct mipi_dsi_device_info info = { >> + .type = "sn65dsi83", >> + .channel = 0, >> + .node = NULL, >> + }; >> + >> + host = of_find_mipi_dsi_host_by_node(ctx->host_node); >> + if (!host) { >> + dev_err(dev, "failed to find dsi host\n"); >> + return -EPROBE_DEFER; >> + } >> + >> + dsi = mipi_dsi_device_register_full(host, &info); >> + if (IS_ERR(dsi)) { >> + return dev_err_probe(dev, PTR_ERR(dsi), >> + "failed to create dsi device\n"); >> + } >> + >> + ctx->dsi = dsi; >> + >> + dsi->lanes = ctx->dsi_lanes; >> + dsi->format = MIPI_DSI_FMT_RGB888; >> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; >> + >> + ret = mipi_dsi_attach(dsi); >> + if (ret < 0) { >> + dev_err(dev, "failed to attach dsi to host\n"); >> + goto err_dsi_attach; >> + } >> + >> + return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, >> + &ctx->bridge, flags); >> + >> +err_dsi_attach: >> + mipi_dsi_device_unregister(dsi); >> + return ret; >> +} >> + >> +static void sn65dsi83_pre_enable(struct drm_bridge *bridge) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + >> + /* >> + * Reset the chip, pull EN line low for t_reset=10ms, >> + * then high for t_en=1ms. >> + */ >> + regcache_mark_dirty(ctx->regmap); >> + gpiod_set_value(ctx->enable_gpio, 0); >> + usleep_range(10000, 11000); >> + gpiod_set_value(ctx->enable_gpio, 1); >> + usleep_range(1000, 1100); >> +} >> + >> +static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx) >> +{ >> + /* >> + * The encoding of the LVDS_CLK_RANGE is as follows: >> + * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz >> + * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz >> + * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz >> + * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz >> + * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz >> + * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz >> + * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that >> + * the ends of the ranges are clamped to the supported range. Since >> + * sn65dsi83_mode_valid() already filters the valid modes and limits >> + * the clock to 25..154 MHz, the range calculation can be simplified >> + * as follows: >> + */ >> + int mode_clock = ctx->mode.clock; >> + >> + if (ctx->lvds_dual_link) >> + mode_clock /= 2; >> + >> + return (mode_clock - 12500) / 25000; >> +} >> + >> +static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx) >> +{ >> + /* >> + * The encoding of the CHA_DSI_CLK_RANGE is as follows: >> + * 0x00 through 0x07 - Reserved >> + * 0x08 - 40 <= DSI_CLK < 45 MHz >> + * 0x09 - 45 <= DSI_CLK < 50 MHz >> + * ... >> + * 0x63 - 495 <= DSI_CLK < 500 MHz >> + * 0x64 - 500 MHz >> + * 0x65 through 0xFF - Reserved >> + * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. >> + * The DSI clock are calculated as: >> + * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 >> + * the 2 is there because the bus is DDR. >> + */ >> + return DIV_ROUND_UP(clamp((unsigned int)ctx->mode.clock * >> + mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / >> + ctx->dsi_lanes / 2, 40000U, 500000U), 5000U); >> +} >> + >> +static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) >> +{ >> + /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ >> + unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); >> + >> + dsi_div /= ctx->dsi_lanes; >> + >> + if (!ctx->lvds_dual_link) >> + dsi_div /= 2; >> + >> + return dsi_div - 1; >> +} >> + >> +static void sn65dsi83_enable(struct drm_bridge *bridge) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + unsigned int pval; >> + u16 val; >> + int ret; >> + >> + /* Clear reset, disable PLL */ >> + regmap_write(ctx->regmap, REG_RC_RESET, 0x00); >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); >> + >> + /* Reference clock derived from DSI link clock. */ >> + regmap_write(ctx->regmap, REG_RC_LVDS_PLL, >> + REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx)) | >> + REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); >> + regmap_write(ctx->regmap, REG_DSI_CLK, >> + REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx))); >> + regmap_write(ctx->regmap, REG_RC_DSI_CLK, >> + REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); >> + >> + /* Set number of DSI lanes and LVDS link config. */ >> + regmap_write(ctx->regmap, REG_DSI_LANE, >> + REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | >> + REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) | >> + /* CHB is DSI85-only, set to default on DSI83/DSI84 */ >> + REG_DSI_LANE_CHB_DSI_LANES(3)); >> + /* No equalization. */ >> + regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); >> + >> + /* Set up sync signal polarity. */ >> + val = (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC ? >> + REG_LVDS_FMT_HS_NEG_POLARITY : 0) | >> + (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC ? >> + REG_LVDS_FMT_VS_NEG_POLARITY : 0); >> + >> + /* Set up bits-per-pixel, 18bpp or 24bpp. */ >> + if (ctx->lvds_format_24bpp) { >> + val |= REG_LVDS_FMT_CHA_24BPP_MODE; >> + if (ctx->lvds_dual_link) >> + val |= REG_LVDS_FMT_CHB_24BPP_MODE; >> + } >> + >> + /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ >> + if (ctx->lvds_format_jeida) { >> + val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; >> + if (ctx->lvds_dual_link) >> + val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; >> + } >> + >> + /* Set up LVDS output config (DSI84,DSI85) */ >> + if (!ctx->lvds_dual_link) >> + val |= REG_LVDS_FMT_LVDS_LINK_CFG; >> + >> + regmap_write(ctx->regmap, REG_LVDS_FMT, val); >> + regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); >> + regmap_write(ctx->regmap, REG_LVDS_LANE, >> + (ctx->lvds_dual_link_even_odd_swap ? >> + REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | >> + REG_LVDS_LANE_CHA_LVDS_TERM | >> + REG_LVDS_LANE_CHB_LVDS_TERM); >> + regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); >> + >> + regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, >> + &ctx->mode.hdisplay, 2); >> + regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, >> + &ctx->mode.vdisplay, 2); >> + val = 32 + 1; /* 32 + 1 pixel clock to ensure proper operation */ >> + regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &val, 2); >> + val = ctx->mode.hsync_end - ctx->mode.hsync_start; >> + regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, >> + &val, 2); >> + val = ctx->mode.vsync_end - ctx->mode.vsync_start; >> + regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, >> + &val, 2); >> + regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, >> + ctx->mode.htotal - ctx->mode.hsync_end); >> + regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, >> + ctx->mode.vtotal - ctx->mode.vsync_end); >> + regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, >> + ctx->mode.hsync_start - ctx->mode.hdisplay); >> + regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, >> + ctx->mode.vsync_start - ctx->mode.vdisplay); >> + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); >> + >> + /* Enable PLL */ >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); >> + usleep_range(3000, 4000); >> + ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, >> + pval & REG_RC_LVDS_PLL_PLL_EN_STAT, >> + 1000, 100000); >> + if (ret) { >> + dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); >> + /* On failure, disable PLL again and exit. */ >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); >> + return; >> + } >> + >> + /* Trigger reset after CSR register update. */ >> + regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); >> + >> + /* Clear all errors that got asserted during initialization. */ >> + regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); >> + regmap_write(ctx->regmap, REG_IRQ_STAT, pval); >> +} >> + >> +static void sn65dsi83_disable(struct drm_bridge *bridge) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + >> + /* Clear reset, disable PLL */ >> + regmap_write(ctx->regmap, REG_RC_RESET, 0x00); >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); >> +} >> + >> +static void sn65dsi83_post_disable(struct drm_bridge *bridge) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + >> + /* Put the chip in reset, pull EN line low. */ >> + gpiod_set_value(ctx->enable_gpio, 0); >> +} >> + >> +static enum drm_mode_status >> +sn65dsi83_mode_valid(struct drm_bridge *bridge, >> + const struct drm_display_info *info, >> + const struct drm_display_mode *mode) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + >> + /* LVDS output clock range 25..154 MHz */ >> + if (mode->clock < 25000) >> + return MODE_CLOCK_LOW; >> + if (mode->clock > 154000) >> + return MODE_CLOCK_HIGH; >> + >> + switch (info->bus_formats[0]) { >> + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: >> + ctx->lvds_format_24bpp = false; >> + ctx->lvds_format_jeida = false; >> + break; >> + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: >> + ctx->lvds_format_24bpp = true; >> + ctx->lvds_format_jeida = true; >> + break; >> + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: >> + ctx->lvds_format_24bpp = true; >> + ctx->lvds_format_jeida = false; >> + break; >> + default: >> + ctx->lvds_format_24bpp = true; >> + ctx->lvds_format_jeida = false; >> + /* >> + * Some bridges still don't set the correct LVDS bus pixel >> + * format, use SPWG24 default format until those are fixed. >> + */ >> + dev_warn(ctx->dev, >> + "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", >> + info->bus_formats[0]); >> + break; >> + } >> + >> + return MODE_OK; >> +} >> + >> +static void sn65dsi83_mode_set(struct drm_bridge *bridge, >> + const struct drm_display_mode *mode, >> + const struct drm_display_mode *adj) >> +{ >> + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); >> + u32 input_bus_format = MEDIA_BUS_FMT_RGB888_1X24; >> + struct drm_encoder *encoder = bridge->encoder; >> + struct drm_device *ddev = encoder->dev; >> + struct drm_connector *connector; >> + >> + /* The DSI format is always RGB888_1X24 */ >> + list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { >> + if (connector->encoder != encoder) >> + continue; >> + >> + drm_display_info_set_bus_formats(&connector->display_info, >> + &input_bus_format, 1); >> + } >> + >> + ctx->mode = *adj; >> +} >> + >> +static const struct drm_bridge_funcs sn65dsi83_funcs = { >> + .attach = sn65dsi83_attach, >> + .pre_enable = sn65dsi83_pre_enable, >> + .enable = sn65dsi83_enable, >> + .disable = sn65dsi83_disable, >> + .post_disable = sn65dsi83_post_disable, >> + .mode_valid = sn65dsi83_mode_valid, >> + .mode_set = sn65dsi83_mode_set, >> +}; >> + >> +static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) >> +{ >> + struct drm_bridge *panel_bridge; >> + struct device *dev = ctx->dev; >> + struct device_node *endpoint; >> + struct drm_panel *panel; >> + int ret; >> + >> + endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); >> + ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); >> + ctx->host_node = of_graph_get_remote_port_parent(endpoint); >> + of_node_put(endpoint); >> + >> + if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4) >> + return -EINVAL; >> + if (!ctx->host_node) >> + return -ENODEV; >> + >> + ctx->lvds_dual_link = false; >> + ctx->lvds_dual_link_even_odd_swap = false; >> + if (model != MODEL_SN65DSI83) { >> + struct device_node *port2, *port3; >> + int dual_link; >> + >> + port2 = of_graph_get_port_by_id(dev->of_node, 2); >> + port3 = of_graph_get_port_by_id(dev->of_node, 3); >> + dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); >> + of_node_put(port2); >> + of_node_put(port3); >> + >> + if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { >> + ctx->lvds_dual_link = true; >> + /* Odd pixels to LVDS Channel A, even pixels to B */ >> + ctx->lvds_dual_link_even_odd_swap = false; >> + } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { >> + ctx->lvds_dual_link = true; >> + /* Even pixels to LVDS Channel A, odd pixels to B */ >> + ctx->lvds_dual_link_even_odd_swap = true; >> + } >> + } >> + >> + ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge); >> + if (ret < 0) >> + return ret; >> + if (panel) { >> + panel_bridge = devm_drm_panel_bridge_add(dev, panel); >> + if (IS_ERR(panel_bridge)) >> + return PTR_ERR(panel_bridge); >> + } >> + >> + ctx->panel_bridge = panel_bridge; >> + >> + return 0; >> +} >> + >> +static int sn65dsi83_probe(struct i2c_client *client, >> + const struct i2c_device_id *id) >> +{ >> + struct device *dev = &client->dev; >> + enum sn65dsi83_model model; >> + struct sn65dsi83 *ctx; >> + int ret; >> + >> + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); >> + if (!ctx) >> + return -ENOMEM; >> + >> + ctx->dev = dev; >> + >> + if (dev->of_node) >> + model = (enum sn65dsi83_model)of_device_get_match_data(dev); >> + else >> + model = id->driver_data; >> + >> + ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW); >> + if (IS_ERR(ctx->enable_gpio)) >> + return PTR_ERR(ctx->enable_gpio); >> + >> + ret = sn65dsi83_parse_dt(ctx, model); >> + if (ret) >> + return ret; >> + >> + ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); >> + if (IS_ERR(ctx->regmap)) >> + return PTR_ERR(ctx->regmap); >> + >> + dev_set_drvdata(dev, ctx); >> + i2c_set_clientdata(client, ctx); >> + >> + ctx->bridge.funcs = &sn65dsi83_funcs; >> + ctx->bridge.of_node = dev->of_node; >> + drm_bridge_add(&ctx->bridge); >> + >> + return 0; >> +} >> + >> +static int sn65dsi83_remove(struct i2c_client *client) >> +{ >> + struct sn65dsi83 *ctx = i2c_get_clientdata(client); >> + >> + mipi_dsi_detach(ctx->dsi); >> + mipi_dsi_device_unregister(ctx->dsi); >> + drm_bridge_remove(&ctx->bridge); >> + of_node_put(ctx->host_node); >> + >> + return 0; >> +} >> + >> +static struct i2c_device_id sn65dsi83_id[] = { >> + { "ti,sn65dsi83", MODEL_SN65DSI83 }, >> + { "ti,sn65dsi84", MODEL_SN65DSI84 }, >> + {}, >> +}; >> +MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); >> + >> +static const struct of_device_id sn65dsi83_match_table[] = { >> + { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, >> + { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, >> + {}, >> +}; >> +MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); >> + >> +static struct i2c_driver sn65dsi83_driver = { >> + .probe = sn65dsi83_probe, >> + .remove = sn65dsi83_remove, >> + .id_table = sn65dsi83_id, >> + .driver = { >> + .name = "sn65dsi83", >> + .of_match_table = sn65dsi83_match_table, >> + }, >> +}; >> +module_i2c_driver(sn65dsi83_driver); >> + >> +MODULE_AUTHOR("Marek Vasut <marex(a)denx.de>"); >> +MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); >> +MODULE_LICENSE("GPL v2"); >> > > ------------------------------ > > Subject: Digest Footer > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > ------------------------------ > > End of dri-devel Digest, Vol 134, Issue 221 > *******************************************

1 0

[PATCH] drm/msm: fix warning "using plain integer as NULL pointer"
by Bernard Zhao 10 May '21

10 May '21

Fix sparse warning: drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1195:41: warning: Using plain integer as NULL pointer drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1348:32: warning: Using plain integer as NULL pointer Signed-off-by: Bernard Zhao <bernard(a)vivo.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index df7f3d3afd8b..cc5cceae80f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1196,7 +1196,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) if (DPU_FORMAT_IS_YUV(fmt)) _dpu_plane_setup_csc(pdpu); else - pdpu->csc_ptr = 0; + pdpu->csc_ptr = NULL; } _dpu_plane_set_qos_lut(plane, fb); @@ -1349,7 +1349,7 @@ static void dpu_plane_reset(struct drm_plane *plane) /* remove previous state, if present */ if (plane->state) { dpu_plane_destroy_state(plane, plane->state); - plane->state = 0; + plane->state = NULL; } pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); -- 2.31.0

1 0

[git pull] drm fixes round two for 5.13-rc1
by Dave Airlie 10 May '21

10 May '21

Hey Linus, Bit later than usual, I queued them all up on Friday then promptly forgot to write the pull request email. This is mainly amdgpu fixes, with some radeon/msm/fbdev and one i915 gvt fix thrown in. Hopefully I get you before you drop rc1, but nothing insanely urgent if not. Dave. drm-next-2021-05-10: drm fixes for 5.13-rc1 amdgpu: - MPO hang workaround - Fix for concurrent VM flushes on vega/navi - dcefclk is not adjustable on navi1x and newer - MST HPD debugfs fix - Suspend/resumes fixes - Register VGA clients late in case driver fails to load - Fix GEM leak in user framebuffer create - Add support for polaris12 with 32 bit memory interface - Fix duplicate cursor issue when using overlay - Fix corruption with tiled surfaces on VCN3 - Add BO size and stride check to fix BO size verification radeon: - Fix off-by-one in power state parsing - Fix possible memory leak in power state parsing msm: - NULL ptr dereference fix fbdev: - procfs disabled warning fix i915: - gvt: Fix a possible division by zero in vgpu display rate calculation The following changes since commit 1cd6b4a04f038eb24fd18c8010e763d1140a9c7a: Merge tag 'drm-intel-next-fixes-2021-04-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-04-30 10:42:03 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-next-2021-05-10 for you to fetch changes up to 0844708ac3d2dbdace70f4a6020669d56958697f: Merge tag 'amd-drm-fixes-5.13-2021-05-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-05-07 12:44:51 +1000) ---------------------------------------------------------------- drm fixes for 5.13-rc1 amdgpu: - MPO hang workaround - Fix for concurrent VM flushes on vega/navi - dcefclk is not adjustable on navi1x and newer - MST HPD debugfs fix - Suspend/resumes fixes - Register VGA clients late in case driver fails to load - Fix GEM leak in user framebuffer create - Add support for polaris12 with 32 bit memory interface - Fix duplicate cursor issue when using overlay - Fix corruption with tiled surfaces on VCN3 - Add BO size and stride check to fix BO size verification radeon: - Fix off-by-one in power state parsing - Fix possible memory leak in power state parsing msm: - NULL ptr dereference fix fbdev: - procfs disabled warning fix i915: - gvt: Fix a possible division by zero in vgpu display rate calculation ---------------------------------------------------------------- Bas Nieuwenhuizen (2): drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode. drm/amdgpu: Use device specific BO size & stride check. Christian König (1): drm/amdgpu: fix concurrent VM flushes on Vega/Navi v2 Colin Xu (1): drm/i915/gvt: Prevent divided by zero when calculating refresh rate Darren Powell (2): amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and newer gpus Dave Airlie (3): Merge tag 'drm-intel-next-fixes-2021-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Merge tag 'drm-misc-next-fixes-2021-05-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Merge tag 'amd-drm-fixes-5.13-2021-05-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-next Evan Quan (1): drm/amdgpu: add new MC firmware for Polaris12 32bit ASIC Guenter Roeck (1): fbmem: Mark proc_fb_seq_ops as __maybe_unused Harry Wentland (1): drm/amd/display: Reject non-zero src_y and src_x for video planes Jani Nikula (1): Merge tag 'gvt-next-fixes-2021-04-29' of https://github.com/intel/gvt-linux into drm-intel-next-fixes Kai-Heng Feng (1): drm/amdgpu: Register VGA clients after init can no longer fail Kees Cook (2): drm/radeon: Fix off-by-one power_state index heap overwrite drm/radeon: Avoid power table parsing memory leaks Mikita Lipski (1): drm/amd/display: fix wrong statement in mst hpd debugfs Pavan Kumar Ramayanam (1): drm/amdgpu: Handling of amdgpu_device_resume return value for graceful teardown Rob Clark (1): drm/msm/dpu: Delete bonkers code Rodrigo Siqueira (1): drm/amd/display: Fix two cursor duplication when using overlay Simon Ser (1): amdgpu: fix GEM obj leak in amdgpu_display_user_framebuffer_create Tom Rix (1): drm/amd/pm: initialize variable Victor Zhao (1): drm/amdgpu: fix r initial values drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 28 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 184 ++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 19 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 ++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 +- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 5 +- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +- drivers/gpu/drm/i915/gvt/handlers.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 10 -- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 -- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 - drivers/gpu/drm/radeon/radeon_atombios.c | 26 ++- drivers/video/fbdev/core/fbmem.c | 2 +- 19 files changed, 332 insertions(+), 81 deletions(-)

4 4

[PATCH] RFC: drm/panel: s6e63m0: Register ESD IRQ handler
by Linus Walleij 09 May '21

09 May '21

The S6E63M0 can emit an "ESD IRQ" which spells out electrostatic discharge interrupt request. This exist on other panels as well. The interrupt will according to some sources occur as a result of the display being bent or cracked and generally failing to display the desired content. I have no idea about how we should handle this IRQ, but the codebase for the Samsung GT-S7710 handles it by restarting the display controller pipeline, and possibly we should also bring the panel, bridge, and display controller down/up in response. One idea I have is to broadcast a notifier so that the core can react to this in process context in response to this interrupt and restart the display pipeline. I.e. raw_notifier_call_chain(). Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- drivers/gpu/drm/panel/panel-samsung-s6e63m0.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c index 603c5dfe8768..5e4d2e8aa7a7 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c @@ -17,6 +17,8 @@ #include <linux/module.h> #include <linux/regulator/consumer.h> #include <linux/media-bus-format.h> +#include <linux/of_irq.h> +#include <linux/interrupt.h> #include <video/mipi_display.h> @@ -713,6 +715,18 @@ static int s6e63m0_backlight_register(struct s6e63m0 *ctx, u32 max_brightness) return ret; } +static irqreturn_t s6e63m0_esd_irq(int irq, void *data) +{ + struct s6e63m0 *ctx = data; + + dev_info(ctx->dev, "ESD IRQ occurred\n"); + + /* Signal to the display controller to restart? */ + msleep(100); + + return IRQ_HANDLED; +} + int s6e63m0_probe(struct device *dev, int (*dcs_read)(struct device *dev, const u8 cmd, u8 *val), int (*dcs_write)(struct device *dev, const u8 *data, size_t len), @@ -720,6 +734,7 @@ int s6e63m0_probe(struct device *dev, { struct s6e63m0 *ctx; u32 max_brightness; + int irq; int ret; ctx = devm_kzalloc(dev, sizeof(struct s6e63m0), GFP_KERNEL); @@ -758,6 +773,13 @@ int s6e63m0_probe(struct device *dev, return PTR_ERR(ctx->reset_gpio); } + irq = of_irq_get(dev->of_node, 0); + if (irq) { + ret = devm_request_threaded_irq(dev, irq, NULL, + s6e63m0_esd_irq, IRQF_ONESHOT, + "s6e63m0-esd", ctx); + } + drm_panel_init(&ctx->panel, dev, &s6e63m0_drm_funcs, dsi_mode ? DRM_MODE_CONNECTOR_DSI : DRM_MODE_CONNECTOR_DPI); -- 2.30.2

1 0

[PATCH] drm: panel-orientation-quirks: Update the Lenovo Ideapad D330 quirk (v2)
by Hans de Goede 09 May '21

09 May '21

2 improvements to the Lenovo Ideapad D330 panel-orientation quirks: 1. Some versions of the Lenovo Ideapad D330 have a DMI_PRODUCT_NAME of "81H3" and others have "81MD". Testing has shown that the "81MD" also has a 90 degree mounted panel. Drop the DMI_PRODUCT_NAME from the existing quirk so that the existing quirk matches both variants. 2. Some of the Lenovo Ideapad D330 models have a HD (800x1280) screen instead of a FHD (1200x1920) screen (both are mounted right-side-up) add a second Lenovo Ideapad D330 quirk for the HD version. Changes in v2: - Add a new quirk for Lenovo Ideapad D330 models with a HD screen instead of a FHD screen Link: https://github.com/systemd/systemd/pull/18884 Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/gpu/drm/drm_panel_orientation_quirks.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 58f5dc2f6dd5..c3a1dbb29ae1 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -204,10 +204,15 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), }, .driver_data = (void *)&lcd800x1280_rightside_up, - }, { /* Lenovo Ideapad D330 */ + }, { /* Lenovo Ideapad D330-10IGM (HD) */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad D330-10IGM"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* Lenovo Ideapad D330-10IGM (FHD) */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "81H3"), DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad D330-10IGM"), }, .driver_data = (void *)&lcd1200x1920_rightside_up, -- 2.31.1

1 0

[PATCH v2] drm/amdgpu: Ensure that the modifier requested is supported by plane.
by Mark Yacoub 09 May '21

09 May '21

From: Mark Yacoub <markyacoub(a)google.com> On initializing the framebuffer, call drm_any_plane_has_format to do a check if the modifier is supported. drm_any_plane_has_format calls dm_plane_format_mod_supported which is extended to validate that the modifier is on the list of the plane's supported modifiers. The bug was caught using igt-gpu-tools test: kms_addfb_basic.addfb25-bad-modifier Tested on ChromeOS Zork by turning on the display, running an overlay test, and running a YT video. === Changes from v1 === Explicitly handle DRM_FORMAT_MOD_INVALID modifier. Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: Bas Nieuwenhuizen <bas(a)basnieuwenhuizen.nl> Signed-off-by: default avatarMark Yacoub <markyacoub(a)chromium.org> --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13 +++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index afa5f8ad0f563..a947b5aa420d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -908,6 +908,19 @@ int amdgpu_display_gem_fb_verify_and_init( &amdgpu_fb_funcs); if (ret) goto err; + /* Verify that the modifier is supported. */ + if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0])) { + struct drm_format_name_buf format_name; + drm_dbg_kms(dev, + "unsupported pixel format %s / modifier 0x%llx\n", + drm_get_format_name(mode_cmd->pixel_format, + &format_name), + mode_cmd->modifier[0]); + + ret = -EINVAL; + goto err; + } ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 961abf1cf040c..6fc746996c24f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3939,6 +3939,7 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, { struct amdgpu_device *adev = drm_to_adev(plane->dev); const struct drm_format_info *info = drm_format_info(format); + int i; enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; @@ -3946,11 +3947,22 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, return false; /* - * We always have to allow this modifier, because core DRM still - * checks LINEAR support if userspace does not provide modifers. + * We always have to allow these modifiers: + * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. + * 2. Not passing any modifiers is the same as explicitly passing INVALID. */ - if (modifier == DRM_FORMAT_MOD_LINEAR) + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == DRM_FORMAT_MOD_INVALID) { return true; + } + + /* Check that the modifier is on the list of the plane's supported modifiers. */ + for (i = 0; i < plane->modifier_count; i++) { + if (modifier == plane->modifiers[i]) + break; + } + if (i == plane->modifier_count) + return false; /* * The arbitrary tiling support for multiplane formats has not been hooked -- 2.31.0.291.g576ba9dcdaf-goog

3 2

[PATCH] video: fbdev: lcd_mipid: Fix a memory leak in an error handling path
by Christophe JAILLET 08 May '21

08 May '21

If 'mipid_detect()' fails, we must free 'md' to avoid a memory leak. While at it, modernize the function: - remove a useless message in case of memory allocation failure - change a '== NULL' into a '!' Fixes: 66d2f99d0bb5 ("omapfb: add support for MIPI-DCS compatible LCDs") Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- drivers/video/fbdev/omap/lcd_mipid.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/omap/lcd_mipid.c b/drivers/video/fbdev/omap/lcd_mipid.c index a75ae0c9b14c..b4b93ff4b41a 100644 --- a/drivers/video/fbdev/omap/lcd_mipid.c +++ b/drivers/video/fbdev/omap/lcd_mipid.c @@ -551,10 +551,8 @@ static int mipid_spi_probe(struct spi_device *spi) int r; md = kzalloc(sizeof(*md), GFP_KERNEL); - if (md == NULL) { - dev_err(&spi->dev, "out of memory\n"); + if (!md) return -ENOMEM; - } spi->mode = SPI_MODE_0; md->spi = spi; @@ -563,11 +561,15 @@ static int mipid_spi_probe(struct spi_device *spi) r = mipid_detect(md); if (r < 0) - return r; + goto free_md; omapfb_register_panel(&md->panel); return 0; + +free_md: + kfree(md); + return r; } static int mipid_spi_remove(struct spi_device *spi) -- 2.30.2

1 0

nouveau timeout errors with kernel 5.12
by Larry Finger 08 May '21

08 May '21

Hi, Beginning with kernel 5.12 I started getting system hangs/freezes, particularly when starting the Chrome browser. At least some of these are logged as a timeout. My hardware is a NVIDIA Corporation GF116 [GeForce GTX 550 Ti] [10de:1244] (rev a1). I tried to bisect the error, but the error does not show immediately, and I have little confidence in the bisection. For reference, my last bad commit was 05fcc256 and my last good commit was 6fc90e18. A typical error splat is: : ------------[ cut here ]------------ : nouveau 0000:01:00.0: timeout : WARNING: CPU: 3 PID: 1970 at drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c:90 gf100_fifo_gpfifo_engine_fini+0x168/0x1b0 [nouveau] : Modules linked in: af_packet vboxnetadp(O) vboxnetflt(O) vboxdrv(O) dmi_sysfs xfs raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq raid1 libcrc32c md_mod edac_mce_amd kvm_amd ccp hid_generic snd_hda_codec_realtek snd_hda_codec_generic kvm usbhid eeepc_wmi ledtrig_audio snd_hda_codec_hdmi snd_hda_intel irqbypass snd_intel_dspcfg snd_intel_sdw_acpi snd_hda_codec snd_hda_core asus_wmi snd_hwdep snd_pcm battery snd_timer sparse_keymap rfkill wmi_bmof pcspkr efi_pstore snd fam15h_power k10temp igb soundcore dca sp5100_tco i2c_piix4 acpi_cpufreq tiny_power_button nls_iso8859_1 nls_cp437 vfat fat nfsd auth_rpcgss nfs_acl lockd grace sunrpc nfs_ssc fuse configfs uas usb_storage nouveau ohci_pci video drm_ttm_helper ttm i2c_algo_bit drm_kms_helper crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel aesni_intel syscopyarea sysfillrect sysimgblt crypto_simd fb_sys_fops cryptd cec rc_core xhci_pci xhci_pci_renesas xhci_hcd drm ehci_pci ohci_hcd : ehci_hcd usbcore mxm_wmi sr_mod cdrom wmi button sg dm_multipath dm_mod scsi_dh_rdac scsi_dh_emc scsi_dh_alua msr efivarfs : CPU: 3 PID: 1970 Comm: gdbus Tainted: G W O 5.12.0-2-default #1 openSUSE Tumbleweed : Hardware name: To be filled by O.E.M. To be filled by O.E.M./970 PRO GAMING/AURA, BIOS 0901 11/07/2016 : RIP: 0010:gf100_fifo_gpfifo_engine_fini+0x168/0x1b0 [nouveau] : Code: 8b 40 10 48 8b 78 10 48 8b 6f 50 48 85 ed 75 03 48 8b 2f e8 ca f3 d6 e4 48 89 ea 48 c7 c7 1c b9 8a c0 48 89 c6 e8 f9 9b 05 e5 <0f> 0b 41 8b 46 38 85 c0 0f 85 53 8c 07 00 48 8b bb d0 01 00 00 41 : RSP: 0018:ffff9fe282517a20 EFLAGS: 00010282 : RAX: 0000000000000000 RBX: ffff89c268a85400 RCX: ffff89c50ecda708 : RDX: 00000000ffffffd8 RSI: 0000000000000027 RDI: ffff89c50ecda700 : RBP: ffff89c20116f1d0 R08: ffff89c51ef567a8 R09: 0000000000013ffb : R10: 00000000ffffc000 R11: 3fffffffffffffff R12: 0000000000000000 : R13: ffff89c250c43de0 R14: ffff89c208350000 R15: 0000000000000000 : FS: 00007f376efb6640(0000) GS:ffff89c50ecc0000(0000) knlGS:0000000000000000 : CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 : CR2: 00005567fe52cfa8 CR3: 00000001507c8000 CR4: 00000000000406e0 : Call Trace: : nvkm_fifo_chan_child_fini+0x79/0xf0 [nouveau] : nvkm_oproxy_fini+0x2c/0x90 [nouveau] : nvkm_object_fini+0xbc/0x150 [nouveau] : nvkm_object_fini+0x73/0x150 [nouveau] : nvkm_ioctl_del+0x2f/0x50 [nouveau] : nvkm_ioctl+0xe1/0x180 [nouveau] : nvif_object_dtor+0x5a/0x80 [nouveau] : nouveau_channel_del+0xad/0x160 [nouveau] : nouveau_abi16_chan_fini.constprop.0+0x10b/0x190 [nouveau] : nouveau_abi16_fini+0x2e/0x60 [nouveau] : nouveau_drm_postclose+0x4c/0xd0 [nouveau] : drm_file_free.part.0+0x1c9/0x230 [drm] : drm_release+0x65/0x110 [drm] : __fput+0x94/0x240 : task_work_run+0x65/0xa0 : do_exit+0x362/0xa20 : do_group_exit+0x33/0xa0 : get_signal+0x161/0x8b0 : arch_do_signal_or_restart+0xef/0x830 : ? __x64_sys_futex+0x13d/0x1c0 : exit_to_user_mode_prepare+0xed/0x180 : syscall_exit_to_user_mode+0x18/0x40 : entry_SYSCALL_64_after_hwframe+0x44/0xae : RIP: 0033:0x7f377ed6d5cf : Code: Unable to access opcode bytes at RIP 0x7f377ed6d5a5. : RSP: 002b:00007f376efb5a40 EFLAGS: 00000293 ORIG_RAX: 0000000000000007 : RAX: fffffffffffffdfc RBX: 00007f377eeae1e0 RCX: 00007f377ed6d5cf : RDX: 00000000ffffffff RSI: 0000000000000003 RDI: 000055b2cd634480 : RBP: 000055b2cd634480 R08: 0000000000000000 R09: 0000000000000004 : R10: 0000000000000030 R11: 0000000000000293 R12: 0000000000000003 : R13: 00007f376efb5a84 R14: 00000000ffffffff R15: 000055b2cd634370 : ---[ end trace c85bfdc7ef3321c2 ]--- : nouveau 0000:01:00.0: fifo: channel 7 [ibus-extension-[1940]] kick timeout : nouveau: ibus-extension-[1940]:00000000:0000906f: detach sw failed, -110 : nouveau 0000:01:00.0: fifo: SCHED_ERROR 0d [] : nouveau 0000:01:00.0: fifo: runlist update timeout : nouveau 0000:01:00.0: ibus-x11[1942]: failed to idle channel 9 [ibus-x11[1942]] : nouveau 0000:01:00.0: ibus-x11[1942]: failed to idle channel 9 [ibus-x11[1942]] : ------------[ cut here ]------------ I will be happy to provide any additional material that may be needed. Thanks, Larry

1 0

Re: [Intel-gfx] [PATCH 4/4] i915: fix remap_io_sg to verify the pgprot
by youling257 08 May '21

08 May '21

This patch cause "x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x064a2000-0x064a2fff], got write-back" problem. my 2GB ram Bay trail z3735f tablet runing on android-x86, "i915: fix remap_io_sg to verify the pgprot" cause this problem. 05-09 02:59:25.099 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x0640a000-0x0640dfff], got write-back 05-09 02:59:25.106 1440 1440 W hwc-gl-worker: EGL_ANDROID_native_fence_sync extension not supported 05-09 02:59:25.111 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x064a2000-0x064a2fff], got write-back 05-09 02:59:25.118 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x06400000-0x06404fff], got write-back 05-09 02:59:25.125 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x06405000-0x06408fff], got write-back 05-09 02:59:25.148 1440 1440 W hwc-gl-worker: EGL_ANDROID_native_fence_sync extension not supported 05-09 02:59:25.158 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x06542000-0x06542fff], got write-back 05-09 02:59:25.165 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x06499000-0x0649dfff], got write-back 05-09 02:59:25.171 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x0649e000-0x064a1fff], got write-back 05-09 02:59:25.177 1440 1440 W hwc-gl-worker: EGL_ANDROID_native_fence_sync extension not supported 05-09 02:59:25.183 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x065fa000-0x065fafff], got write-back 05-09 02:59:25.192 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x06539000-0x0653dfff], got write-back 05-09 02:59:25.199 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x0653e000-0x06541fff], got write-back 05-09 02:59:25.204 1440 1440 W hwc-gl-worker: EGL_ANDROID_native_fence_sync extension not supported 05-09 02:59:25.212 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x066a2000-0x066a2fff], got write-back 05-09 02:59:25.218 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x065f1000-0x065f5fff], got write-back 05-09 02:59:25.226 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x065f6000-0x065f9fff], got write-back 05-09 02:59:27.101 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x08a76000-0x08a76fff], got write-back 05-09 02:59:27.225 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x08a77000-0x08a7afff], got write-back 05-09 02:59:27.242 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x08bd0000-0x08bd0fff], got write-back 05-09 02:59:27.254 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x08bd1000-0x08bf0fff], got write-back 05-09 02:59:27.310 1440 1440 E drm-fb : Failed to get handle from prime fd: 25 05-09 02:59:27.322 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x080d5000-0x080d9fff], got write-back 05-09 02:59:27.322 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x080da000-0x080ddfff], got write-back 05-09 02:59:27.338 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x1b830000-0x1b83ffff], got write-back 05-09 02:59:27.338 0 0 W x86/PAT : BootAnimation:1665 map pfn RAM range req write-combining for [mem 0x1b76a000-0x1b76efff], got write-back 05-09 02:59:27.344 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x07e87000-0x07e8bfff], got write-back 05-09 02:59:27.349 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x07e8c000-0x07e90fff], got write-back 05-09 02:59:27.347 1440 1440 E drm-fb : Failed to get handle from prime fd: 25 05-09 02:59:27.361 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c123000-0x1c126fff], got write-back 05-09 02:59:27.361 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c127000-0x1c12afff], got write-back 05-09 02:59:27.362 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c12f000-0x1c13efff], got write-back 05-09 02:59:27.362 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c12b000-0x1c12efff], got write-back 05-09 02:59:27.364 1440 1440 E drm-fb : Failed to get handle from prime fd: 25 05-09 02:59:27.377 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c140000-0x1c144fff], got write-back 05-09 02:59:27.377 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c145000-0x1c148fff], got write-back 05-09 02:59:27.378 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c14b000-0x1c14ffff], got write-back 05-09 02:59:27.379 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c151000-0x1c155fff], got write-back 05-09 02:59:27.377 1440 1440 E drm-fb : Failed to get handle from prime fd: 25 05-09 02:59:27.393 0 0 W x86/PAT : surfaceflinger:1440 map pfn RAM range req write-combining for [mem 0x1c157000-0x1c15bfff], got write-back

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[PATCH] drm: panel-orientation-quirks: Make the Lenovo Ideapad D330 quirk also match the 81MD version
by Hans de Goede 08 May '21

08 May '21

The Lenovo Ideapad D330 has 2 versions, one with a DMI_PRODUCT_NAME of "81H3" and one with "81MD". Testing has shown that the "81MD" also has a 90 degree mounted panel with a resolution of 1200x1920. Drop the DMI_PRODUCT_NAME from the existing quirk so that the existing quirk matches both versions. Link: https://github.com/systemd/systemd/pull/18884 Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/gpu/drm/drm_panel_orientation_quirks.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 58f5dc2f6dd5..3fadf4aade3a 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -207,7 +207,6 @@ static const struct dmi_system_id orientation_data[] = { }, { /* Lenovo Ideapad D330 */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "81H3"), DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad D330-10IGM"), }, .driver_data = (void *)&lcd1200x1920_rightside_up, -- 2.31.1

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dri-devel May 2021