dri-devel May 2021

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[Bug 212935] New: When my monitors go to standby amdgpu crashes
by bugzilla-daemon＠bugzilla.kernel.org 04 May '21

04 May '21

https://bugzilla.kernel.org/show_bug.cgi?id=212935 Bug ID: 212935 Summary: When my monitors go to standby amdgpu crashes Product: Drivers Version: 2.5 Kernel Version: 5.11 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: mwolf(a)adiumentum.com Regression: No Created attachment 296605 --> https://bugzilla.kernel.org/attachment.cgi?id=296605&action=edit dmesg of the crash general protection fault, probably for non-canonical address 0x8e60543000000000: 0000 [#1] SMP PTI CPU: 4 PID: 34572 Comm: kworker/4:0 Not tainted 5.11.16-300.fc34.x86_64 #1 Hardware name: ASUS All Series/Z97-A-USB31, BIOS 3503 04/18/2018 Workqueue: events drm_sched_job_timedout [gpu_sched] amdgpu 0000:01:00.0: amdgpu: GPU reset begin! amdgpu 0000:01:00.0: amdgpu: Bailing on TDR for s_job:201fc, as another already in progress RIP: 0010:free_mqd_hiq_sdma+0x5/0x20 [amdgpu] Code: 00 48 01 d1 48 89 48 18 49 8b 88 08 02 00 00 48 01 d1 48 89 48 08 49 03 90 10 02 00 00 48 89 50 10 5b 5d c3 90 0f 1f 44 00 00 <48> 83 7a 18 00 48 89 d7 74 05 e9 bc 7b cb d5 0f 0b e9 b5 7b cb d5 RSP: 0018:ffffb1b7446c3d30 EFLAGS: 00010206 RAX: ffffffffc063a220 RBX: ffff89b10a957400 RCX: 0000000080800033 RDX: 8e60543000000000 RSI: 0000000055d51400 RDI: ffff89b10da85700 RBP: ffff89b2f0284000 R08: 0000000000000001 R09: 0000000000000000 R10: ffff89b243481a40 R11: 0000000000000001 R12: ffff89b10a9574d0 R13: ffff89b10b580000 R14: ffff89b1014e7000 R15: ffff89b1014e70c8 FS: 0000000000000000(0000) GS:ffff89b42ed00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000037dbfa13c000 CR3: 00000001bba10006 CR4: 00000000001706e0 Call Trace: kernel_queue_uninit+0x33/0xe0 [amdgpu] stop_cpsch+0xa0/0xc0 [amdgpu] kgd2kfd_suspend.part.0+0x2f/0x40 [amdgpu] kgd2kfd_pre_reset+0x3f/0x50 [amdgpu] amdgpu_device_gpu_recover.cold+0x33d/0x924 [amdgpu] ? uvd_v3_1_resume+0x11/0x20 [amdgpu] amdgpu_job_timedout+0x123/0x150 [amdgpu] drm_sched_job_timedout+0x72/0xf0 [gpu_sched] process_one_work+0x1ec/0x380 worker_thread+0x53/0x3e0 ? process_one_work+0x380/0x380 kthread+0x11b/0x140 ? kthread_associate_blkcg+0xa0/0xa0 ret_from_fork+0x22/0x30 Modules linked in: uinput snd_seq_dummy snd_hrtimer tun xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_nat_sip nf_nat_tftp nf_conntrack_sip nf_conntrack_tftp nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat bridge stp llc nf_tables ebtable_nat ebtable_broute ip6table_nat ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 iptable_mangle iptable_raw iptable_security ip_set nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter sunrpc vfat fat snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_hda_codec_hdmi intel_rapl_msr intel_rapl_common snd_hda_intel snd_intel_dspcfg soundwire_intel soundwire_generic_allocation snd_soc_core x86_pkg_temp_thermal intel_powerclamp coretemp snd_compress kvm_intel snd_pcm_dmaengine soundwire_cadence snd_hda_codec snd_usb_audio kvm snd_hda_core mei_hdcp iTCO_wdt eeepc_wmi snd_usbmidi_lib intel_pmc_bxt ac97_bus at24 iTCO_vendor_support snd_rawmidi snd_hwdep asus_wmi irqbypass snd_seq sparse_keymap rapl intel_cstate snd_seq_device rfkill intel_uncore mxm_wmi wmi_bmof pcspkr i2c_i801 i2c_smbus snd_pcm snd_timer lpc_ich joydev mc snd mei_me mei soundcore acpi_pad binfmt_misc zram ip_tables amdgpu uas usb_storage drm_ttm_helper ttm crct10dif_pclmul iommu_v2 crc32_pclmul -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH 1/2] drm/msm/dp: service only one irq_hpd if there are multiple irq_hpd pending
by Kuogee Hsieh 04 May '21

04 May '21

Some dongle may generate more than one irq_hpd events in a short period of time. This patch will treat those irq_hpd events as single one and service only one irq_hpd event. Signed-off-by: Kuogee Hsieh <khsieh(a)codeaurora.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 5a39da6..0a7d383 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -707,6 +707,9 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) return 0; } + /* only handle first irq_hpd in case of multiple irs_hpd pending */ + dp_del_event(dp, EV_IRQ_HPD_INT); + ret = dp_display_usbpd_attention_cb(&dp->pdev->dev); if (ret == -ECONNRESET) { /* cable unplugged */ dp->core_initialized = false; @@ -1300,6 +1303,9 @@ static int dp_pm_suspend(struct device *dev) /* host_init will be called at pm_resume */ dp->core_initialized = false; + /* system suspended, delete pending irq_hdps */ + dp_del_event(dp, EV_IRQ_HPD_INT); + mutex_unlock(&dp->event_mutex); return 0; @@ -1496,6 +1502,9 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder) /* stop sentinel checking */ dp_del_event(dp_display, EV_DISCONNECT_PENDING_TIMEOUT); + /* link is down, delete pending irq_hdps */ + dp_del_event(dp_display, EV_IRQ_HPD_INT); + dp_display_disable(dp_display, 0); rc = dp_display_unprepare(dp); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 10

[PATCH] MAINTAINERS: Fix file name for simple framebuffers' drm driver
by Liu Ying 04 May '21

04 May '21

The file name for simple framebuffers' drm driver should be 'simpledrm.c' rather than 'simplekms.c'. This patch fixes it. Signed-off-by: Liu Ying <victor.liu(a)nxp.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4d10ad6586042..7a9879c14742b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5770,7 +5770,7 @@ M: Thomas Zimmermann <tzimmermann(a)suse.de> L: dri-devel(a)lists.freedesktop.org S: Maintained T: git git://anongit.freedesktop.org/drm/drm-misc -F: drivers/gpu/drm/tiny/simplekms.c +F: drivers/gpu/drm/tiny/simpledrm.c DRM DRIVER FOR SIS VIDEO CARDS S: Orphan / Obsolete -- 2.25.1

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[RESEND PATCH v6 1/4] mfd: rt4831: Adds support for Richtek RT4831
by cy_huang 04 May '21

04 May '21

From: ChiYuan Huang <cy_huang(a)richtek.com> This adds support Richtek RT4831 core. It includes four channel WLED driver and Display Bias Voltage outputs. Signed-off-by: ChiYuan Huang <cy_huang(a)richtek.com> --- Resend this v6 patch series to loop devicetree reviewers. The RT4831 regulator patches are already on main stream, and can be referred to 9351ab8b0cb6 regulator: rt4831: Adds support for Richtek RT4831 DSV regulator 934b05e81862 regulator: rt4831: Adds DT binding document for Richtek RT4831 DSV regulator since v6 - Respin the date from 2020 to 2021. - Rmove the shutdown routine. - Change the macro OF_MFD_CELL to MFD_CELL_OF. since v5 - Rename file name from rt4831-core.c to rt4831.c - Change RICHTEK_VID to RICHTEK_VENDOR_ID. - Change gpio_desc nameing from 'enable' to 'enable_gpio' in probe. - Change variable 'val' to the meaningful name 'chip_id'. - Refine the error log when vendor id is not matched. - Remove of_match_ptr. since v2 - Refine Kconfig descriptions. - Add copyright. - Refine error logs in probe. - Refine comment lines in remove and shutdown. --- drivers/mfd/Kconfig | 10 +++++ drivers/mfd/Makefile | 1 + drivers/mfd/rt4831.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/mfd/rt4831.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b74efa4..3f43834 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1065,6 +1065,16 @@ config MFD_RDC321X southbridge which provides access to GPIOs and Watchdog using the southbridge PCI device configuration space. +config MFD_RT4831 + tristate "Richtek RT4831 four channel WLED and Display Bias Voltage" + depends on I2C + select MFD_CORE + select REGMAP_I2C + help + This enables support for the Richtek RT4831 that includes 4 channel + WLED driving and Display Bias Voltage. It's commonly used to provide + power to the LCD display and LCD backlight. + config MFD_RT5033 tristate "Richtek RT5033 Power Management IC" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 834f546..5986914 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -235,6 +235,7 @@ obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o obj-$(CONFIG_MFD_DLN2) += dln2.o +obj-$(CONFIG_MFD_RT4831) += rt4831.o obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o diff --git a/drivers/mfd/rt4831.c b/drivers/mfd/rt4831.c new file mode 100644 index 00000000..b169781 --- /dev/null +++ b/drivers/mfd/rt4831.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Richtek Technology Corp. + * + * Author: ChiYuan Huang <cy_huang(a)richtek.com> + */ + +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#define RT4831_REG_REVISION 0x01 +#define RT4831_REG_ENABLE 0x08 +#define RT4831_REG_I2CPROT 0x15 + +#define RICHTEK_VENDOR_ID 0x03 +#define RT4831_VID_MASK GENMASK(1, 0) +#define RT4831_RESET_MASK BIT(7) +#define RT4831_I2CSAFETMR_MASK BIT(0) + +static const struct mfd_cell rt4831_subdevs[] = { + MFD_CELL_OF("rt4831-backlight", NULL, NULL, 0, 0, "richtek,rt4831-backlight"), + MFD_CELL_NAME("rt4831-regulator") +}; + +static bool rt4831_is_accessible_reg(struct device *dev, unsigned int reg) +{ + if (reg >= RT4831_REG_REVISION && reg <= RT4831_REG_I2CPROT) + return true; + return false; +} + +static const struct regmap_config rt4831_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = RT4831_REG_I2CPROT, + + .readable_reg = rt4831_is_accessible_reg, + .writeable_reg = rt4831_is_accessible_reg, +}; + +static int rt4831_probe(struct i2c_client *client) +{ + struct gpio_desc *enable_gpio; + struct regmap *regmap; + unsigned int chip_id; + int ret; + + enable_gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(enable_gpio)) { + dev_err(&client->dev, "Failed to get 'enable' GPIO\n"); + return PTR_ERR(enable_gpio); + } + + regmap = devm_regmap_init_i2c(client, &rt4831_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&client->dev, "Failed to initialize regmap\n"); + return PTR_ERR(regmap); + } + + ret = regmap_read(regmap, RT4831_REG_REVISION, &chip_id); + if (ret) { + dev_err(&client->dev, "Failed to get H/W revision\n"); + return ret; + } + + if ((chip_id & RT4831_VID_MASK) != RICHTEK_VENDOR_ID) { + dev_err(&client->dev, "Chip vendor ID 0x%02x not matched\n", chip_id); + return -ENODEV; + } + + /* + * Used to prevent the abnormal shutdown. + * If SCL/SDA both keep low for one second to reset HW. + */ + ret = regmap_update_bits(regmap, RT4831_REG_I2CPROT, RT4831_I2CSAFETMR_MASK, + RT4831_I2CSAFETMR_MASK); + if (ret) { + dev_err(&client->dev, "Failed to enable I2C safety timer\n"); + return ret; + } + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, rt4831_subdevs, + ARRAY_SIZE(rt4831_subdevs), NULL, 0, NULL); +} + +static int rt4831_remove(struct i2c_client *client) +{ + struct regmap *regmap = dev_get_regmap(&client->dev, NULL); + + /* Disable WLED and DSV outputs */ + return regmap_update_bits(regmap, RT4831_REG_ENABLE, RT4831_RESET_MASK, RT4831_RESET_MASK); +} + +static const struct of_device_id __maybe_unused rt4831_of_match[] = { + { .compatible = "richtek,rt4831", }, + {} +}; +MODULE_DEVICE_TABLE(of, rt4831_of_match); + +static struct i2c_driver rt4831_driver = { + .driver = { + .name = "rt4831", + .of_match_table = rt4831_of_match, + }, + .probe_new = rt4831_probe, + .remove = rt4831_remove, +}; +module_i2c_driver(rt4831_driver); + +MODULE_AUTHOR("ChiYuan Huang <cy_huang(a)richtek.com>"); +MODULE_LICENSE("GPL v2"); -- 2.7.4

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[PATCH 0/1] Add support for querying engine cycles
by Umesh Nerlige Ramappa 04 May '21

04 May '21

This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch v4: Split cpu timestamp array into timestamp and delta for cleaner API v5: Add width of the cs cycles to the uapi Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> Test-with: 20210504001003.69445-1-umesh.nerlige.ramappa(a)intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 157 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 56 +++++++++++ 2 files changed, 213 insertions(+) -- 2.20.1

1 1

[PATCH] dt-bindings: display: renesas, du: Add missing power-domains property
by Geert Uytterhoeven 03 May '21

03 May '21

"make dtbs_check" complains: arch/arm/boot/dts/r8a7779-marzen.dt.yaml: display@fff80000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77970-v3msk.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77970-eagle.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77980-condor.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dt.yaml: display@feb00000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' Fix this by documenting the power-domains property. Fixes: 99d66127fad25ebb ("dt-bindings: display: renesas,du: Convert binding to YAML") Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- Documentation/devicetree/bindings/display/renesas,du.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index e955034da53b86e2..0dad87cdd8735542 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -51,6 +51,9 @@ properties: resets: true reset-names: true + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/port description: | -- 2.25.1

4 3

[PATCH 1/1] drm/vmwgfx: use ttm_bo_move_null() when there is nothing to move
by Nirmoy Das 03 May '21

03 May '21

Use ttm_bo_move_null() instead of ttm_bo_assign_mem(). Signed-off-by: Nirmoy Das <nirmoy.das(a)amd.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index 2dc031fe4a90..beaf42f84f03 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -738,7 +738,7 @@ static int vmw_move(struct ttm_buffer_object *bo, if (old_man->use_tt && new_man->use_tt) { if (bo->mem.mem_type == TTM_PL_SYSTEM) { - ttm_bo_assign_mem(bo, new_mem); + ttm_bo_move_null(bo, new_mem); return 0; } ret = ttm_bo_wait_ctx(bo, ctx); -- 2.31.1

2 1

[PATCH 0/1] Add support for querying engine cycles
by Umesh Nerlige Ramappa 03 May '21

03 May '21

This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch v4: Split cpu timestamp array into timestamp and delta for cleaner API Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa(a)intel.com> Test-with: 20210429002959.69473-1-umesh.nerlige.ramappa(a)intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 148 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 52 +++++++++++ 2 files changed, 200 insertions(+) -- 2.20.1

4 11

[PATCH 1/1] drm/vmwgfx: free ttm resource before assigning a new one
by Nirmoy Das 03 May '21

03 May '21

TTM BO resource need to be freed before calling ttm_bo_assign_mem(). Signed-off-by: Nirmoy Das <nirmoy.das(a)amd.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index 2dc031fe4a90..93e4cf34a3a3 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -738,6 +738,7 @@ static int vmw_move(struct ttm_buffer_object *bo, if (old_man->use_tt && new_man->use_tt) { if (bo->mem.mem_type == TTM_PL_SYSTEM) { + ttm_resource_free(bo, &bo->mem); ttm_bo_assign_mem(bo, new_mem); return 0; } -- 2.31.1

3 2

[PATCH 0/4] drm/i915/display Try YCbCr420 color when RGB fails
by Werner Sembach 03 May '21

03 May '21

When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which previously failed silently. AMDGPU had nearly the exact same issue. This problem description is therefore copied from my commit message of the AMDGPU patch. On some setups, while the monitor and the gpu support display modes with pixel clocks of up to 600MHz, the link encoder might not. This prevents YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be possible. However, which color mode is used is decided before the link encoder capabilities are checked. This patch fixes the problem by retrying to find a display mode with YCbCr420 enforced and using it, if it is valid. This patchset is revision 2, now split up in multiple parts with some minor restructuring added für a cleaner implementation.

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dri-devel May 2021