dri-devel June 2021

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[PATCH 00/27] drm/i915/gem: ioctl clean-ups (v5)
by Jason Ekstrand 03 Jun '21

03 Jun '21

Overview: --------- This patch series attempts to clean up some of the IOCTL mess we've created over the last few years. The most egregious bit being context mutability. In summary, this series: 1. Drops two never-used context params: RINGSIZE and NO_ZEROMAP 2. Drops the entire CONTEXT_CLONE API 3. Implements SINGLE_TIMELINE with a syncobj instead of actually sharing intel_timeline between engines. 4. Adds a few sanity restrictions to the balancing/bonding API. 5. Implements a proto-ctx mechanism so that the engine set and VM can only be set early on in the lifetime of a context, before anything ever executes on it. This effectively makes the VM and engine set immutable. This series has been tested with IGT as well as the Iris, ANV, and the Intel media driver doing an 8K decode (this uses bonding/balancing). I've also done quite a bit of git archeology to ensure that nothing in here will break anything that's already shipped at some point in history. It's possible I've missed something, but I've dug quite a bit. Details and motivation: ----------------------- In very broad strokes, there's an effort going on right now within Intel to try and clean up and simplify i915 anywhere we can. We obviously don't want to break any shipping userspace but, as can be seen by this series, there's a lot i915 theoretically supports which userspace doesn't actually need. Some of this, like the two context params used here, were simply oversights where we went through the usual API review process and merged the i915 bits but the userspace bits never landed for some reason. Not all are so innocent, however. For instance, there's an entire context cloning API which allows one to create a context with certain parameters "cloned" from some other context. This entire API has never been used by any userspace except IGT and there were never patches to any other userspace to use it. It never should have landed. Also, when we added support for setting explicit engine sets and sharing VMs across contexts, people decided to do so via SET_CONTEXT_PARAM. While this allowed them to re-use existing API, it did so at the cost of making those states mutable which leads to a plethora of potential race conditions. There were even IGT tests merged to cover some of theses: - gem_vm_create@async-destroy and gem_vm_create@destroy-race which test swapping out the VM on a running context. - gem_ctx_persistence@replace* which test whether a client can escape a non-persistent context by submitting a hanging batch and then swapping out the engine set before the hang is detected. - api_intel_bb@bb-with-vm which tests the that intel_bb_assign_vm works properly. This API is never used by any other IGT test. There is also an entire deferred flush and set state framework in i915_gem_cotnext.c which exists for safely swapping out the VM while there is work in-flight on a context. So, clearly people knew that this API was inherently racy and difficult to implement but they landed it anyway. Why? The best explanation I've been given is because it makes the API more "unified" or "symmetric" for this stuff to go through SET_CONTEXT_PARAM. It's not because any userspace actually wants to be able to swap out the VM or the set of engines on a running context. That would be utterly insane. This patch series cleans up this particular mess by introducing the concept of a i915_gem_proto_context data structure which contains context creation information. When you initially call GEM_CONTEXT_CREATE, a proto-context in created instead of an actual context. Then, the first time something is done on the context besides SET_CONTEXT_PARAM, an actual context is created. This allows us to keep the old drivers which use SET_CONTEXT_PARAM to set up the engine set (see also media) while ensuring that, once you have an i915_gem_context, the VM and the engine set are immutable state. Eventually, there are more clean-ups I'd like to do on top of this which should make working with contexts inside i915 simpler and safer: 1. Move the GEM handle -> vma LUT from i915_gem_context into either i915_ppgtt or drm_i915_file_private depending on whether or not the hardware has a full PPGTT. 2. Move the delayed context destruction code into intel_context or a per-engine wrapper struct rather than i915_gem_context. 3. Get rid of the separation between context close and context destroy 4. Get rid of the RCU on i915_gem_context However, these should probably be done as a separate patch series as this one is already starting to get longish, especially if you consider the 89 IGT patches that go along with it. Test-with: 20210423214853.876911-1-jason(a)jlekstrand.net Jason Ekstrand (27): drm/i915: Drop I915_CONTEXT_PARAM_RINGSIZE drm/i915: Stop storing the ring size in the ring pointer drm/i915: Drop I915_CONTEXT_PARAM_NO_ZEROMAP drm/i915/gem: Set the watchdog timeout directly in intel_context_set_gem (v2) drm/i915/gem: Return void from context_apply_all drm/i915: Drop the CONTEXT_CLONE API drm/i915: Implement SINGLE_TIMELINE with a syncobj (v4) drm/i915: Drop getparam support for I915_CONTEXT_PARAM_ENGINES drm/i915/gem: Disallow bonding of virtual engines (v3) drm/i915/gem: Remove engine auto-magic with FENCE_SUBMIT drm/i915/request: Remove the hook from await_execution drm/i915/gem: Disallow creating contexts with too many engines drm/i915: Stop manually RCU banging in reset_stats_ioctl (v2) drm/i915/gem: Add a separate validate_priority helper drm/i915: Add gem/i915_gem_context.h to the docs drm/i915/gem: Add an intermediate proto_context struct drm/i915/gem: Rework error handling in default_engines drm/i915/gem: Optionally set SSEU in intel_context_set_gem drm/i915/gem: Use the proto-context to handle create parameters drm/i915/gem: Return an error ptr from context_lookup drm/i915/gt: Drop i915_address_space::file (v2) drm/i915/gem: Delay context creation drm/i915/gem: Don't allow changing the VM on running contexts drm/i915/gem: Don't allow changing the engine set on running contexts drm/i915/selftests: Take a VM in kernel_context() i915/gem/selftests: Assign the VM at context creation in igt_shared_ctx_exec drm/i915/gem: Roll all of context creation together Documentation/gpu/i915.rst | 2 + drivers/gpu/drm/i915/Makefile | 1 - drivers/gpu/drm/i915/gem/i915_gem_context.c | 3015 ++++++++--------- drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 198 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 31 +- .../drm/i915/gem/selftests/i915_gem_context.c | 127 +- .../gpu/drm/i915/gem/selftests/mock_context.c | 67 +- .../gpu/drm/i915/gem/selftests/mock_context.h | 4 +- drivers/gpu/drm/i915/gt/intel_context.c | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 5 - drivers/gpu/drm/i915/gt/intel_context_param.c | 63 - drivers/gpu/drm/i915/gt/intel_context_param.h | 6 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 - .../drm/i915/gt/intel_execlists_submission.c | 114 - .../drm/i915/gt/intel_execlists_submission.h | 7 - drivers/gpu/drm/i915/gt/intel_gtt.h | 11 - drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 251 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 30 +- drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_request.c | 42 +- drivers/gpu/drm/i915/i915_request.h | 4 +- .../drm/i915/selftests/i915_mock_selftests.h | 1 - drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 - include/uapi/drm/i915_drm.h | 40 +- 31 files changed, 1655 insertions(+), 2398 deletions(-) delete mode 100644 drivers/gpu/drm/i915/gt/intel_context_param.c -- 2.31.1

5 63

[v5 0/5] drm: Support basic DPCD backlight in panel-simple and add a new panel ATNA33XC20
by Rajeev Nandan 03 Jun '21

03 Jun '21

This series adds the support for the eDP panel that needs the backlight controlling over the DP AUX channel using DPCD registers of the panel as per the VESA's standard. This series also adds support for the Samsung eDP AMOLED panel that needs DP AUX to control the backlight, and introduces new delays in the @panel_desc.delay to support this panel. This patch series depends on the following two series: - Doug's series [1], exposed the DP AUX channel to the panel-simple. - Lyude's series [2], introduced new drm helper functions for DPCD backlight. This series is the logical successor to the series [3]. Changes in v1: - Created dpcd backlight helper with very basic functionality, added backlight registration in the ti-sn65dsi86 bridge driver. Changes in v2: - Created a new DisplayPort aux backlight driver and moved the code from drm_dp_aux_backlight.c (v1) to the new driver. Changes in v3: - Fixed module compilation (kernel test bot). Changes in v4: - Added basic DPCD backlight support in panel-simple. - Added support for a new Samsung panel ATNA33XC20 that needs DPCD backlight controlling and has a requirement of delays between enable GPIO and regulator. Changes in v5: Addressed review suggestions from Douglas: - Created a new API drm_panel_dp_aux_backlight() in drm_panel.c - Moved DP AUX backlight functions from panel-simple.c to drm_panel.c - panel-simple probe() calls drm_panel_dp_aux_backlight() to create backlight when the backlight phandle is not specified in panel DT and DP AUX channel is present. - Added check for drm_edp_backlight_supported() before registering. - Removed the @uses_dpcd_backlight flag from panel_desc as this should be auto-detected. - Updated comments/descriptions. [1] https://lore.kernel.org/dri-devel/20210525000159.3384921-1-dianders@chromiu… [2] https://lore.kernel.org/dri-devel/20210514181504.565252-1-lyude@redhat.com/ [3] https://lore.kernel.org/dri-devel/1619416756-3533-1-git-send-email-rajeevny… Rajeev Nandan (5): drm/panel: add basic DP AUX backlight support drm/panel-simple: Support DP AUX backlight drm/panel-simple: Support for delays between GPIO & regulator dt-bindings: display: simple: Add Samsung ATNA33XC20 drm/panel-simple: Add Samsung ATNA33XC20 .../bindings/display/panel/panel-simple.yaml | 2 + drivers/gpu/drm/drm_panel.c | 108 +++++++++++++++++++++ drivers/gpu/drm/panel/panel-simple.c | 67 +++++++++++++ include/drm/drm_panel.h | 15 ++- 4 files changed, 188 insertions(+), 4 deletions(-) -- 2.7.4

5 13

[pull] amdgpu drm-fixes-5.13
by Alex Deucher 03 Jun '21

03 Jun '21

Hi Dave, Daniel, Fixes for 5.13. The following changes since commit 8124c8a6b35386f73523d27eacb71b5364a68c4c: Linux 5.13-rc4 (2021-05-30 11:58:25 -1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.13-2021-06-02 for you to fetch changes up to e7591a8d56bab89c617dae055446b6337ec32dc9: amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic (2021-06-02 17:58:11 -0400) ---------------------------------------------------------------- amd-drm-fixes-5.13-2021-06-02: amdgpu: - Display fixes - FRU EEPROM error handling fix - RAS fix - PSP fix - Releasing pinned BO fix ---------------------------------------------------------------- Asher Song (1): drm/amdgpu: add judgement for dc support Bindu Ramamurthy (1): drm/amd/display: Allow bandwidth validation for 0 streams. Jiansong Chen (1): drm/amdgpu: refine amdgpu_fru_get_product_info Luben Tuikov (1): drm/amdgpu: Don't query CE and UE errors Nicholas Kazlauskas (1): drm/amd/display: Fix GPU scaling regression by FS video support Nirmoy Das (1): drm/amdgpu: make sure we unpin the UVD BO Rodrigo Siqueira (1): drm/amd/display: Fix overlay validation by considering cursors Roman Li (1): drm/amd/display: Fix potential memory leak in DMUB hw_init Simon Ser (1): amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic Victor Zhao (1): drm/amd/amdgpu:save psp ring wptr to avoid attack drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 16 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 42 ++++++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++++------ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 9 files changed, 52 insertions(+), 50 deletions(-)

1 0

[PATCH] drm: amdgpu: Remove duplicate include of drm_drv.h
by Wan Jiabing 03 Jun '21

03 Jun '21

drm_drv.h is included at line 28, remove the duplicate here. Signed-off-by: Wan Jiabing <wanjiabing(a)vivo.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 3ff76cb..131cff0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -41,8 +41,6 @@ #include "amdgpu_securedisplay.h" #include "amdgpu_atomfirmware.h" -#include <drm/drm_drv.h> - static int psp_sysfs_init(struct amdgpu_device *adev); static void psp_sysfs_fini(struct amdgpu_device *adev); -- 2.7.4

1 0

[PATCH] drm/msm/dsi: add continuous clock support for 7nm PHY
by Dmitry Baryshkov 03 Jun '21

03 Jun '21

Unlike previous generations, 7nm PHYs are required to collaborate with the host for conitnuos clock mode. Add changes neccessary to enable continuous clock mode in the 7nm DSI PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/dsi/dsi.h | 4 +++- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 12 ++++++++---- drivers/gpu/drm/msm/dsi/dsi_manager.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 15 +++++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 17 +++++++++++++++++ 7 files changed, 48 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 7abfeab08165..c4e7cace120c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -108,7 +108,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host); int msm_dsi_host_disable(struct mipi_dsi_host *host); int msm_dsi_host_power_on(struct mipi_dsi_host *host, struct msm_dsi_phy_shared_timings *phy_shared_timings, - bool is_dual_dsi); + bool is_dual_dsi, struct msm_dsi_phy *phy); int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); @@ -173,6 +173,8 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy); +bool msm_dsi_phy_needs_hs_phy_sel(struct msm_dsi_phy *phy); +void msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable); #endif /* __DSI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 50eb4d1b8fdd..b1b668ff7e10 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -511,6 +511,7 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) #define REG_DSI_LANE_CTRL 0x000000a8 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 +#define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 41e1d0f7ab6e..4507c16c9385 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -835,7 +835,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( } static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, - struct msm_dsi_phy_shared_timings *phy_shared_timings) + struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) { u32 flags = msm_host->mode_flags; enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; @@ -930,8 +930,12 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); + if (msm_dsi_phy_needs_hs_phy_sel(phy)) + lane_ctrl |= DSI_LANE_CTRL_HS_REQ_SEL_PHY; dsi_write(msm_host, REG_DSI_LANE_CTRL, lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); + if (msm_dsi_phy_needs_hs_phy_sel(phy)) + msm_dsi_phy_set_continuous_clock(phy, enable); } data |= DSI_CTRL_ENABLE; @@ -2360,7 +2364,7 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) int msm_dsi_host_power_on(struct mipi_dsi_host *host, struct msm_dsi_phy_shared_timings *phy_shared_timings, - bool is_dual_dsi) + bool is_dual_dsi, struct msm_dsi_phy *phy) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; @@ -2400,7 +2404,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, dsi_timing_setup(msm_host, is_dual_dsi); dsi_sw_reset(msm_host); - dsi_ctrl_config(msm_host, true, phy_shared_timings); + dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); if (msm_host->disp_en_gpio) gpiod_set_value(msm_host->disp_en_gpio, 1); @@ -2431,7 +2435,7 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host) goto unlock_ret; } - dsi_ctrl_config(msm_host, false, NULL); + dsi_ctrl_config(msm_host, false, NULL, NULL); if (msm_host->disp_en_gpio) gpiod_set_value(msm_host->disp_en_gpio, 0); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index e138a0c16085..082a20565886 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -382,7 +382,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) return; - ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi); + ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi, msm_dsi->phy); if (ret) { pr_err("%s: power on host %d failed, %d\n", __func__, id, ret); goto host_on_fail; @@ -390,7 +390,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (is_dual_dsi && msm_dsi1) { ret = msm_dsi_host_power_on(msm_dsi1->host, - &phy_shared_timings[DSI_1], is_dual_dsi); + &phy_shared_timings[DSI_1], is_dual_dsi, msm_dsi->phy); if (ret) { pr_err("%s: power on host1 failed, %d\n", __func__, ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ccbd19f7d9cf..c2c7a46463ac 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -851,6 +851,21 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, phy->usecase = uc; } +bool msm_dsi_phy_needs_hs_phy_sel(struct msm_dsi_phy *phy) +{ + if (!phy) + return false; + return phy->cfg->needs_continuous_clock; +} + +void msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) +{ + if (!phy || !phy->cfg->ops.set_continuous_clock) + return; + + phy->cfg->ops.set_continuous_clock(phy, enable); +} + int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, struct clk **byte_clk_provider, struct clk **pixel_clk_provider) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 94a77ac364d3..16d974f4d536 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -24,6 +24,7 @@ struct msm_dsi_phy_ops { void (*disable)(struct msm_dsi_phy *phy); void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); + void (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); }; struct msm_dsi_phy_cfg { @@ -38,6 +39,7 @@ struct msm_dsi_phy_cfg { const int quirks; bool has_phy_regulator; bool has_phy_lane; + bool needs_continuous_clock; }; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index e76ce40a12ab..771fb31eb607 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -930,6 +930,19 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, return 0; } +static void dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) +{ + void __iomem *base = phy->base; + u32 data; + + data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1); + if (enable) + data |= BIT(5) | BIT(6); + else + data &= ~(BIT(5) | BIT(6)); + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data); +} + static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) { void __iomem *base = phy->base; @@ -970,12 +983,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .pll_init = dsi_pll_7nm_init, .save_pll_state = dsi_7nm_pll_save_state, .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, }, .min_pll_rate = 600000000UL, .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V4_1, + .needs_continuous_clock = true, }; const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { @@ -992,9 +1007,11 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .pll_init = dsi_pll_7nm_init, .save_pll_state = dsi_7nm_pll_save_state, .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .needs_continuous_clock = true, }; -- 2.30.2

2 1

(no subject)
by Dmitry Baryshkov 02 Jun '21

02 Jun '21

>From Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> # This line is ignored. From: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> Reply-To: Subject: [PATCH v2 0/6] drm/msm/dpu: simplify RM code In-Reply-To: There is no need to request most of hardware blocks through the resource manager (RM), since typically there is 1:1 or N:1 relationship between corresponding blocks. Each LM is tied to the single PP. Each MERGE_3D can be used by the specified pair of PPs. Each DSPP is also tied to single LM. So instead of allocating them through the RM, get them via static configuration. Depends on: https://lore.kernel.org/linux-arm-msm/20210515190909.1809050-1-dmitry.barys… Changes since v1: - Split into separate patch series to ease review. ---------------------------------------------------------------- Dmitry Baryshkov (6): drm/msm/dpu: get DSPP blocks directly rather than through RM drm/msm/dpu: get MERGE_3D blocks directly rather than through RM drm/msm/dpu: get PINGPONG blocks directly rather than through RM drm/msm/dpu: get INTF blocks directly rather than through RM drm/msm/dpu: drop unused lm_max_width from RM drm/msm/dpu: simplify peer LM handling drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 54 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 8 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 310 ++------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 18 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 +- 16 files changed, 115 insertions(+), 401 deletions(-)

2 9

[pull] amdgpu, amdkfd, radeon, drm drm-next-5.14
by Alex Deucher 02 Jun '21

02 Jun '21

Hi Dave, Daniel, More new stuff for 5.14. The following changes since commit 9a91e5e0af5e03940d0eec72c36364a1701de240: Merge tag 'amd-drm-next-5.14-2021-05-21' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-05-21 15:59:05 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.14-2021-06-02 for you to fetch changes up to 7d9c70d23550eb86a1bec1954ccaa8d6ec3a3328: drm/amdgpu: remove unsafe optimization to drop preamble ib (2021-06-01 22:55:39 -0400) ---------------------------------------------------------------- amd-drm-next-5.14-2021-06-02: amdgpu: - GC/MM register access macro clean up for SR-IOV - Beige Goby updates - W=1 Fixes - Aldebaran fixes - Misc display fixes - ACPI ATCS/ATIF handling rework - SR-IOV fixes - RAS fixes - 16bpc fixed point format support - Initial smartshift support - RV/PCO power tuning fixes for suspend/resume - More buffer object subclassing work - Add new INFO query for additional vbios information - Add new placement for preemptable SG buffers amdkfd: - Misc fixes radeon: - W=1 Fixes - Misc cleanups UAPI: - Add new INFO query for additional vbios information Useful for debugging vbios related issues. Proposed umr patch: https://patchwork.freedesktop.org/patch/433297/ - 16bpc fixed point format support IGT test: https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html Proposed Vulkan patch: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecba… - Add a new GEM flag which is only used internally in the kernel driver. Userspace is not allowed to set it. drm: - 16bpc fixed point format fourcc ---------------------------------------------------------------- Alex Deucher (7): drm/amdgpu/display: make backlight setting failure messages debug drm/amdgpu/acpi: unify ATCS handling (v3) drm/amdgpu/apci: switch ATIF/ATCS probe order drm/amdgpu/acpi: fix typo in ATCS handling drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_running drm/amdgpu/acpi: make ATPX/ATCS structures global (v2) drm/amdgpu: bump driver version Alvin Lee (1): drm/amd/display: Implement INBOX0 usage in driver Aric Cyr (1): drm/amd/display: 3.2.137 Asher Song (1): drm/amdgpu: add judgement for dc support Aurabindo Pillai (1): drm/amd/display: take dc_lock in short pulse handler only Baokun Li (1): drm/amd/display: fix warning: ‘update_dsc_caps’ and ‘apply_dsc_policy_for_stream’ defined but not used Bindu Ramamurthy (1): drm/amd/display: Allow bandwidth validation for 0 streams. Chengming Gui (2): drm/amd/pm: Update PPTable struct for beige_goby drm/amd/pm: Correct reserved uint32_t number in beige_goby_PPTable Dan Carpenter (2): drm/amdgpu: add missing unreserve on error drm/amdgpu: Fix an error code in kfd_mem_attach_dmabuf() David M Nieto (3): drm/amdgpu/pm: Update metrics table (v2) drm/amdgpu/pm: add new fields for Navi1x (v3) drm/amdgpu/pm: display vcn pp dpm (v4) Dmytro Laktyushkin (1): drm/amd/display: fix odm scaling Eric Huang (1): drm/amdgpu: Fix a bug on flag table_freed Evan Quan (1): drm/amd/pm: correct MGpuFanBoost setting Fangzhi Zuo (3): drm/amd/display: Retrieve DSC Branch Decoder Caps drm/amd/display: Add Log for SST DSC Determination Policy drm/amd/display: Refactor SST DSC Determination Policy Feifei Xu (1): drm/amd/pm: fix return value in aldebaran_set_mp1_state() Felix Kuehling (2): drm/amdgpu: Add new placement for preemptible SG BOs drm/amdgpu: Use preemptible placement for KFD Guenter Roeck (1): drm/amd/amdkfd: Drop unnecessary NULL check after container_of Jake Wang (1): drm/amd/display: Added support for individual control for multiple back-light instances. James Zhu (7): drm/amdgpu/vcn1: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn2.0: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn2.5: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn3: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg2.0: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg2.5: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg3: add cancel_delayed_work_sync before power gate Jiansong Chen (2): drm/amdgpu: refine amdgpu_fru_get_product_info drm/amdgpu: remove unsafe optimization to drop preamble ib Jiapeng Chong (2): drm/amdgpu: Fix inconsistent indenting amdgpu: remove unreachable code Jiawei Gu (1): drm/amdgpu: Add vbios info ioctl interface Jimmy Kizito (2): drm/amd/display: Update DP link configuration. drm/amd/display: Expand DP module clock recovery API. Kees Cook (1): drm/amd/display: Avoid HDCP over-read and corruption Kevin Wang (3): drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error drm/amdgpu: fix sdma firmware version error in sriov drm/amdgpu: optimize code about format string in gfx_v10_0_init_microcode() Lee Jones (45): drm/radeon/radeon_cs: Fix incorrectly documented function 'radeon_cs_parser_fini' drm/amd/amdgpu/amdgpu_ids: Correct some function name disparity drm/amd/amdgpu/amdgpu_debugfs: Fix a couple of misnamed functions drm/amd/amdgpu/amdgpu_gmc: Fix a little naming related doc-rot drm/amd/amdgpu/cik_sdma: Fix a few incorrectly named functions drm/amd/amdgpu/gfx_v7_0: Repair function names in the documentation drm/amd/amdgpu/si_dma: Fix some function name disparity drm/amd/amdgpu/dce_v6_0: Repair function name of 'si_get_number_of_dram_channels()' drm/radeon/cik: Fix incorrectly named function 'cik_irq_suspend()' drm/radeon/radeon_vm: Fix function naming disparities drm/amd/include/aldebaran_ip_offset: Mark top-level IP_BASE as __maybe_unused drm/amd/amdgpu/gmc_v7_0: Fix potential copy/paste issue drm/amd/amdgpu/mmhub_v9_4: Fix naming disparity with 'mmhub_v9_4_set_fault_enable_default()' drm/amd/amdgpu/gmc_v10_0: Fix potential copy/paste issue drm/radeon/r100: Realign doc header with function 'r100_cs_packet_parse_vline()' drm/amd/amdgpu/gfx_v9_4_2: Mark functions called by reference as static drm/amd/amdgpu/sdma_v2_4: Correct misnamed function 'sdma_v2_4_ring_emit_hdp_flush()' drm/amd/amdgpu/sdma_v4_0: Realign functions with their headers drm/amd/amdgpu/sdma_v5_0: Fix typo in function name drm/amd/amdgpu/amdgpu_vce: Fix a few incorrectly named functions drm/amd/amdgpu/sdma_v5_2: Repair typo in function name drm/amd/amdgpu/vcn_v1_0: Fix some function naming disparity drm/amd/amdgpu/gfx_v10_0: Demote kernel-doc abuse drm/amd/amdgpu/smuio_v13_0: Realign 'smuio_v13_0_is_host_gpu_xgmi_supported()' header drm/amd/pm/inc/smu_v13_0: Move table into the only source file that uses it drm/amd/pm/powerplay/hwmgr/smu7_thermal: Provide function name for 'smu7_fan_ctrl_set_default_mode()' drm/amd/pm/powerplay/hwmgr/vega12_thermal: Provide function name drm/amd/pm/powerplay/hwmgr/vega12_hwmgr: Provide 'vega12_init_smc_table()' function name drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Kernel-doc headers must contain function names drm/amd/pm/powerplay/hwmgr/vega20_hwmgr: Provide function name 'vega20_init_smc_table()' drm/amd/display/dc/bios/command_table_helper: Fix function name for 'dal_cmd_table_helper_transmitter_bp_to_atom()' drm/amd/display/dc/bios/command_table_helper2: Fix function name 'dal_cmd_table_helper_transmitter_bp_to_atom2()' drm/amd/display/dc/bios/bios_parser: Fix formatting and misnaming issues drm/amd/display/amdgpu_dm/amdgpu_dm: Functions must directly follow their headers drm/amd/display/dc/dce/dmub_outbox: Convert over to kernel-doc drm/amd/display/dc/gpio/gpio_service: Pass around correct dce_{version, environment} types drm/amd/display/dc/dce110/dce110_hw_sequencer: Include our own header drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK} drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK drm/amd/amdgpu/amdgpu_device: Make local function static drm/amd/display/amdgpu_dm/amdgpu_dm: Fix kernel-doc formatting issue drm/amd/display/dc/dce110/dce110_hw_sequencer: Include header containing our prototypes drm/amd/display/dc/core/dc: Convert function headers to kernel-doc drm/amd/display/dmub/src/dmub_srv_stat: Convert function header to kernel-doc drm/amd/display/modules/hdcp/hdcp_psp: Remove unused function 'mod_hdcp_hdcp1_get_link_encryption_status()' Luben Tuikov (3): drm/amdgpu: Don't query CE and UE errors drm/amdgpu: Fix RAS function interface drm/amdgpu: Use delayed work to collect RAS error counters Mario Kleiner (5): drm/fourcc: Add 16 bpc fixed point framebuffer formats. drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616. drm/amd/display: Increase linebuffer pixel depth to 36bpp. drm/amd/display: Make assert in DCE's program_bit_depth_reduction more lenient. drm/amd/display: Enable support for 16 bpc fixed-point framebuffers. Mukul Joshi (1): drm/amdgpu: Correctly clear GCEA error status Nicholas Kazlauskas (1): drm/amd/display: Fix GPU scaling regression by FS video support Nirmoy Das (10): drm/amd/display: do not dereference on NULL drm/amd/display: WARN_ON cleanups drm/amdgpu: make sure we unpin the UVD BO drm/amdgpu: add amdgpu_bo_vm bo type drm/amdgpu: move shadow bo validation to VM code drm/admgpu: add two shadow BO helper functions drm/amdgpu: switch to amdgpu_bo_vm for vm code drm/amdgpu: remove unused code drm/amdgpu: do not allocate entries separately drm/amdgpu: flush gart changes after all BO recovery Peng Ju Zhou (9): drm/amdgpu: Indirect register access for Navi12 sriov drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV drm/amdgpu: Change IP init sequence to support PSP program IH_RB_CNTL on NV12 SRIOV Qingqing Zhuo (1): Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue" Rodrigo Siqueira (1): drm/amd/display: Fix overlay validation by considering cursors Roman Li (2): drm/amd/display: Remove redundant safeguards for dmub-srv destroy() drm/amd/display: Fix potential memory leak in DMUB hw_init Sathishkumar S (3): drm/amd/pm: use attr_update if the attr has it drm/amdgpu: support atcs method powershift (v4) drm/amdgpu: enable smart shift on dGPU (v5) Shaokun Zhang (4): drm/amd/display: Remove the repeated declaration drm/radeon/evergreen: Remove the repeated declaration drm/radeon: remove the repeated declaration drm/amd/display: Remove the redundant initialization of local variable Shiwu Zhang (2): drm/amdgpu: fix metadata_size for ubo ioctl queries drm/amdgpu: free the metadata buffer for sg type BOs as well Simon Ser (1): amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic Victor Zhao (1): drm/amd/amdgpu:save psp ring wptr to avoid attack Wenjing Liu (2): drm/amd/display: add exit training mode and update channel coding in LT drm/amd/display: isolate 8b 10b link training sequence into its own function Xiaojian Du (1): drm/amd/pm: retain the fine grain tuning parameters after resume Yu Kuai (1): drm/amd/display: fix gcc set but not used warning of variable 'old_plane_state' Zheng Yongjun (1): drm/amdgpu: Remove unneeded semicolon hvanzyll (1): drm/amd/display: disable desktop VRR when using older flip model pengzhou (1): drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* tony.huang_cp (1): drm/amdgpu: fix typo drivers/gpu/drm/amd/amdgpu/Makefile | 7 +- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 47 +- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 388 +++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 42 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 12 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 41 +- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 32 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 42 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 22 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 88 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 33 +- drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 190 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 63 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 166 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 19 +- drivers/gpu/drm/amd/amdgpu/atom.c | 172 ++++++ drivers/gpu/drm/amd/amdgpu/atom.h | 10 + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 117 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 24 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 27 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 +- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 41 +- drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2 +- drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 93 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 6 +- drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 87 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 + drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 + drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 222 +++++--- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 10 +- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 6 +- .../drm/amd/display/dc/bios/command_table_helper.c | 2 +- .../amd/display/dc/bios/command_table_helper2.c | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 2 + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 + drivers/gpu/drm/amd/display/dc/core/dc.c | 63 +-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 309 +++++++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 577 ++++++++------------- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 + drivers/gpu/drm/amd/display/dc/dc_link.h | 19 +- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 + drivers/gpu/drm/amd/display/dc/dc_types.h | 5 - drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 2 + drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 2 - drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 10 +- .../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 8 + .../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 3 + drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c | 17 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 + .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1 + .../drm/amd/display/dc/dce110/dce110_transform_v.c | 3 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 9 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 12 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 34 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 6 - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 - drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 6 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 1 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 4 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 31 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 5 - drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 - drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 2 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 17 +- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 6 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 2 +- .../gpu/drm/amd/display/dc/dcn301/dcn301_init.c | 1 - drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 + .../drm/amd/display/dc/dml/display_mode_structs.h | 2 + .../gpu/drm/amd/display/dc/dml/display_mode_vba.c | 13 + drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 12 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 70 ++- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 3 - drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 4 - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 - drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../gpu/drm/amd/display/dmub/src/dmub_srv_stat.c | 19 +- .../amd/display/include/gpio_service_interface.h | 4 +- .../drm/amd/display/include/link_service_types.h | 1 + .../drm/amd/display/modules/freesync/freesync.c | 29 +- .../drm/amd/display/modules/hdcp/hdcp1_execution.c | 4 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 13 - .../drm/amd/display/modules/power/power_helpers.c | 15 +- .../drm/amd/display/modules/power/power_helpers.h | 3 +- drivers/gpu/drm/amd/include/aldebaran_ip_offset.h | 2 +- drivers/gpu/drm/amd/include/amd_acpi.h | 18 + drivers/gpu/drm/amd/include/atomfirmware.h | 17 +- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 69 +++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +- .../amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 2 +- drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 6 - .../drm/amd/pm/powerplay/hwmgr/hardwaremanager.c | 3 +- .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 + .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 8 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 26 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 2 +- .../drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 3 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 ++ drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 85 ++- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 14 + drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 33 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 61 ++- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 + drivers/gpu/drm/drm_fourcc.c | 4 + drivers/gpu/drm/radeon/cik.c | 2 +- drivers/gpu/drm/radeon/evergreen.h | 1 - drivers/gpu/drm/radeon/r100.c | 2 +- drivers/gpu/drm/radeon/radeon_asic.h | 2 - drivers/gpu/drm/radeon/radeon_cs.c | 2 +- drivers/gpu/drm/radeon/radeon_vm.c | 4 +- include/drm/drm_atomic.h | 12 + include/uapi/drm/amdgpu_drm.h | 15 + include/uapi/drm/drm_fourcc.h | 7 + 164 files changed, 2705 insertions(+), 1498 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c

1 0

[PATCH 1/2] dma-buf: fix inconsistent debug print v2
by Christian König 02 Jun '21

02 Jun '21

Drop the whole rcu handling since we are holding the resv lock anyway. v2: drop all rcu handling instead. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/dma-buf.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index eadd1eaa2fb5..ee04fb442015 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -1349,15 +1349,14 @@ EXPORT_SYMBOL_GPL(dma_buf_vunmap); #ifdef CONFIG_DEBUG_FS static int dma_buf_debug_show(struct seq_file *s, void *unused) { - int ret; struct dma_buf *buf_obj; struct dma_buf_attachment *attach_obj; struct dma_resv *robj; struct dma_resv_list *fobj; struct dma_fence *fence; - unsigned seq; int count = 0, attach_count, shared_count, i; size_t size = 0; + int ret; ret = mutex_lock_interruptible(&db_list.lock); @@ -1383,33 +1382,25 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused) buf_obj->name ?: ""); robj = buf_obj->resv; - while (true) { - seq = read_seqcount_begin(&robj->seq); - rcu_read_lock(); - fobj = rcu_dereference(robj->fence); - shared_count = fobj ? fobj->shared_count : 0; - fence = rcu_dereference(robj->fence_excl); - if (!read_seqcount_retry(&robj->seq, seq)) - break; - rcu_read_unlock(); - } - + fence = rcu_dereference_protected(robj->fence_excl, + dma_resv_held(robj)); if (fence) seq_printf(s, "\tExclusive fence: %s %s %ssignalled\n", fence->ops->get_driver_name(fence), fence->ops->get_timeline_name(fence), dma_fence_is_signaled(fence) ? "" : "un"); + + fobj = rcu_dereference_protected(robj->fence, + dma_resv_held(robj)); + shared_count = fobj ? fobj->shared_count : 0; for (i = 0; i < shared_count; i++) { - fence = rcu_dereference(fobj->shared[i]); - if (!dma_fence_get_rcu(fence)) - continue; + fence = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(robj)); seq_printf(s, "\tShared fence: %s %s %ssignalled\n", fence->ops->get_driver_name(fence), fence->ops->get_timeline_name(fence), dma_fence_is_signaled(fence) ? "" : "un"); - dma_fence_put(fence); } - rcu_read_unlock(); seq_puts(s, "\tAttached Devices:\n"); attach_count = 0; -- 2.25.1

2 3

[PATCH] drm/ttm: nuke VM_MIXEDMAP on BO mappings
by Christian König 02 Jun '21

02 Jun '21

We discussed if that is really the right approach for quite a while now, but digging deeper into a bug report on arm turned out that this is actually horrible broken right now. The reason for this is that vmf_insert_mixed_prot() always tries to grab a reference to the underlaying page on architectures without ARCH_HAS_PTE_SPECIAL and as far as I can see also enabled GUP. So nuke using VM_MIXEDMAP here and use VM_PFNMAP instead. Also set VM_SHARED, not 100% sure if that is needed with VM_PFNMAP, but better save than sorry. Signed-off-by: Christian König <christian.koenig(a)amd.com> Bugs: https://gitlab.freedesktop.org/drm/amd/-/issues/1606#note_936174 --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 9bd15cb39145..bf86ae849340 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -359,12 +359,7 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, * at arbitrary times while the data is mmap'ed. * See vmf_insert_mixed_prot() for a discussion. */ - if (vma->vm_flags & VM_MIXEDMAP) - ret = vmf_insert_mixed_prot(vma, address, - __pfn_to_pfn_t(pfn, PFN_DEV), - prot); - else - ret = vmf_insert_pfn_prot(vma, address, pfn, prot); + ret = vmf_insert_pfn_prot(vma, address, pfn, prot); /* Never error on prefaulted PTEs */ if (unlikely((ret & VM_FAULT_ERROR))) { @@ -411,15 +406,9 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) pfn = page_to_pfn(page); /* Prefault the entire VMA range right away to avoid further faults */ - for (address = vma->vm_start; address < vma->vm_end; address += PAGE_SIZE) { - - if (vma->vm_flags & VM_MIXEDMAP) - ret = vmf_insert_mixed_prot(vma, address, - __pfn_to_pfn_t(pfn, PFN_DEV), - prot); - else - ret = vmf_insert_pfn_prot(vma, address, pfn, prot); - } + for (address = vma->vm_start; address < vma->vm_end; + address += PAGE_SIZE) + ret = vmf_insert_pfn_prot(vma, address, pfn, prot); return ret; } @@ -576,14 +565,10 @@ static void ttm_bo_mmap_vma_setup(struct ttm_buffer_object *bo, struct vm_area_s vma->vm_private_data = bo; - /* - * We'd like to use VM_PFNMAP on shared mappings, where - * (vma->vm_flags & VM_SHARED) != 0, for performance reasons, - * but for some reason VM_PFNMAP + x86 PAT + write-combine is very - * bad for performance. Until that has been sorted out, use - * VM_MIXEDMAP on all mappings. See freedesktop.org bug #75719 + /* Enforce VM_SHARED here since no driver backend actually supports COW + * on TTM buffer object mappings. */ - vma->vm_flags |= VM_MIXEDMAP; + vma->vm_flags |= VM_PFNMAP | VM_SHARED; vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; } -- 2.25.1

4 9

Re: [Freedreno] [RESEND 14/26] drm/msm/dp/dp_link: Fix some potential doc-rot
by abhinavk＠codeaurora.org 02 Jun '21

02 Jun '21

On 2021-06-02 07:32, Lee Jones wrote: > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/msm/dp/dp_link.c:374: warning: expecting prototype > for dp_parse_video_pattern_params(). Prototype was for > dp_link_parse_video_pattern_params() instead > drivers/gpu/drm/msm/dp/dp_link.c:573: warning: expecting prototype > for dp_parse_phy_test_params(). Prototype was for > dp_link_parse_phy_test_params() instead > drivers/gpu/drm/msm/dp/dp_link.c:975: warning: expecting prototype > for dp_link_process_downstream_port_status_change(). Prototype was for > dp_link_process_ds_port_status_change() instead > > Cc: Rob Clark <robdclark(a)gmail.com> > Cc: Sean Paul <sean(a)poorly.run> > Cc: David Airlie <airlied(a)linux.ie> > Cc: Daniel Vetter <daniel(a)ffwll.ch> > Cc: Chandan Uddaraju <chandanu(a)codeaurora.org> > Cc: Kuogee Hsieh <khsieh(a)codeaurora.org> > Cc: linux-arm-msm(a)vger.kernel.org > Cc: dri-devel(a)lists.freedesktop.org > Cc: freedreno(a)lists.freedesktop.org > Signed-off-by: Lee Jones <lee.jones(a)linaro.org> Reviewed-by: Abhinav Kumar <abhinavk(a)codeaurora.org> > --- > drivers/gpu/drm/msm/dp/dp_link.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_link.c > b/drivers/gpu/drm/msm/dp/dp_link.c > index be986da78c4a5..1099604bd1c86 100644 > --- a/drivers/gpu/drm/msm/dp/dp_link.c > +++ b/drivers/gpu/drm/msm/dp/dp_link.c > @@ -364,7 +364,7 @@ static int dp_link_parse_timing_params3(struct > dp_link_private *link, > } > > /** > - * dp_parse_video_pattern_params() - parses video pattern parameters > from DPCD > + * dp_link_parse_video_pattern_params() - parses video pattern > parameters from DPCD > * @link: Display Port Driver data > * > * Returns 0 if it successfully parses the video link pattern and the > link > @@ -563,7 +563,7 @@ static int > dp_link_parse_link_training_params(struct dp_link_private *link) > } > > /** > - * dp_parse_phy_test_params() - parses the phy link parameters > + * dp_link_parse_phy_test_params() - parses the phy link parameters > * @link: Display Port Driver data > * > * Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is > being > @@ -961,7 +961,7 @@ static int > dp_link_process_link_status_update(struct dp_link_private *link) > } > > /** > - * dp_link_process_downstream_port_status_change() - process port > status changes > + * dp_link_process_ds_port_status_change() - process port status > changes > * @link: Display Port Driver data > * > * This function will handle downstream port updates that are > initiated by

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dri-devel June 2021