dri-devel July 2021

dri-devel@lists.freedesktop.org

321 participants
829 discussions

[PATCH v4] drm/panel: Add support for E Ink VB3300-KCA
by Alistair Francis 31 Jul '21

31 Jul '21

Add support for the 10.3" E Ink panel described at: https://www.eink.com/product.html?type=productdetail&id=7 Signed-off-by: Alistair Francis <alistair(a)alistair23.me> Acked-by: Rob Herring <robh(a)kernel.org> --- v4: - Fixup alphebetical sorting .../bindings/display/panel/panel-simple.yaml | 2 ++ .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ drivers/gpu/drm/panel/panel-simple.c | 29 +++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index b3797ba2698b..799e20222551 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -128,6 +128,8 @@ properties: # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch - edt,etm0700g0dh6 - edt,etm0700g0edh6 + # E Ink VB3300-KCA + - eink,vb3300-kca # Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel - evervision,vgg804821 # Foxlink Group 5" WVGA TFT LCD panel diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 71da86e7b3a2..31745c45dd92 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -339,6 +339,8 @@ patternProperties: description: eGalax_eMPIA Technology Inc "^einfochips,.*": description: Einfochips + "^eink,.*": + description: E Ink Corporation "^elan,.*": description: Elan Microelectronic Corp. "^element14,.*": diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 21939d4352cf..8d6317b85465 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2046,6 +2046,32 @@ static const struct panel_desc edt_etm0700g0bdh6 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, }; +static const struct display_timing eink_vb3300_kca_timing = { + .pixelclock = { 40000000, 40000000, 40000000 }, + .hactive = { 334, 334, 334 }, + .hfront_porch = { 1, 1, 1 }, + .hback_porch = { 1, 1, 1 }, + .hsync_len = { 1, 1, 1 }, + .vactive = { 1405, 1405, 1405 }, + .vfront_porch = { 1, 1, 1 }, + .vback_porch = { 1, 1, 1 }, + .vsync_len = { 1, 1, 1 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, +}; + +static const struct panel_desc eink_vb3300_kca = { + .timings = &eink_vb3300_kca_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 157, + .height = 209, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, +}; + static const struct display_timing evervision_vgg804821_timing = { .pixelclock = { 27600000, 33300000, 50000000 }, .hactive = { 800, 800, 800 }, @@ -4350,6 +4376,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "edt,etm0700g0edh6", .data = &edt_etm0700g0bdh6, + }, { + .compatible = "eink,vb3300-kca", + .data = &eink_vb3300_kca, }, { .compatible = "evervision,vgg804821", .data = &evervision_vgg804821, -- 2.31.1

2 2

[PATCH v2 0/6] drm/panel: atna33xc20: Fix the Samsung ATNA33XC20 panel
by Douglas Anderson 31 Jul '21

31 Jul '21

The overall goal of this series is to make the Samsung ATNA33XC20 panel work more properly. As part of this, we have: * A bugfix for the recently abstracted DP AUX backlight code. * A bugfix for the sequencing of the ti-sn65dsi86 bridge driver. * Removal of the panel from panel-simple and moving it to its own driver. If the bugfixes look good but the rest of the series needs work then those could land early on their own. There's no real compile time dependency on the bugfixes, things are just glitchier without them. NOTE: this series will (slightly) conflict with my other recent series making eDP panels probable [1]. I'll re-post that one atop this one. It should be noted that the fact that the Samsung ATNA33XC20 needs its own panel driver means that it _can't_ handled as a probed driver. I think this is fine, at least for now. I don't think it would be easy to make a unified design with this panel and other panels given that it's an AMOLED panel and has a whole bunch of different components on board. As discussed in IRC, the only difference in v2 is the addition of a "Fixes" tag to patch #3 and the collection of Reviews/Acks from Sean and Robert. If people feel that this is ready to land today then I can help land it (please let me know). Otherwise I'm happy for someone else to actually do the commit next week (I'm on vacation) or I can take it when I get back. [1] https://lore.kernel.org/r/20210723002146.1962910-1-dianders@chromium.org/ Changes in v2: - Added Fixes tag as requested by Sam. Douglas Anderson (6): drm/dp: Don't zero PWMGEN_BIT_COUNT when driver_pwm_freq_hz not specified drm/bridge: ti-sn65dsi86: Fix power off sequence drm/bridge: ti-sn65dsi86: Add some 100 us delays Revert "drm/panel-simple: Add Samsung ATNA33XC20" Revert "drm/panel-simple: Support for delays between GPIO & regulator" drm/panel: atna33xc20: Introduce the Samsung ATNA33XC20 panel drivers/gpu/drm/bridge/ti-sn65dsi86.c | 17 +- drivers/gpu/drm/drm_dp_helper.c | 10 +- drivers/gpu/drm/panel/Kconfig | 12 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-samsung-atna33xc20.c | 366 ++++++++++++++++++ drivers/gpu/drm/panel/panel-simple.c | 61 --- 6 files changed, 398 insertions(+), 69 deletions(-) create mode 100644 drivers/gpu/drm/panel/panel-samsung-atna33xc20.c -- 2.32.0.554.ge1b32706d8-goog

2 8

[PATCH v2 0/3] Remove all strcpy() uses
by Len Baker 31 Jul '21

31 Jul '21

strcpy() performs no bounds checking on the destination buffer. This could result in linear overflows beyond the end of the buffer, leading to all kinds of misbehaviors. So, this serie removes all strcpy uses from the "staging/fbtft" subsystem. Also, refactor the code a bit to follow the kernel coding-style and avoid unnecessary variable initialization. Changelog v1 -> v2 - Add two new commits to clean the code. - Use the "%*ph" format specifier instead of strscpy() function (Geert Uytterhoeven) Len Baker (3): staging/fbtft: Remove all strcpy() uses staging/fbtft: Remove unnecessary variable initialization staging/fbtft: Fix braces coding style drivers/staging/fbtft/fbtft-core.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) -- 2.25.1

3 9

[PATCH v6 00/14] drm/i915/guc/slpc: Enable GuC based power management features
by Vinay Belgaumkar 31 Jul '21

31 Jul '21

This series enables Single Loop Power Control (SLPC) feature in GuC. GuC implements various power management algorithms as part of it's operation. These need to be specifically enabled by KMD. They replace the legacy host based management of these features. With this series, we will enable two PM features - GTPerf and GuCRC. These are the Turbo and RC6 equivalents of the host based version. GuC provides various interfaces via host-to-guc messaging, which allows KMD to enable these features after GuC is loaded and GuC submission is enabled. We will specifically disable the IA/GT Balancer and Duty Cycle control features in SLPC. To enable GTPerf, KMD sends a specific h2g message after setting up some shared data structures. As part of this, we will gate host RPS as well. GuC takes over the duties of requesting frequencies by monitoring GPU busyness. We can influence what GuC requests by modifying the min and max frequencies setup by SLPC through the sysfs interfaces that have been exposed by legacy Turbo. SLPC typically requests efficient frequency instead of minimum frequency to optimize performance. It also does not necessarily stick to platform max, and can request frequencies that are much higher since pcode will ultimately grant the appropriate values. However, we will force it to adhere to platform min and max values so as to maintain legacy behavior. SLPC does not have the concept of waitboost, so the boost_freq sysfs will show a '0' value for now. There is a patch forthcoming to ensure the interface is not exposed when SLPC is enabled. GuCRC is enabled similarly through a h2g message. We still need to enable RC6 feature bit (GEN6_RC_CTL_RC6_ENABLE) before we send this out. Render/Media power gating still needs to be enabled by host as before. GuC will take care of setting up the hysterisis values for RC6, host does not need to set this up anymore. v2: Address review comments (Michal W) v3: More comments, optimizations (Michal W) v4: Address comments (Michal W, Matt Roper, Matthew Brost) v5: Address checkpatch issues and some more comments v6: Error checking in patch 11 (Michal W) Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar(a)intel.com> Vinay Belgaumkar (14): drm/i915/guc/slpc: Initial definitions for SLPC drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled drm/i915/guc/slpc: Adding SLPC communication interfaces drm/i915/guc/slpc: Allocate, initialize and release SLPC drm/i915/guc/slpc: Enable SLPC and add related H2G events drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable drm/i915/guc/slpc: Add methods to set min/max frequency drm/i915/guc/slpc: Add get max/min freq hooks drm/i915/guc/slpc: Add debugfs for SLPC info drm/i915/guc/slpc: Enable ARAT timer interrupt drm/i915/guc/slpc: Cache platform frequency limits drm/i915/guc/slpc: Sysfs hooks for SLPC drm/i915/guc/slpc: Add SLPC selftest drm/i915/guc/rc: Setup and enable GuCRC feature drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 47 +- drivers/gpu/drm/i915/gt/intel_rps.c | 201 ++++++ drivers/gpu/drm/i915/gt/intel_rps.h | 10 + drivers/gpu/drm/i915/gt/selftest_slpc.c | 311 +++++++++ .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 7 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 +++++++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 17 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 + .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 22 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++ drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 626 ++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 42 ++ .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 29 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 - drivers/gpu/drm/i915/gt/uc/intel_uc.c | 25 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 + drivers/gpu/drm/i915/i915_pmu.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/i915_sysfs.c | 83 +-- .../drm/i915/selftests/i915_live_selftests.h | 1 + 24 files changed, 1707 insertions(+), 90 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h -- 2.25.0

2 15

[PATCH] scsi: csiostor: fix possible null-pointer dereference in csio_eh_lun_reset_handler()
by Tuo Li 31 Jul '21

31 Jul '21

The variable rn is checked in: if (!rn) If rn is NULL, the program goes to the label fail: fail: CSIO_INC_STATS(rn, n_lun_rst_fail); However, rn is dereferenced in this macro: #define CSIO_INC_STATS(elem, val) ((elem)->stats.val++) To fix this possible null-pointer dereference, the function returns FAILED directly if rn is NULL. Reported-by: TOTE Robot <oslab(a)tsinghua.edu.cn> Signed-off-by: Tuo Li <islituo(a)gmail.com> --- drivers/scsi/csiostor/csio_scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/csiostor/csio_scsi.c b/drivers/scsi/csiostor/csio_scsi.c index 56b9ad0a1ca0..df0bf8348860 100644 --- a/drivers/scsi/csiostor/csio_scsi.c +++ b/drivers/scsi/csiostor/csio_scsi.c @@ -2070,7 +2070,7 @@ csio_eh_lun_reset_handler(struct scsi_cmnd *cmnd) struct csio_scsi_level_data sld; if (!rn) - goto fail; + return FAILED; csio_dbg(hw, "Request to reset LUN:%llu (ssni:0x%x tgtid:%d)\n", cmnd->device->lun, rn->flowid, rn->scsi_id); -- 2.25.1

1 0

[PATCH 0/7] drm: Extend COMPILE_TEST support to some ARM drivers
by Laurent Pinchart 31 Jul '21

31 Jul '21

Hello, This patch series stems from subsystem-wide changes I wanted to compile-test with an ARM64 cross-compiler. My laziness to fire a 32-bit ARM build probably resulted in more time being spent writing these patches, but hopefully they'll turn out to be useful for more people :-) Patches 1/7 and 2/7 are fixes for compilation warnings on 64-bit platforms in the omapdrm and sti-drm drivers. They are a dependency for the Kconfig changes that follow to avoid introducing build warnings, but could also be merged before. Patches 3/7 to 7/7 enable compilation of the imx-dcss, omapdrm, sti-drm, tegra-drm and tilcdc drivers on ARM64 with COMPILE_TEST. The patches are independent from each other, so they can be picked by their respective maintainers. We could also extend test compilation to more architecture, but I didn't want to remove all dependencies on ARM or ARM64 at this point for fear or triggering build warnings that I wouldn't be able to catch locally. If there's a consensus that fully relaxing the platform requirement is better, I can submit a new version that does so and rely on the 0day bot to catch issues. Laurent Pinchart (7): drm/omap: Cast pointer to integer safely drm/sti: Use correct printk format specifiers for size_t drm/imx/dcss: Enable COMPILE_TEST on all ARM64 platforms drm/omap: Enable COMPILE_TEST on all ARM and ARM64 platforms drm/sti: Enable COMPILE_TEST on all ARM and ARM64 platforms drm/tegra: Enable COMPILE_TEST on all ARM64 platforms drm/tilcdc: Enable COMPILE_TEST on all ARM64 platforms drivers/gpu/drm/imx/dcss/Kconfig | 3 ++- drivers/gpu/drm/omapdrm/Kconfig | 2 +- drivers/gpu/drm/omapdrm/omap_drv.c | 2 +- drivers/gpu/drm/sti/Kconfig | 3 ++- drivers/gpu/drm/sti/sti_hqvdp.c | 4 ++-- drivers/gpu/drm/tegra/Kconfig | 2 +- drivers/gpu/drm/tilcdc/Kconfig | 3 ++- drivers/gpu/host1x/Kconfig | 2 +- 8 files changed, 12 insertions(+), 9 deletions(-) -- Regards, Laurent Pinchart

8 17

[PATCH 0/5] drm/msm/dp: Support multiple DP instances and add sc8180x
by Bjorn Andersson 31 Jul '21

31 Jul '21

The current implementation supports a single DP instance and the DPU code will only match it against INTF_DP instance 0. These patches extends this to allow multiple DP instances and support for matching against DP instances beyond 0. This is based on v4 of Dmitry's work on multiple DSI interfaces: https://lore.kernel.org/linux-arm-msm/20210717124016.316020-1-dmitry.barysh… With that in place add SC8180x DP and eDP controllers. Bjorn Andersson (5): drm/msm/dp: Remove global g_dp_display variable drm/msm/dp: Modify prototype of encoder based API drm/msm/dp: Support up to 3 DP controllers dt-bindings: msm/dp: Add SC8180x compatibles drm/msm/dp: Add sc8180x DP controllers .../bindings/display/msm/dp-controller.yaml | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 60 +++--- .../gpu/drm/msm/disp/msm_disp_snapshot_util.c | 8 +- drivers/gpu/drm/msm/dp/dp_display.c | 183 +++++++++++++----- drivers/gpu/drm/msm/msm_drv.h | 33 ++-- 6 files changed, 200 insertions(+), 103 deletions(-) -- 2.29.2

4 15

Re: [Intel-gfx] [PATCH] drm/i915/xehp: Fix missing sentinel on mcr_ranges_xehp
by Lucas De Marchi 31 Jul '21

31 Jul '21

I guess I forgot to Cc dri-devel. Doing it now. Lucas De Marchi On Fri, Jul 30, 2021 at 12:18:59PM -0700, Matt Roper wrote: >On Fri, Jul 30, 2021 at 12:11:15PM -0700, Lucas De Marchi wrote: >> There's a missing sentinel since we are not using ARRAY_SIZE(), but rather >> checking that the .start is 0 to stop the iteration in mcr_range(). >> >> BUG: KASAN: global-out-of-bounds in mcr_range.isra.0+0x69/0xa0 [i915] >> Read of size 4 at addr ffffffffa0889928 by task modprobe/3881 >> >> Fixes: d8905ba705ab ("drm/i915/xehp: Define multicast register ranges") >> Signed-off-by: Lucas De Marchi <lucas.demarchi(a)intel.com> > >Reviewed-by: Matt Roper <matthew.d.roper(a)intel.com> > >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 9173df59821a..053fa7251cd0 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -2000,6 +2000,7 @@ static const struct mcr_range mcr_ranges_xehp[] = { >> { .start = 0xdc00, .end = 0xffff }, >> { .start = 0x17000, .end = 0x17fff }, >> { .start = 0x24a00, .end = 0x24a7f }, >> + {}, >> }; >> >> static bool mcr_range(struct drm_i915_private *i915, u32 offset) >> -- >> 2.31.1 >> > >-- >Matt Roper >Graphics Software Engineer >VTT-OSGC Platform Enablement >Intel Corporation >(916) 356-2795

1 0

[PATCH 1/3] dma-buf: nuke seqno-fence
by Christian König 30 Jul '21

30 Jul '21

Entirely unused. Signed-off-by: Christian König <christian.koenig(a)amd.com> --- drivers/dma-buf/Makefile | 2 +- drivers/dma-buf/seqno-fence.c | 71 ---------------------- include/linux/seqno-fence.h | 109 ---------------------------------- 3 files changed, 1 insertion(+), 181 deletions(-) delete mode 100644 drivers/dma-buf/seqno-fence.c delete mode 100644 include/linux/seqno-fence.h diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 40d81f23cacf..1ef021273a06 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ - dma-resv.o seqno-fence.o + dma-resv.o obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o obj-$(CONFIG_DMABUF_HEAPS) += heaps/ obj-$(CONFIG_SYNC_FILE) += sync_file.o diff --git a/drivers/dma-buf/seqno-fence.c b/drivers/dma-buf/seqno-fence.c deleted file mode 100644 index bfe14e94c488..000000000000 --- a/drivers/dma-buf/seqno-fence.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * seqno-fence, using a dma-buf to synchronize fencing - * - * Copyright (C) 2012 Texas Instruments - * Copyright (C) 2012-2014 Canonical Ltd - * Authors: - * Rob Clark <robdclark(a)gmail.com> - * Maarten Lankhorst <maarten.lankhorst(a)canonical.com> - */ - -#include <linux/slab.h> -#include <linux/export.h> -#include <linux/seqno-fence.h> - -static const char *seqno_fence_get_driver_name(struct dma_fence *fence) -{ - struct seqno_fence *seqno_fence = to_seqno_fence(fence); - - return seqno_fence->ops->get_driver_name(fence); -} - -static const char *seqno_fence_get_timeline_name(struct dma_fence *fence) -{ - struct seqno_fence *seqno_fence = to_seqno_fence(fence); - - return seqno_fence->ops->get_timeline_name(fence); -} - -static bool seqno_enable_signaling(struct dma_fence *fence) -{ - struct seqno_fence *seqno_fence = to_seqno_fence(fence); - - return seqno_fence->ops->enable_signaling(fence); -} - -static bool seqno_signaled(struct dma_fence *fence) -{ - struct seqno_fence *seqno_fence = to_seqno_fence(fence); - - return seqno_fence->ops->signaled && seqno_fence->ops->signaled(fence); -} - -static void seqno_release(struct dma_fence *fence) -{ - struct seqno_fence *f = to_seqno_fence(fence); - - dma_buf_put(f->sync_buf); - if (f->ops->release) - f->ops->release(fence); - else - dma_fence_free(&f->base); -} - -static signed long seqno_wait(struct dma_fence *fence, bool intr, - signed long timeout) -{ - struct seqno_fence *f = to_seqno_fence(fence); - - return f->ops->wait(fence, intr, timeout); -} - -const struct dma_fence_ops seqno_fence_ops = { - .get_driver_name = seqno_fence_get_driver_name, - .get_timeline_name = seqno_fence_get_timeline_name, - .enable_signaling = seqno_enable_signaling, - .signaled = seqno_signaled, - .wait = seqno_wait, - .release = seqno_release, -}; -EXPORT_SYMBOL(seqno_fence_ops); diff --git a/include/linux/seqno-fence.h b/include/linux/seqno-fence.h deleted file mode 100644 index 3cca2b8fac43..000000000000 --- a/include/linux/seqno-fence.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * seqno-fence, using a dma-buf to synchronize fencing - * - * Copyright (C) 2012 Texas Instruments - * Copyright (C) 2012 Canonical Ltd - * Authors: - * Rob Clark <robdclark(a)gmail.com> - * Maarten Lankhorst <maarten.lankhorst(a)canonical.com> - */ - -#ifndef __LINUX_SEQNO_FENCE_H -#define __LINUX_SEQNO_FENCE_H - -#include <linux/dma-fence.h> -#include <linux/dma-buf.h> - -enum seqno_fence_condition { - SEQNO_FENCE_WAIT_GEQUAL, - SEQNO_FENCE_WAIT_NONZERO -}; - -struct seqno_fence { - struct dma_fence base; - - const struct dma_fence_ops *ops; - struct dma_buf *sync_buf; - uint32_t seqno_ofs; - enum seqno_fence_condition condition; -}; - -extern const struct dma_fence_ops seqno_fence_ops; - -/** - * to_seqno_fence - cast a fence to a seqno_fence - * @fence: fence to cast to a seqno_fence - * - * Returns NULL if the fence is not a seqno_fence, - * or the seqno_fence otherwise. - */ -static inline struct seqno_fence * -to_seqno_fence(struct dma_fence *fence) -{ - if (fence->ops != &seqno_fence_ops) - return NULL; - return container_of(fence, struct seqno_fence, base); -} - -/** - * seqno_fence_init - initialize a seqno fence - * @fence: seqno_fence to initialize - * @lock: pointer to spinlock to use for fence - * @sync_buf: buffer containing the memory location to signal on - * @context: the execution context this fence is a part of - * @seqno_ofs: the offset within @sync_buf - * @seqno: the sequence # to signal on - * @cond: fence wait condition - * @ops: the fence_ops for operations on this seqno fence - * - * This function initializes a struct seqno_fence with passed parameters, - * and takes a reference on sync_buf which is released on fence destruction. - * - * A seqno_fence is a dma_fence which can complete in software when - * enable_signaling is called, but it also completes when - * (s32)((sync_buf)[seqno_ofs] - seqno) >= 0 is true - * - * The seqno_fence will take a refcount on the sync_buf until it's - * destroyed, but actual lifetime of sync_buf may be longer if one of the - * callers take a reference to it. - * - * Certain hardware have instructions to insert this type of wait condition - * in the command stream, so no intervention from software would be needed. - * This type of fence can be destroyed before completed, however a reference - * on the sync_buf dma-buf can be taken. It is encouraged to re-use the same - * dma-buf for sync_buf, since mapping or unmapping the sync_buf to the - * device's vm can be expensive. - * - * It is recommended for creators of seqno_fence to call dma_fence_signal() - * before destruction. This will prevent possible issues from wraparound at - * time of issue vs time of check, since users can check dma_fence_is_signaled() - * before submitting instructions for the hardware to wait on the fence. - * However, when ops.enable_signaling is not called, it doesn't have to be - * done as soon as possible, just before there's any real danger of seqno - * wraparound. - */ -static inline void -seqno_fence_init(struct seqno_fence *fence, spinlock_t *lock, - struct dma_buf *sync_buf, uint32_t context, - uint32_t seqno_ofs, uint32_t seqno, - enum seqno_fence_condition cond, - const struct dma_fence_ops *ops) -{ - BUG_ON(!fence || !sync_buf || !ops); - BUG_ON(!ops->wait || !ops->enable_signaling || - !ops->get_driver_name || !ops->get_timeline_name); - - /* - * ops is used in dma_fence_init for get_driver_name, so needs to be - * initialized first - */ - fence->ops = ops; - dma_fence_init(&fence->base, &seqno_fence_ops, lock, context, seqno); - get_dma_buf(sync_buf); - fence->sync_buf = sync_buf; - fence->seqno_ofs = seqno_ofs; - fence->condition = cond; -} - -#endif /* __LINUX_SEQNO_FENCE_H */ -- 2.25.1

4 14

[PATCH v5 00/14] drm/i915/guc/slpc: Enable GuC based power management features
by Vinay Belgaumkar 30 Jul '21

30 Jul '21

This series enables Single Loop Power Control (SLPC) feature in GuC. GuC implements various power management algorithms as part of it's operation. These need to be specifically enabled by KMD. They replace the legacy host based management of these features. With this series, we will enable two PM features - GTPerf and GuCRC. These are the Turbo and RC6 equivalents of the host based version. GuC provides various interfaces via host-to-guc messaging, which allows KMD to enable these features after GuC is loaded and GuC submission is enabled. We will specifically disable the IA/GT Balancer and Duty Cycle control features in SLPC. To enable GTPerf, KMD sends a specific h2g message after setting up some shared data structures. As part of this, we will gate host RPS as well. GuC takes over the duties of requesting frequencies by monitoring GPU busyness. We can influence what GuC requests by modifying the min and max frequencies setup by SLPC through the sysfs interfaces that have been exposed by legacy Turbo. SLPC typically requests efficient frequency instead of minimum frequency to optimize performance. It also does not necessarily stick to platform max, and can request frequencies that are much higher since pcode will ultimately grant the appropriate values. However, we will force it to adhere to platform min and max values so as to maintain legacy behavior. SLPC does not have the concept of waitboost, so the boost_freq sysfs will show a '0' value for now. There is a patch forthcoming to ensure the interface is not exposed when SLPC is enabled. GuCRC is enabled similarly through a h2g message. We still need to enable RC6 feature bit (GEN6_RC_CTL_RC6_ENABLE) before we send this out. Render/Media power gating still needs to be enabled by host as before. GuC will take care of setting up the hysterisis values for RC6, host does not need to set this up anymore. v2: Address review comments (Michal W) v3: More comments, optimizations (Michal W) v4: Address comments (Michal W, Matt Roper, Matthew Brost) v5: Address checkpatch issues and some more comments Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar(a)intel.com> Vinay Belgaumkar (14): drm/i915/guc/slpc: Initial definitions for SLPC drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled drm/i915/guc/slpc: Adding SLPC communication interfaces drm/i915/guc/slpc: Allocate, initialize and release SLPC drm/i915/guc/slpc: Enable SLPC and add related H2G events drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable drm/i915/guc/slpc: Add methods to set min/max frequency drm/i915/guc/slpc: Add get max/min freq hooks drm/i915/guc/slpc: Add debugfs for SLPC info drm/i915/guc/slpc: Enable ARAT timer interrupt drm/i915/guc/slpc: Cache platform frequency limits drm/i915/guc/slpc: Sysfs hooks for SLPC drm/i915/guc/slpc: Add SLPC selftest drm/i915/guc/rc: Setup and enable GuCRC feature drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 47 +- drivers/gpu/drm/i915/gt/intel_rps.c | 201 ++++++ drivers/gpu/drm/i915/gt/intel_rps.h | 10 + drivers/gpu/drm/i915/gt/selftest_slpc.c | 314 +++++++++ .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 7 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 +++++++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 17 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 + .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 22 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++ drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 601 ++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 42 ++ .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 29 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 - drivers/gpu/drm/i915/gt/uc/intel_uc.c | 25 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 + drivers/gpu/drm/i915/i915_pmu.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/i915_sysfs.c | 83 +-- .../drm/i915/selftests/i915_live_selftests.h | 1 + 24 files changed, 1685 insertions(+), 90 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h -- 2.25.0

2 15

← Newer
1
...
20
21
22
23
24
25
26
...
83
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel July 2021