dri-devel July 2021

dri-devel@lists.freedesktop.org

321 participants
829 discussions

[PATCH] drm/amdkfd: move PTR_ERR under IS_ERR() condition
by Cai Huoqing 27 Jul '21

27 Jul '21

no need to get error code when IS_ERR is false Signed-off-by: Cai Huoqing <caihuoqing(a)baidu.com> --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e48acdd03c1a..710659b3c1f0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -72,16 +72,18 @@ int kfd_chardev_init(void) goto err_register_chrdev; kfd_class = class_create(THIS_MODULE, kfd_dev_name); - err = PTR_ERR(kfd_class); - if (IS_ERR(kfd_class)) + if (IS_ERR(kfd_class)) { + err = PTR_ERR(kfd_class); goto err_class_create; + } kfd_device = device_create(kfd_class, NULL, MKDEV(kfd_char_dev_major, 0), NULL, kfd_dev_name); - err = PTR_ERR(kfd_device); - if (IS_ERR(kfd_device)) + if (IS_ERR(kfd_device)) { + err = PTR_ERR(kfd_device); goto err_device_create; + } return 0; -- 2.25.1

2 1

[PATCH v6] drm/msm/dp: add logs across DP driver for ease of debugging
by maitreye 27 Jul '21

27 Jul '21

From: Maitreyee Rao <maitreye(a)codeaurora.org> Add trace points across the MSM DP driver to help debug interop issues. Changes in v2: - Got rid of redundant log messages. - Added %#x instead of 0x%x wherever required. - Got rid of __func__ calls in debug messages. - Added newline wherever missing. Changes in v3: - Got rid of redundant log messages. - Unstuck colon from printf specifier in various places. Changes in v4: - Changed goto statement and used if else-if Changes in v5: - Changed if else if statement, to not overwrite the ret variable multiple times. Changes in v6: - Changed a wrong log message. Signed-off-by: Maitreyee Rao <maitreye(a)codeaurora.org> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 8 ++++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 5 +++- drivers/gpu/drm/msm/dp/dp_display.c | 13 ++++++++++ drivers/gpu/drm/msm/dp/dp_link.c | 50 +++++++++++++------------------------ drivers/gpu/drm/msm/dp/dp_power.c | 3 +++ 5 files changed, 44 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 32f3575..958d3fa3 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -372,6 +372,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + DRM_DEBUG_DP("enable=%d\n", enable); if (enable) { /* * To make sure link reg writes happens before other operation, @@ -580,6 +581,7 @@ void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, config = (en ? config | intr_mask : config & ~intr_mask); + DRM_DEBUG_DP("intr_mask=%#x config=%#x\n", intr_mask, config); dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, config & DP_DP_HPD_INT_MASK); } @@ -610,6 +612,7 @@ u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog) u32 status; status = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + DRM_DEBUG_DP("aux status: %#x\n", status); status >>= DP_DP_HPD_STATE_STATUS_BITS_SHIFT; status &= DP_DP_HPD_STATE_STATUS_BITS_MASK; @@ -685,6 +688,7 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, /* Make sure to clear the current pattern before starting a new one */ dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); + DRM_DEBUG_DP("pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: dp_write_link(catalog, REG_DP_STATE_CTRL, @@ -745,7 +749,7 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: - DRM_DEBUG_DP("No valid test pattern requested:0x%x\n", pattern); + DRM_DEBUG_DP("No valid test pattern requested: %#x\n", pattern); break; } } @@ -928,7 +932,7 @@ void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog) select = dp_catalog->audio_data; acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14); - DRM_DEBUG_DP("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl); + DRM_DEBUG_DP("select: %#x, acr_ctrl: %#x\n", select, acr_ctrl); dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 2a8955c..72de71a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -122,7 +122,7 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) pr_warn("PUSH_IDLE pattern timedout\n"); - pr_debug("mainlink off done\n"); + DRM_DEBUG_DP("mainlink off done\n"); } static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) @@ -1013,6 +1013,8 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) u32 voltage_swing_level = link->phy_params.v_level; u32 pre_emphasis_level = link->phy_params.p_level; + DRM_DEBUG_DP("voltage level: %d emphasis level: %d\n", voltage_swing_level, + pre_emphasis_level); ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, voltage_swing_level, pre_emphasis_level); @@ -1384,6 +1386,7 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset) if (reset) dp_catalog_ctrl_reset(ctrl->catalog); + DRM_DEBUG_DP("flip=%d\n", flip); dp_catalog_ctrl_phy_reset(ctrl->catalog); phy_init(phy); dp_catalog_ctrl_enable_irq(ctrl->catalog, true); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cf9c645..bbd9541 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -275,6 +275,8 @@ static bool dp_display_is_ds_bridge(struct dp_panel *panel) static bool dp_display_is_sink_count_zero(struct dp_display_private *dp) { + DRM_DEBUG_DP("present=%#x sink_count=%d\n", dp->panel->dpcd[DP_DOWNSTREAMPORT_PRESENT], + dp->link->sink_count); return dp_display_is_ds_bridge(dp->panel) && (dp->link->sink_count == 0); } @@ -320,6 +322,7 @@ static int dp_display_send_hpd_notification(struct dp_display_private *dp, dp->dp_display.is_connected = hpd; + DRM_DEBUG_DP("hpd=%d\n", hpd); dp_display_send_hpd_event(&dp->dp_display); return 0; @@ -369,6 +372,7 @@ static void dp_display_host_init(struct dp_display_private *dp, int reset) { bool flip = false; + DRM_DEBUG_DP("core_initialized=%d\n", dp->core_initialized); if (dp->core_initialized) { DRM_DEBUG_DP("DP core already initialized\n"); return; @@ -483,8 +487,10 @@ static int dp_display_handle_irq_hpd(struct dp_display_private *dp) { u32 sink_request = dp->link->sink_request; + DRM_DEBUG_DP("%d\n", sink_request); if (dp->hpd_state == ST_DISCONNECTED) { if (sink_request & DP_LINK_STATUS_UPDATED) { + DRM_DEBUG_DP("Disconnected sink_request: %d\n", sink_request); DRM_ERROR("Disconnected, no DP_LINK_STATUS_UPDATED\n"); return -EINVAL; } @@ -523,6 +529,7 @@ static int dp_display_usbpd_attention_cb(struct device *dev) rc = dp_link_process_request(dp->link); if (!rc) { sink_request = dp->link->sink_request; + DRM_DEBUG_DP("hpd_state=%d sink_request=%d\n", dp->hpd_state, sink_request); if (sink_request & DS_PORT_STATUS_CHANGED) rc = dp_display_handle_port_ststus_changed(dp); else @@ -545,6 +552,7 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) mutex_lock(&dp->event_mutex); state = dp->hpd_state; + DRM_DEBUG_DP("hpd_state=%d\n", state); if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) { mutex_unlock(&dp->event_mutex); return 0; @@ -680,6 +688,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) /* start sentinel checking in case of missing uevent */ dp_add_event(dp, EV_DISCONNECT_PENDING_TIMEOUT, 0, DP_TIMEOUT_5_SECOND); + DRM_DEBUG_DP("hpd_state=%d\n", state); /* signal the disconnect event early to ensure proper teardown */ dp_display_handle_plugged_change(g_dp_display, false); @@ -738,6 +747,7 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) if (ret == -ECONNRESET) { /* cable unplugged */ dp->core_initialized = false; } + DRM_DEBUG_DP("hpd_state=%d\n", state); mutex_unlock(&dp->event_mutex); @@ -882,6 +892,7 @@ static int dp_display_enable(struct dp_display_private *dp, u32 data) dp_display = g_dp_display; + DRM_DEBUG_DP("sink_count=%d\n", dp->link->sink_count); if (dp_display->power_on) { DRM_DEBUG_DP("Link already setup, return\n"); return 0; @@ -943,6 +954,7 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) dp_display->power_on = false; + DRM_DEBUG_DP("sink count: %d\n", dp->link->sink_count); return 0; } @@ -1190,6 +1202,7 @@ static irqreturn_t dp_display_irq_handler(int irq, void *dev_id) hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); + DRM_DEBUG_DP("hpd isr status=%#x\n", hpd_isr_status); if (hpd_isr_status & 0x0F) { /* hpd related interrupts */ if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK || diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index be986da..ac53c06 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -1036,43 +1036,29 @@ int dp_link_process_request(struct dp_link *dp_link) if (link->request.test_requested == DP_TEST_LINK_EDID_READ) { dp_link->sink_request |= DP_TEST_LINK_EDID_READ; - return ret; - } - - ret = dp_link_process_ds_port_status_change(link); - if (!ret) { + } else if (!dp_link_process_ds_port_status_change(link)) { dp_link->sink_request |= DS_PORT_STATUS_CHANGED; - return ret; - } - - ret = dp_link_process_link_training_request(link); - if (!ret) { + } else if (!dp_link_process_link_training_request(link)) { dp_link->sink_request |= DP_TEST_LINK_TRAINING; - return ret; - } - - ret = dp_link_process_phy_test_pattern_request(link); - if (!ret) { + } else if (!dp_link_process_phy_test_pattern_request(link)) { dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN; - return ret; - } - - ret = dp_link_process_link_status_update(link); - if (!ret) { - dp_link->sink_request |= DP_LINK_STATUS_UPDATED; - return ret; - } - - if (dp_link_is_video_pattern_requested(link)) { - ret = 0; - dp_link->sink_request |= DP_TEST_LINK_VIDEO_PATTERN; - } - - if (dp_link_is_audio_pattern_requested(link)) { - dp_link->sink_request |= DP_TEST_LINK_AUDIO_PATTERN; - return -EINVAL; + } else { + ret = dp_link_process_link_status_update(link); + if (!ret) { + dp_link->sink_request |= DP_LINK_STATUS_UPDATED; + } else { + if (dp_link_is_video_pattern_requested(link)) { + ret = 0; + dp_link->sink_request |= DP_TEST_LINK_VIDEO_PATTERN; + } + if (dp_link_is_audio_pattern_requested(link)) { + dp_link->sink_request |= DP_TEST_LINK_AUDIO_PATTERN; + ret = -EINVAL; + } + } } + DRM_DEBUG_DP("sink request=%#x", dp_link->sink_request); return ret; } diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index 3961ba4..b48b45e 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -208,6 +208,9 @@ static int dp_power_clk_set_rate(struct dp_power_private *power, int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type) { + DRM_DEBUG_DP("core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", + dp_power->core_clks_on, dp_power->link_clks_on, dp_power->stream_clks_on); + if (pm_type == DP_CORE_PM) return dp_power->core_clks_on; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

2 1

[PATCH] drm/msm/dp: Initialize dp->aux->drm_dev before registration
by Sean Paul 27 Jul '21

27 Jul '21

From: Sean Paul <seanpaul(a)chromium.org> Avoids the following WARN: [ 3.009556] ------------[ cut here ]------------ [ 3.014306] WARNING: CPU: 7 PID: 109 at drivers/gpu/drm/drm_dp_helper.c:1796 drm_dp_aux_register+0xa4/0xac [ 3.024209] Modules linked in: [ 3.027351] CPU: 7 PID: 109 Comm: kworker/7:8 Not tainted 5.10.47 #69 [ 3.033958] Hardware name: Google Lazor (rev1 - 2) (DT) [ 3.039323] Workqueue: events deferred_probe_work_func [ 3.044596] pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--) [ 3.050761] pc : drm_dp_aux_register+0xa4/0xac [ 3.055329] lr : dp_aux_register+0x40/0x88 [ 3.059538] sp : ffffffc010ad3920 [ 3.062948] x29: ffffffc010ad3920 x28: ffffffa64196ac70 [ 3.067239] mmc1: Command Queue Engine enabled [ 3.068406] x27: ffffffa64196ac68 x26: 0000000000000001 [ 3.068407] x25: 0000000000000002 x24: 0000000000000060 [ 3.068409] x23: ffffffa642ab3400 x22: ffffffe126c10e5b [ 3.068410] x21: ffffffa641dc3188 x20: ffffffa641963c10 [ 3.068412] x19: ffffffa642aba910 x18: 00000000ffff0a00 [ 3.068414] x17: 000000476f8e002a x16: 00000000000000b8 [ 3.073008] mmc1: new HS400 Enhanced strobe MMC card at address 0001 [ 3.078448] x15: ffffffffffffffff x14: ffffffffffffffff [ 3.078450] x13: 0000000000000030 x12: 0000000000000030 [ 3.078452] x11: 0101010101010101 x10: ffffffe12647a914 [ 3.078453] x9 : ffffffe12647a8cc x8 : 0000000000000000 [ 3.084452] mmcblk1: mmc1:0001 DA4032 29.1 GiB [ 3.089372] [ 3.089372] x7 : 6c6064717372fefe x6 : ffffffa642b11494 [ 3.089374] x5 : 0000000000000000 x4 : 6d006c657869ffff [ 3.089375] x3 : 000000006c657869 x2 : 000000000000000c [ 3.089376] x1 : ffffffe126c3ae3c x0 : ffffffa642aba910 [ 3.089381] Call trace: [ 3.094931] mmcblk1boot0: mmc1:0001 DA4032 partition 1 4.00 MiB [ 3.100291] drm_dp_aux_register+0xa4/0xac [ 3.100292] dp_aux_register+0x40/0x88 [ 3.100294] dp_display_bind+0x64/0xcc [ 3.100295] component_bind_all+0xdc/0x210 [ 3.100298] msm_drm_bind+0x1e8/0x5d4 [ 3.100301] try_to_bring_up_master+0x168/0x1b0 [ 3.105861] mmcblk1boot1: mmc1:0001 DA4032 partition 2 4.00 MiB [ 3.112282] __component_add+0xa0/0x158 [ 3.112283] component_add+0x1c/0x28 [ 3.112284] dp_display_probe+0x33c/0x380 [ 3.112286] platform_drv_probe+0x9c/0xbc [ 3.112287] really_probe+0x140/0x35c [ 3.112289] driver_probe_device+0x84/0xc0 [ 3.112292] __device_attach_driver+0x94/0xb0 [ 3.117967] mmcblk1rpmb: mmc1:0001 DA4032 partition 3 16.0 MiB, chardev (239:0) [ 3.123201] bus_for_each_drv+0x8c/0xd8 [ 3.123202] __device_attach+0xc4/0x150 [ 3.123204] device_initial_probe+0x1c/0x28 [ 3.123205] bus_probe_device+0x3c/0x9c [ 3.123206] deferred_probe_work_func+0x90/0xcc [ 3.123211] process_one_work+0x218/0x3ec [ 3.131976] mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 [ 3.134123] worker_thread+0x288/0x3e8 [ 3.134124] kthread+0x148/0x1b0 [ 3.134127] ret_from_fork+0x10/0x30 [ 3.134128] ---[ end trace cfb9fce3f70f824d ]--- Signed-off-by: Sean Paul <seanpaul(a)chromium.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 051c1be1de7e..987f9e330138 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -219,6 +219,7 @@ static int dp_display_bind(struct device *dev, struct device *master, goto end; } + dp->aux->drm_dev = drm; rc = dp_aux_register(dp->aux); if (rc) { DRM_ERROR("DRM DP AUX register failed\n"); -- Sean Paul, Software Engineer, Google / Chromium OS

3 2

Re: [PATCH v3 1/3] drm/loongson: Add DRM Driver for Loongson 7A1000 bridge chip
by Daniel Vetter 27 Jul '21

27 Jul '21

On Fri, Jul 23, 2021 at 11:12:49AM +0800, lichenyang wrote: > From: Chenyang Li <lichenyang(a)loongson.cn> > > This patch adds an initial DRM driver for the Loongson LS7A1000 > bridge chip(LS7A). The LS7A bridge chip contains two display > controllers, support dual display output. The maximum support for > each channel display is to 1920x1080@60Hz. > At present, DC device detection and DRM driver registration are > completed, the crtc/plane/encoder/connector objects has been > implemented. > On Loongson 3A4000 CPU and 7A1000 system, we have achieved the use > of dual screen, and support dual screen clone mode and expansion > mode. > > v9: > - Optimize the error handling process. > - Remove the useless flags parameter. > - Fix some incorrect use of variables and constructs. > > v8: > - Update the atomic_update function interface. > > v7: > - The pixel clock is limited to less than 173000. > > v6: > - Remove spin_lock in mmio reg read and write. > - TO_UNCAC is replac with ioremap. > - Fix error arguments in crtc_atomic_enable/disable/mode_valid. > > v5: > - Change the name of the chip to LS7A. > - Change magic value in crtc to macros. > - Correct mistakes words. > - Change the register operation function prefix to ls7a. > > v4: > - Move the mode_valid function to the crtc. > > v3: > - Move the mode_valid function to the connector and optimize it. > - Fix num_crtc calculation method. > > v2: > - Complete the case of 32-bit color in CRTC. > > Signed-off-by: Chenyang Li <lichenyang(a)loongson.cn> Somehow this simple driver is at v9 and still not landed. Do you have someone from the drm maintainers/committers who's guiding you through all this? I'm not seeing you Cc: a specific person, without that there's good chances your contribution gets lost. I'm swamped myself, which is why I've ignored this and hope you'd fine someone else and stick to them. A few comments below. > --- > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/loongson/Kconfig | 14 + > drivers/gpu/drm/loongson/Makefile | 14 + > drivers/gpu/drm/loongson/loongson_connector.c | 46 +++ > drivers/gpu/drm/loongson/loongson_crtc.c | 249 ++++++++++++++++ > drivers/gpu/drm/loongson/loongson_device.c | 35 +++ > drivers/gpu/drm/loongson/loongson_drv.c | 278 ++++++++++++++++++ > drivers/gpu/drm/loongson/loongson_drv.h | 140 +++++++++ > drivers/gpu/drm/loongson/loongson_encoder.c | 37 +++ > drivers/gpu/drm/loongson/loongson_plane.c | 97 ++++++ > 11 files changed, 913 insertions(+) > create mode 100644 drivers/gpu/drm/loongson/Kconfig > create mode 100644 drivers/gpu/drm/loongson/Makefile > create mode 100644 drivers/gpu/drm/loongson/loongson_connector.c > create mode 100644 drivers/gpu/drm/loongson/loongson_crtc.c > create mode 100644 drivers/gpu/drm/loongson/loongson_device.c > create mode 100644 drivers/gpu/drm/loongson/loongson_drv.c > create mode 100644 drivers/gpu/drm/loongson/loongson_drv.h > create mode 100644 drivers/gpu/drm/loongson/loongson_encoder.c > create mode 100644 drivers/gpu/drm/loongson/loongson_plane.c > > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig > index 7ff89690a976..08562d9be6e3 100644 > --- a/drivers/gpu/drm/Kconfig > +++ b/drivers/gpu/drm/Kconfig > @@ -365,6 +365,8 @@ source "drivers/gpu/drm/xen/Kconfig" > > source "drivers/gpu/drm/vboxvideo/Kconfig" > > +source "drivers/gpu/drm/loongson/Kconfig" > + > source "drivers/gpu/drm/lima/Kconfig" > > source "drivers/gpu/drm/panfrost/Kconfig" > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index a118692a6df7..29c05b8cf2ad 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -119,6 +119,7 @@ obj-$(CONFIG_DRM_PL111) += pl111/ > obj-$(CONFIG_DRM_TVE200) += tve200/ > obj-$(CONFIG_DRM_XEN) += xen/ > obj-$(CONFIG_DRM_VBOXVIDEO) += vboxvideo/ > +obj-$(CONFIG_DRM_LOONGSON) += loongson/ > obj-$(CONFIG_DRM_LIMA) += lima/ > obj-$(CONFIG_DRM_PANFROST) += panfrost/ > obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ > diff --git a/drivers/gpu/drm/loongson/Kconfig b/drivers/gpu/drm/loongson/Kconfig > new file mode 100644 > index 000000000000..3cf42a4cca08 > --- /dev/null > +++ b/drivers/gpu/drm/loongson/Kconfig > @@ -0,0 +1,14 @@ > +# SPDX-License-Identifier: GPL-2.0-only > + > +config DRM_LOONGSON > + tristate "DRM support for LS7A bridge chipset" > + depends on DRM && PCI > + depends on CPU_LOONGSON64 > + select DRM_KMS_HELPER > + select DRM_VRAM_HELPER > + select DRM_TTM > + select DRM_TTM_HELPER > + default n > + help > + Support the display controllers found on the Loongson LS7A > + bridge. > diff --git a/drivers/gpu/drm/loongson/Makefile b/drivers/gpu/drm/loongson/Makefile > new file mode 100644 > index 000000000000..22d063953b78 > --- /dev/null > +++ b/drivers/gpu/drm/loongson/Makefile > @@ -0,0 +1,14 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Makefile for loongson drm drivers. > +# This driver provides support for the > +# Direct Rendering Infrastructure (DRI) > + > +ccflags-y := -Iinclude/drm > +loongson-y := loongson_drv.o \ > + loongson_crtc.o \ > + loongson_plane.o \ > + loongson_device.o \ > + loongson_connector.o \ > + loongson_encoder.o > +obj-$(CONFIG_DRM_LOONGSON) += loongson.o > diff --git a/drivers/gpu/drm/loongson/loongson_connector.c b/drivers/gpu/drm/loongson/loongson_connector.c > new file mode 100644 > index 000000000000..a571f9ef4266 > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_connector.c > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "loongson_drv.h" > + > +static int loongson_get_modes(struct drm_connector *connector) > +{ > + int count; > + > + count = drm_add_modes_noedid(connector, 1920, 1080); > + drm_set_preferred_mode(connector, 1024, 768); > + > + return count; > +} > + > +static const struct drm_connector_helper_funcs loongson_connector_helper = { > + .get_modes = loongson_get_modes, > +}; > + > +static const struct drm_connector_funcs loongson_connector_funcs = { > + .fill_modes = drm_helper_probe_single_connector_modes, > + .destroy = drm_connector_cleanup, > + .reset = drm_atomic_helper_connector_reset, > + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, > +}; > + > +int loongson_connector_init(struct loongson_device *ldev, int index) > +{ > + struct drm_connector *connector; > + struct loongson_connector *lconnector; > + > + lconnector = kzalloc(sizeof(struct loongson_connector), GFP_KERNEL); > + if (!lconnector) > + return -ENOMEM; > + > + lconnector->ldev = ldev; > + lconnector->id = index; > + > + ldev->mode_info[index].connector = lconnector; > + connector = &lconnector->base; > + drm_connector_init(ldev->dev, connector, &loongson_connector_funcs, Hm we don't have a drmm_connector_alloc helper like for the others, would be really nice to fix this. > + DRM_MODE_CONNECTOR_Unknown); > + drm_connector_helper_add(connector, &loongson_connector_helper); > + > + return 0; > +} > diff --git a/drivers/gpu/drm/loongson/loongson_crtc.c b/drivers/gpu/drm/loongson/loongson_crtc.c > new file mode 100644 > index 000000000000..163e24d85b02 > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_crtc.c > @@ -0,0 +1,249 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "loongson_drv.h" > + > +static void try_each_loopc(u32 clk, u32 pstdiv, u32 frefc, > + struct pix_pll *pll_config) > +{ > + u32 loopc; > + u32 clk_out; > + u32 precision; > + u32 min = 1000; > + u32 base_clk = 100000L; > + > + for (loopc = LOOPC_MIN; loopc < LOOPC_MAX; loopc++) { > + if ((loopc < FRE_REF_MIN * frefc) || > + (loopc > FRE_REF_MAX * frefc)) > + continue; > + > + clk_out = base_clk * loopc / frefc; > + precision = (clk > clk_out) ? (clk - clk_out) : (clk_out - clk); > + if (precision < min) { > + pll_config->l2_div = pstdiv; > + pll_config->l1_loopc = loopc; > + pll_config->l1_frefc = frefc; > + } > + } > +} > + > +static void cal_freq(u32 pixclock, struct pix_pll *pll_config) > +{ > + u32 pstdiv; > + u32 frefc; > + u32 clk; > + > + for (pstdiv = 1; pstdiv < PST_DIV_MAX; pstdiv++) { > + clk = pixclock * pstdiv; > + for (frefc = DIV_REF_MIN; frefc <= DIV_REF_MAX; frefc++) > + try_each_loopc(clk, pstdiv, frefc, pll_config); > + } > +} > + > +static void config_pll(struct loongson_device *ldev, unsigned long pll_base, > + struct pix_pll *pll_cfg) > +{ > + u32 val; > + u32 count = 0; > + > + /* clear sel_pll_out0 */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val &= ~(1UL << 8); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + > + /* set pll_pd */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val |= (1UL << 13); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + > + /* clear set_pll_param */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val &= ~(1UL << 11); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + > + /* clear old value & config new value */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val &= ~(0x7fUL << 0); > + val |= (pll_cfg->l1_frefc << 0); /* refc */ > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + val = ls7a_io_rreg(ldev, pll_base + 0x0); > + val &= ~(0x7fUL << 0); > + val |= (pll_cfg->l2_div << 0); /* div */ > + val &= ~(0x1ffUL << 21); > + val |= (pll_cfg->l1_loopc << 21); /* loopc */ > + ls7a_io_wreg(ldev, pll_base + 0x0, val); > + > + /* set set_pll_param */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val |= (1UL << 11); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + /* clear pll_pd */ > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val &= ~(1UL << 13); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > + > + while (!(ls7a_io_rreg(ldev, pll_base + 0x4) & 0x80)) { > + cpu_relax(); > + count++; > + if (count >= 1000) { > + DRM_ERROR("loongson-7A PLL lock failed\n"); > + break; > + } > + } > + > + val = ls7a_io_rreg(ldev, pll_base + 0x4); > + val |= (1UL << 8); > + ls7a_io_wreg(ldev, pll_base + 0x4, val); > +} > + > +static void loongson_crtc_mode_set_nofb(struct drm_crtc *crtc) > +{ > + struct drm_device *dev = crtc->dev; > + struct loongson_device *ldev = dev->dev_private; > + struct loongson_crtc *lcrtc = to_loongson_crtc(crtc); > + struct drm_display_mode *mode = &crtc->state->adjusted_mode; > + const struct drm_format_info *format; > + struct pix_pll pll_cfg; > + u32 hr, hss, hse, hfl; > + u32 vr, vss, vse, vfl; > + u32 pix_freq; > + u32 reg_offset; > + > + hr = mode->hdisplay; > + hss = mode->hsync_start; > + hse = mode->hsync_end; > + hfl = mode->htotal; > + > + vr = mode->vdisplay; > + vss = mode->vsync_start; > + vse = mode->vsync_end; > + vfl = mode->vtotal; > + > + pix_freq = mode->clock; > + reg_offset = lcrtc->reg_offset; > + format = crtc->primary->state->fb->format; > + > + ls7a_mm_wreg(ldev, FB_DITCFG_REG + reg_offset, 0); > + ls7a_mm_wreg(ldev, FB_DITTAB_LO_REG + reg_offset, 0); > + ls7a_mm_wreg(ldev, FB_DITTAB_HI_REG + reg_offset, 0); > + ls7a_mm_wreg(ldev, FB_PANCFG_REG + reg_offset, FB_PANCFG_DEF); > + ls7a_mm_wreg(ldev, FB_PANTIM_REG + reg_offset, 0); > + > + ls7a_mm_wreg(ldev, FB_HDISPLAY_REG + reg_offset, (hfl << 16) | hr); > + ls7a_mm_wreg(ldev, FB_HSYNC_REG + reg_offset, > + FB_HSYNC_PULSE | (hse << 16) | hss); > + > + ls7a_mm_wreg(ldev, FB_VDISPLAY_REG + reg_offset, (vfl << 16) | vr); > + ls7a_mm_wreg(ldev, FB_VSYNC_REG + reg_offset, > + FB_VSYNC_PULSE | (vse << 16) | vss); > + > + switch (format->format) { > + case DRM_FORMAT_RGB565: > + lcrtc->cfg_reg |= 0x3; > + break; > + case DRM_FORMAT_RGB888: > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + default: > + lcrtc->cfg_reg |= 0x4; > + break; > + } > + ls7a_mm_wreg(ldev, FB_CFG_REG + reg_offset, lcrtc->cfg_reg); > + > + cal_freq(pix_freq, &pll_cfg); > + config_pll(ldev, LS7A_PIX_PLL + reg_offset, &pll_cfg); > +} > + > +static void loongson_crtc_atomic_enable(struct drm_crtc *crtc, > + struct drm_atomic_state *old_state) > +{ > + struct drm_device *dev = crtc->dev; > + struct loongson_device *ldev = dev->dev_private; > + struct loongson_crtc *lcrtc = to_loongson_crtc(crtc); > + u32 reg_offset = lcrtc->reg_offset; > + > + lcrtc->cfg_reg |= CFG_ENABLE; > + ls7a_mm_wreg(ldev, FB_CFG_REG + reg_offset, lcrtc->cfg_reg); > +} > + > +static void loongson_crtc_atomic_disable(struct drm_crtc *crtc, > + struct drm_atomic_state *old_state) > +{ > + struct drm_device *dev = crtc->dev; > + struct loongson_device *ldev = dev->dev_private; > + struct loongson_crtc *lcrtc = to_loongson_crtc(crtc); > + u32 reg_offset = lcrtc->reg_offset; > + > + lcrtc->cfg_reg &= ~CFG_ENABLE; > + ls7a_mm_wreg(ldev, FB_CFG_REG + reg_offset, lcrtc->cfg_reg); > +} > + > +static enum drm_mode_status loongson_mode_valid(struct drm_crtc *crtc, > + const struct drm_display_mode *mode) > +{ > + if (mode->hdisplay > 1920) > + return MODE_BAD; > + if (mode->vdisplay > 1080) > + return MODE_BAD; > + if (mode->hdisplay % 64) > + return MODE_BAD; > + if (mode->clock >= 173000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static const struct drm_crtc_helper_funcs loongson_crtc_helper_funcs = { > + .mode_valid = loongson_mode_valid, > + .atomic_enable = loongson_crtc_atomic_enable, > + .atomic_disable = loongson_crtc_atomic_disable, > + .mode_set_nofb = loongson_crtc_mode_set_nofb, > +}; > + > +static const struct drm_crtc_funcs loongson_crtc_funcs = { > + .set_config = drm_atomic_helper_set_config, > + .page_flip = drm_atomic_helper_page_flip, > + .reset = drm_atomic_helper_crtc_reset, > + .destroy = drm_crtc_cleanup, > + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, > +}; > + > +int loongson_crtc_init(struct loongson_device *ldev, int index) > +{ > + struct loongson_crtc *lcrtc; > + int ret; > + > + lcrtc = kzalloc(sizeof(struct loongson_crtc), GFP_KERNEL); > + if (!lcrtc) > + return -ENOMEM; > + > + lcrtc->ldev = ldev; > + lcrtc->reg_offset = index * REG_OFFSET; > + lcrtc->cfg_reg = CFG_RESET; > + lcrtc->crtc_id = index; > + > + ret = loongson_plane_init(lcrtc); > + if (ret) > + goto free_lcrtc; > + > + ret = drm_crtc_init_with_planes(ldev->dev, &lcrtc->base, &lcrtc->plane, > + NULL, &loongson_crtc_funcs, NULL); Please use the drmm_crtc version here and don't kzalloc yourself. That simplifies the cleanup (since atm you're just leaking this memory). Also loongson hw looks a like like something which should use the simple kms helpers since you're embedding the single plane into your crtc struct: https://dri.freedesktop.org/docs/drm/gpu/drm-kms-helpers.html#simple-kms-he… Also at that point your driver is probabyl small enough that single source file is the right thing, and you should move it into drivers/gpu/drm/tiny. It would be the first simple/tiny drm driver with 2 outputs. Rule of thumb we have is that if it's below 1kloc, a single file and putting it into drm/tiny is best. Cheers, Daniel > + if (ret) { > + DRM_ERROR("failed to init crtc %d\n", index); > + goto cleanup_plane; > + } > + > + drm_crtc_helper_add(&lcrtc->base, &loongson_crtc_helper_funcs); > + > + ldev->mode_info[index].crtc = lcrtc; > + > + return 0; > + > +cleanup_plane: > + drm_plane_cleanup(&lcrtc->plane); > +free_lcrtc: > + kfree(lcrtc); > + > + return ret; > +} > + > diff --git a/drivers/gpu/drm/loongson/loongson_device.c b/drivers/gpu/drm/loongson/loongson_device.c > new file mode 100644 > index 000000000000..a79d64fc1a06 > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_device.c > @@ -0,0 +1,35 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "loongson_drv.h" > + > +u32 loongson_gpu_offset(struct drm_plane_state *state, > + struct loongson_device *ldev) > +{ > + struct drm_gem_vram_object *gbo; > + u32 gpu_addr; > + > + gbo = drm_gem_vram_of_gem(state->fb->obj[0]); > + gpu_addr = ldev->vram_start + drm_gem_vram_offset(gbo); > + > + return gpu_addr; > +} > + > +u32 ls7a_io_rreg(struct loongson_device *ldev, u32 offset) > +{ > + return readl(ldev->io + offset); > +} > + > +void ls7a_io_wreg(struct loongson_device *ldev, u32 offset, u32 val) > +{ > + writel(val, ldev->io + offset); > +} > + > +u32 ls7a_mm_rreg(struct loongson_device *ldev, u32 offset) > +{ > + return readl(ldev->mmio + offset); > +} > + > +void ls7a_mm_wreg(struct loongson_device *ldev, u32 offset, u32 val) > +{ > + writel(val, ldev->mmio + offset); > +} > diff --git a/drivers/gpu/drm/loongson/loongson_drv.c b/drivers/gpu/drm/loongson/loongson_drv.c > new file mode 100644 > index 000000000000..c84494f7aabb > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_drv.c > @@ -0,0 +1,278 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Loongson LS7A1000 bridge chipset drm driver > + */ > + > +#include <linux/console.h> > +#include <linux/pci.h> > +#include <linux/module.h> > +#include <linux/kernel.h> > +#include "loongson_drv.h" > + > +/* Interface history: > + * 0.1 - original. > + */ > +#define DRIVER_MAJOR 0 > +#define DRIVER_MINOR 1 > + > +static const struct drm_mode_config_funcs loongson_mode_funcs = { > + .fb_create = drm_gem_fb_create, > + .atomic_check = drm_atomic_helper_check, > + .atomic_commit = drm_atomic_helper_commit, > + .output_poll_changed = drm_fb_helper_output_poll_changed, > + .mode_valid = drm_vram_helper_mode_valid > +}; > + > +static int loongson_device_init(struct drm_device *dev) > +{ > + struct loongson_device *ldev = dev->dev_private; > + struct pci_dev *pdev = to_pci_dev(dev->dev); > + struct pci_dev *gpu_pdev; > + resource_size_t aper_base; > + resource_size_t aper_size; > + resource_size_t mmio_base; > + resource_size_t mmio_size; > + int ret; > + > + /* GPU MEM */ > + /* We need get 7A-gpu pci device information for ldev->gpu_pdev */ > + /* dev->pdev save 7A-dc pci device information */ > + gpu_pdev = pci_get_device(PCI_VENDOR_ID_LOONGSON, > + PCI_DEVICE_ID_LOONGSON_GPU, NULL); > + ldev->gpu_pdev = gpu_pdev; > + ret = pci_enable_device(ldev->gpu_pdev); > + if (ret) > + return ret; > + pci_set_drvdata(ldev->gpu_pdev, dev); > + > + aper_base = pci_resource_start(gpu_pdev, 2); > + aper_size = pci_resource_len(gpu_pdev, 2); > + ldev->vram_start = aper_base; > + ldev->vram_size = aper_size; > + > + if (!devm_request_mem_region(ldev->dev->dev, ldev->vram_start, > + ldev->vram_size, "loongson_vram")) { > + DRM_ERROR("Can't reserve VRAM\n"); > + return -ENXIO; > + } > + > + /* DC MEM */ > + mmio_base = pci_resource_start(pdev, 0); > + mmio_size = pci_resource_len(pdev, 0); > + ldev->mmio = devm_ioremap(dev->dev, mmio_base, mmio_size); > + if (!ldev->mmio) { > + drm_err(dev, "Cannot map mmio region\n"); > + return -ENOMEM; > + } > + > + if (!devm_request_mem_region(ldev->dev->dev, mmio_base, > + mmio_size, "loongson_mmio")) { > + DRM_ERROR("Can't reserve mmio registers\n"); > + return -ENOMEM; > + } > + > + /* DC IO */ > + ldev->io = devm_ioremap(dev->dev, LS7A_CHIPCFG_REG_BASE, 0xf); > + if (!ldev->io) > + return -ENOMEM; > + > + DRM_INFO("DC mmio base 0x%llx size 0x%llx io 0x%llx\n", > + mmio_base, mmio_size, *(u64 *)ldev->io); > + DRM_INFO("GPU vram start = 0x%x size = 0x%x\n", > + ldev->vram_start, ldev->vram_size); > + > + return 0; > +} > + > +int loongson_modeset_init(struct loongson_device *ldev) > +{ > + struct drm_encoder *encoder; > + struct drm_connector *connector; > + int i; > + int ret; > + > + ldev->dev->mode_config.allow_fb_modifiers = true; > + > + for (i = 0; i < 2; i++) { > + ret = loongson_crtc_init(ldev, i); > + if (ret) { > + DRM_WARN("loongson crtc%d init failed\n", i); > + continue; > + } > + > + ret = loongson_encoder_init(ldev, i); > + if (ret) { > + DRM_ERROR("loongson_encoder_init failed\n"); > + return ret; > + } > + > + ret = loongson_connector_init(ldev, i); > + if (ret) { > + DRM_ERROR("loongson_connector_init failed\n"); > + return ret; > + } > + > + encoder = &ldev->mode_info[i].encoder->base; > + connector = &ldev->mode_info[i].connector->base; > + drm_connector_attach_encoder(connector, encoder); > + ldev->num_crtc++; > + } > + > + return 0; > +} > + > +static int loongson_drm_load(struct drm_device *dev) > +{ > + struct loongson_device *ldev; > + int ret; > + > + ldev = devm_kzalloc(dev->dev, sizeof(*ldev), GFP_KERNEL); Please don't use devm_kzalloc here, but instead embedde the struct drm_device into your struct looongson_device. -Daniel > + if (!ldev) > + return -ENOMEM; > + > + dev->dev_private = ldev; > + ldev->dev = dev; > + > + ret = loongson_device_init(dev); > + if (ret) > + goto err; > + > + ret = drmm_vram_helper_init(dev, ldev->vram_start, ldev->vram_size); > + if (ret) { > + drm_err(dev, "Error initializing vram %d\n", ret); > + goto err; > + } > + > + drm_mode_config_init(dev); > + dev->mode_config.funcs = (void *)&loongson_mode_funcs; > + dev->mode_config.min_width = 1; > + dev->mode_config.min_height = 1; > + dev->mode_config.max_width = 4096; > + dev->mode_config.max_height = 4096; > + dev->mode_config.preferred_depth = 32; > + dev->mode_config.prefer_shadow = 1; > + dev->mode_config.fb_base = ldev->vram_start; > + > + ret = loongson_modeset_init(ldev); > + if (ret) { > + drm_err(dev, "Fatal error during modeset init: %d\n", ret); > + goto err; > + } > + > + drm_kms_helper_poll_init(dev); > + drm_mode_config_reset(dev); > + > + return 0; > + > +err: > + kfree(ldev); > + drm_err(dev, "failed to initialize drm driver: %d\n", ret); > + return ret; > +} > + > +static void loongson_drm_unload(struct drm_device *dev) > +{ > + drm_vram_helper_release_mm(dev); > + drm_mode_config_cleanup(dev); > + dev->dev_private = NULL; > + dev_set_drvdata(dev->dev, NULL); > +} > + > +DEFINE_DRM_GEM_FOPS(fops); > + > +static struct drm_driver loongson_drm_driver = { > + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, > + .fops = &fops, > + DRM_GEM_VRAM_DRIVER, > + > + .name = DRIVER_NAME, > + .desc = DRIVER_DESC, > + .date = DRIVER_DATE, > + .major = DRIVER_MAJOR, > + .minor = DRIVER_MINOR, > +}; > + > +static int loongson_pci_probe(struct pci_dev *pdev, > + const struct pci_device_id *ent) > +{ > + int ret; > + struct drm_device *dev; > + > + DRM_INFO("Start loongson drm probe\n"); > + dev = drm_dev_alloc(&loongson_drm_driver, &pdev->dev); > + if (IS_ERR(dev)) { > + DRM_ERROR("failed to allocate drm_device\n"); > + return PTR_ERR(dev); > + } > + > + pci_set_drvdata(pdev, dev); > + > + ret = pci_enable_device(pdev); > + if (ret) { > + drm_err(dev, "failed to enable pci device: %d\n", ret); > + goto err_free; > + } > + > + ret = loongson_drm_load(dev); > + if (ret) { > + drm_err(dev, "failed to load loongson: %d\n", ret); > + goto err_pdev; > + } > + > + ret = drm_dev_register(dev, 0); > + if (ret) { > + drm_err(dev, "failed to register drv for userspace access: %d\n", > + ret); > + goto loongson_drm_unload; > + } > + > + drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth); > + > + return 0; > + > +loongson_drm_unload: > + loongson_drm_unload(dev); > +err_pdev: > + pci_disable_device(pdev); > +err_free: > + drm_dev_put(dev); > + return ret; > +} > + > +static void loongson_pci_remove(struct pci_dev *pdev) > +{ > + struct drm_device *dev = pci_get_drvdata(pdev); > + > + drm_dev_unregister(dev); > + loongson_drm_unload(dev); > + drm_dev_put(dev); > +} > + > +static struct pci_device_id loongson_pci_devices[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC) }, > + {0,} > +}; > + > +static struct pci_driver loongson_drm_pci_driver = { > + .name = DRIVER_NAME, > + .id_table = loongson_pci_devices, > + .probe = loongson_pci_probe, > + .remove = loongson_pci_remove, > +}; > + > +static int __init loongson_drm_init(void) > +{ > + return pci_register_driver(&loongson_drm_pci_driver); > +} > + > +static void __exit loongson_drm_exit(void) > +{ > + pci_unregister_driver(&loongson_drm_pci_driver); > +} > + > +module_init(loongson_drm_init); > +module_exit(loongson_drm_exit); > + > +MODULE_AUTHOR(DRIVER_AUTHOR); > +MODULE_DESCRIPTION(DRIVER_DESC); > +MODULE_LICENSE("GPL v2"); > diff --git a/drivers/gpu/drm/loongson/loongson_drv.h b/drivers/gpu/drm/loongson/loongson_drv.h > new file mode 100644 > index 000000000000..e4ebb9026afd > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_drv.h > @@ -0,0 +1,140 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __LOONGSON_DRV_H__ > +#define __LOONGSON_DRV_H__ > + > +#include <drm/drm_drv.h> > +#include <drm/drm_gem.h> > +#include <drm/drm_fb_helper.h> > +#include <drm/drm_fourcc.h> > +#include <drm/drm_probe_helper.h> > +#include <drm/drm_atomic.h> > +#include <drm/drm_atomic_helper.h> > +#include <drm/drm_gem_framebuffer_helper.h> > +#include <drm/drm_gem_vram_helper.h> > +#include <drm/drm_plane.h> > +#include <drm/drm_plane_helper.h> > +#include <drm/drm_crtc.h> > +#include <drm/drm_crtc_helper.h> > +#include <drm/drm_connector.h> > +#include <drm/drm_encoder.h> > + > +/* General customization: > + */ > +#define DRIVER_AUTHOR "Loongson graphics driver team" > +#define DRIVER_NAME "loongson-drm" > +#define DRIVER_DESC "Loongson LS7A DRM driver" > +#define DRIVER_DATE "20200915" > + > +#define to_loongson_crtc(x) container_of(x, struct loongson_crtc, base) > +#define to_loongson_encoder(x) container_of(x, struct loongson_encoder, base) > + > +#define LS7A_CHIPCFG_REG_BASE (0x10010000) > +#define PCI_DEVICE_ID_LOONGSON_DC 0x7a06 > +#define PCI_DEVICE_ID_LOONGSON_GPU 0x7a15 > +#define LS7A_PIX_PLL (0x04b0) > +#define REG_OFFSET (0x10) > +#define FB_CFG_REG (0x1240) > +#define FB_ADDR0_REG (0x1260) > +#define FB_ADDR1_REG (0x1580) > +#define FB_STRI_REG (0x1280) > +#define FB_DITCFG_REG (0x1360) > +#define FB_DITTAB_LO_REG (0x1380) > +#define FB_DITTAB_HI_REG (0x13a0) > +#define FB_PANCFG_REG (0x13c0) > +#define FB_PANTIM_REG (0x13e0) > +#define FB_HDISPLAY_REG (0x1400) > +#define FB_HSYNC_REG (0x1420) > +#define FB_VDISPLAY_REG (0x1480) > +#define FB_VSYNC_REG (0x14a0) > + > +#define CFG_FMT GENMASK(2, 0) > +#define CFG_FBSWITCH BIT(7) > +#define CFG_ENABLE BIT(8) > +#define CFG_FBNUM BIT(11) > +#define CFG_GAMMAR BIT(12) > +#define CFG_RESET BIT(20) > + > +#define FB_PANCFG_DEF 0x80001311 > +#define FB_HSYNC_PULSE (1 << 30) > +#define FB_VSYNC_PULSE (1 << 30) > + > +/* PIX PLL */ > +#define LOOPC_MIN 24 > +#define LOOPC_MAX 161 > +#define FRE_REF_MIN 12 > +#define FRE_REF_MAX 32 > +#define DIV_REF_MIN 3 > +#define DIV_REF_MAX 5 > +#define PST_DIV_MAX 64 > + > +struct pix_pll { > + u32 l2_div; > + u32 l1_loopc; > + u32 l1_frefc; > +}; > + > +struct loongson_crtc { > + struct drm_crtc base; > + struct loongson_device *ldev; > + u32 crtc_id; > + u32 reg_offset; > + u32 cfg_reg; > + struct drm_plane plane; > +}; > + > +struct loongson_encoder { > + struct drm_encoder base; > + struct loongson_device *ldev; > + struct loongson_crtc *lcrtc; > +}; > + > +struct loongson_connector { > + struct drm_connector base; > + struct loongson_device *ldev; > + u16 id; > + u32 type; > +}; > + > +struct loongson_mode_info { > + struct loongson_device *ldev; > + struct loongson_crtc *crtc; > + struct loongson_encoder *encoder; > + struct loongson_connector *connector; > +}; > + > +struct loongson_device { > + struct drm_device *dev; > + struct drm_atomic_state *state; > + > + void __iomem *mmio; > + void __iomem *io; > + u32 vram_start; > + u32 vram_size; > + > + u32 num_crtc; > + struct loongson_mode_info mode_info[2]; > + struct pci_dev *gpu_pdev; /* LS7A gpu device info */ > +}; > + > +/* crtc */ > +int loongson_crtc_init(struct loongson_device *ldev, int index); > + > +/* connector */ > +int loongson_connector_init(struct loongson_device *ldev, int index); > + > +/* encoder */ > +int loongson_encoder_init(struct loongson_device *ldev, int index); > + > +/* plane */ > +int loongson_plane_init(struct loongson_crtc *lcrtc); > + > +/* device */ > +u32 loongson_gpu_offset(struct drm_plane_state *state, > + struct loongson_device *dev); > +u32 ls7a_mm_rreg(struct loongson_device *ldev, u32 offset); > +void ls7a_mm_wreg(struct loongson_device *ldev, u32 offset, u32 val); > +u32 ls7a_io_rreg(struct loongson_device *ldev, u32 offset); > +void ls7a_io_wreg(struct loongson_device *ldev, u32 offset, u32 val); > + > +#endif /* __LOONGSON_DRV_H__ */ > diff --git a/drivers/gpu/drm/loongson/loongson_encoder.c b/drivers/gpu/drm/loongson/loongson_encoder.c > new file mode 100644 > index 000000000000..b64ff3bf610b > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_encoder.c > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "loongson_drv.h" > + > +static void loongson_encoder_destroy(struct drm_encoder *encoder) > +{ > + struct loongson_encoder *lencoder = to_loongson_encoder(encoder); > + > + drm_encoder_cleanup(encoder); > + kfree(lencoder); > +} > + > +static const struct drm_encoder_funcs loongson_encoder_funcs = { > + .destroy = loongson_encoder_destroy, > +}; > + > +int loongson_encoder_init(struct loongson_device *ldev, int index) > +{ > + struct drm_encoder *encoder; > + struct loongson_encoder *lencoder; > + > + lencoder = kzalloc(sizeof(struct loongson_encoder), GFP_KERNEL); > + if (!lencoder) > + return -ENOMEM; > + > + lencoder->lcrtc = ldev->mode_info[index].crtc; > + lencoder->ldev = ldev; > + encoder = &lencoder->base; > + encoder->possible_crtcs = 1 << index; > + > + drm_encoder_init(ldev->dev, encoder, &loongson_encoder_funcs, > + DRM_MODE_ENCODER_DAC, NULL); Please use the drmm_encoder version here too. > + > + ldev->mode_info[index].encoder = lencoder; > + > + return 0; > +} > diff --git a/drivers/gpu/drm/loongson/loongson_plane.c b/drivers/gpu/drm/loongson/loongson_plane.c > new file mode 100644 > index 000000000000..679d6981fece > --- /dev/null > +++ b/drivers/gpu/drm/loongson/loongson_plane.c > @@ -0,0 +1,97 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > + > +#include "loongson_drv.h" > + > +static void loongson_plane_atomic_update(struct drm_plane *plane, > + struct drm_atomic_state *state) > +{ > + struct loongson_crtc *lcrtc; > + struct loongson_device *ldev; > + struct drm_plane_state *lstate = plane->state; > + u32 gpu_addr = 0; > + u32 fb_addr = 0; > + u32 reg_val = 0; > + u32 reg_offset; > + u32 pitch; > + u8 depth; > + u32 x, y; > + > + if (!lstate->crtc || !lstate->fb) > + return; > + > + pitch = lstate->fb->pitches[0]; > + lcrtc = to_loongson_crtc(lstate->crtc); > + ldev = lcrtc->ldev; > + reg_offset = lcrtc->reg_offset; > + x = lstate->crtc->x; > + y = lstate->crtc->y; > + depth = lstate->fb->format->cpp[0] << 3; > + > + gpu_addr = loongson_gpu_offset(lstate, ldev); > + reg_val = (pitch + 255) & ~255; > + ls7a_mm_wreg(ldev, FB_STRI_REG + reg_offset, reg_val); > + > + switch (depth) { > + case 12 ... 16: > + fb_addr = gpu_addr + y * pitch + ALIGN(x, 64) * 2; > + break; > + case 24 ... 32: > + default: > + fb_addr = gpu_addr + y * pitch + ALIGN(x, 64) * 4; > + break; > + } > + > + ls7a_mm_wreg(ldev, FB_ADDR0_REG + reg_offset, fb_addr); > + ls7a_mm_wreg(ldev, FB_ADDR1_REG + reg_offset, fb_addr); > + reg_val = lcrtc->cfg_reg | CFG_ENABLE; > + ls7a_mm_wreg(ldev, FB_CFG_REG + reg_offset, reg_val); > +} > + > +static const uint32_t loongson_formats[] = { > + DRM_FORMAT_RGB565, > + DRM_FORMAT_RGB888, > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_ARGB8888, > +}; > + > +static const uint64_t loongson_format_modifiers[] = { DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID }; > + > +static const struct drm_plane_funcs loongson_plane_funcs = { > + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > + .destroy = drm_plane_cleanup, > + .disable_plane = drm_atomic_helper_disable_plane, > + .reset = drm_atomic_helper_plane_reset, > + .update_plane = drm_atomic_helper_update_plane, > +}; > + > +static const struct drm_plane_helper_funcs loongson_plane_helper_funcs = { > + .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, > + .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, > + .atomic_update = loongson_plane_atomic_update, > +}; > + > +int loongson_plane_init(struct loongson_crtc *lcrtc) > +{ > + struct loongson_device *ldev; > + int crtc_id; > + int ret; > + > + ldev = lcrtc->ldev; > + crtc_id = lcrtc->crtc_id; > + > + ret = drm_universal_plane_init(ldev->dev, &lcrtc->plane, BIT(crtc_id), > + &loongson_plane_funcs, loongson_formats, > + ARRAY_SIZE(loongson_formats), > + loongson_format_modifiers, > + DRM_PLANE_TYPE_PRIMARY, NULL); > + if (ret) { > + DRM_ERROR("fail to init planed crtc %d\n", crtc_id); > + return ret; > + } > + > + drm_plane_helper_add(&lcrtc->plane, &loongson_plane_helper_funcs); > + > + return 0; > +} > -- > 2.32.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

2 3

[PATCH v3 00/13] drm/msm: drm scheduler conversion and cleanups
by Rob Clark 27 Jul '21

27 Jul '21

From: Rob Clark <robdclark(a)chromium.org> Conversion to gpu_scheduler, and bonus removal of drm_gem_object_put_locked() v2: Fix priority mixup (msm UAPI has lower numeric priority value as higher priority, inverse of drm/scheduler) and add some comments in the UAPI header to clarify. Now that we move active refcnt get into msm_gem_submit, add a patch to mark all bos busy before pinning, to avoid evicting bos used in same batch. Fix bo locking for cmdstream dumping ($debugfs/n/{rd,hangrd}) v3: Add a patch to drop submit bo_list and instead use -EALREADY to detect errors with same obj appearing multiple times in the submit ioctl bos table. Otherwise, with struct_mutex locking dropped, we'd need to move insertion into and removal from bo_list under the obj lock. Rob Clark (13): drm/msm: Docs and misc cleanup drm/msm: Small submitqueue creation cleanup drm/msm: drop drm_gem_object_put_locked() drm: Drop drm_gem_object_put_locked() drm/msm/submit: Simplify out-fence-fd handling drm/msm: Consolidate submit bo state drm/msm: Track "seqno" fences by idr drm/msm: Return ERR_PTR() from submit_create() drm/msm: Conversion to drm scheduler drm/msm: Drop submit bo_list drm/msm: Drop struct_mutex in submit path drm/msm: Utilize gpu scheduler priorities drm/msm/gem: Mark active before pinning drivers/gpu/drm/drm_gem.c | 22 -- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 7 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 12 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 +- drivers/gpu/drm/msm/msm_drv.c | 30 +- drivers/gpu/drm/msm/msm_fence.c | 39 --- drivers/gpu/drm/msm/msm_fence.h | 2 - drivers/gpu/drm/msm/msm_gem.c | 94 +----- drivers/gpu/drm/msm/msm_gem.h | 47 +-- drivers/gpu/drm/msm/msm_gem_submit.c | 344 ++++++++++++-------- drivers/gpu/drm/msm/msm_gpu.c | 46 +-- drivers/gpu/drm/msm/msm_gpu.h | 78 ++++- drivers/gpu/drm/msm/msm_rd.c | 6 +- drivers/gpu/drm/msm/msm_ringbuffer.c | 70 +++- drivers/gpu/drm/msm/msm_ringbuffer.h | 12 + drivers/gpu/drm/msm/msm_submitqueue.c | 53 ++- include/drm/drm_gem.h | 2 - include/uapi/drm/msm_drm.h | 14 +- 24 files changed, 516 insertions(+), 387 deletions(-) -- 2.31.1

1 13

[pull] drm/msm: drm-msm-fixes-2021-07-27 for v5.14-rc4
by Rob Clark 27 Jul '21

27 Jul '21

Hi Dave & Daniel, A few fixes for v5.14, including a fix for a crash if display triggers an iommu fault (which tends to happen at probe time on devices with bootloader fw that leaves display enabled as kernel starts) The following changes since commit ff1176468d368232b684f75e82563369208bc371: Linux 5.14-rc3 (2021-07-25 15:35:14 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git drm-msm-fixes-2021-07-27 for you to fetch changes up to fc71c9e6f41f9912d22a75dfa76bc10811af7e22: drm/msm/dp: Initialize dp->aux->drm_dev before registration (2021-07-27 08:14:58 -0700) ---------------------------------------------------------------- Bjorn Andersson (1): drm/msm/dp: Initialize the INTF_CONFIG register Kuogee Hsieh (2): drm/msm/dp: use dp_ctrl_off_link_stream during PHY compliance test run drm/msm/dp: signal audio plugged change at dp_pm_resume Rob Clark (1): drm/msm: Fix display fault handling Robert Foss (1): drm/msm/dpu: Fix sm8250_mdp register length Sean Paul (1): drm/msm/dp: Initialize dp->aux->drm_dev before registration drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 1 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 5 +++++ drivers/gpu/drm/msm/msm_iommu.c | 11 ++++++++++- 5 files changed, 18 insertions(+), 3 deletions(-)

1 0

[PATCH v2 0/5] video: fbdev: ssd1307fb: Optimizations and improvements
by Geert Uytterhoeven 27 Jul '21

27 Jul '21

Hi all, This patch series optimizes console operations on ssd1307fb, after the customary fixes and cleanups. Currently, each screen update triggers an I2C transfer of all screen data, up to 1 KiB of data for a 128x64 display, which takes at least 20 ms in Fast mode. While many displays are smaller, and thus require less data to be transferred, 20 ms is still an optimistic value, as the actual data transfer may be much slower, especially on bitbanged I2C drivers. After this series, the amount of data transfer is reduced, as fillrect, copyarea, and imageblit only update the rectangle that changed. Changes compared to v1[1]: - Add Acked-by, - Use two separate helpers instead of a single combined helper, - Reorder operands in DIV_ROUND_UP() to improve readability. This has been tested on an Adafruit FeatherWing OLED with an SSD1306 controller and a 128x32 OLED, connected to an OrangeCrab ECP5 FPGA board running a 64 MHz VexRiscv RISC-V softcore, where it reduced the CPU usage for blinking the cursor from more than 70% to ca. 10%. Thanks for applying! [1] https://lore.kernel.org/dri-devel/20210714145804.2530727-1-geert@linux-m68k… Geert Uytterhoeven (5): video: fbdev: ssd1307fb: Propagate errors via ssd1307fb_update_display() video: fbdev: ssd1307fb: Simplify ssd1307fb_update_display() video: fbdev: ssd1307fb: Extract ssd1307fb_set_{col,page}_range() video: fbdev: ssd1307fb: Optimize screen updates video: fbdev: ssd1307fb: Cache address ranges drivers/video/fbdev/ssd1307fb.c | 151 ++++++++++++++++++++++---------- 1 file changed, 104 insertions(+), 47 deletions(-) -- 2.25.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert(a)linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds

2 6

[PATCH v2] gpu: ipu-v3: use swap()
by Salah Triki 27 Jul '21

27 Jul '21

Use swap() instead of implementing it since it makes code cleaner. Signed-off-by: Salah Triki <salah.triki(a)gmail.com> --- Changes since v1: - Remove the declaration of tmp - Fix typo in the description drivers/gpu/ipu-v3/ipu-image-convert.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c b/drivers/gpu/ipu-v3/ipu-image-convert.c index aa1d4b6d278f..af1612044eef 100644 --- a/drivers/gpu/ipu-v3/ipu-image-convert.c +++ b/drivers/gpu/ipu-v3/ipu-image-convert.c @@ -990,7 +990,7 @@ static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, const struct ipu_image_pixfmt *fmt = image->fmt; unsigned int row, col, tile = 0; u32 H, top, y_stride, uv_stride; - u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; + u32 uv_row_off, uv_col_off, uv_off, u_off, v_off; u32 y_row_off, y_col_off, y_off; u32 y_size, uv_size; @@ -1021,11 +1021,8 @@ static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, u_off = y_size - y_off + uv_off; v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; - if (fmt->uv_swapped) { - tmp = u_off; - u_off = v_off; - v_off = tmp; - } + if (fmt->uv_swapped) + swap(u_off, v_off); image->tile[tile].offset = y_off; image->tile[tile].u_off = u_off; -- 2.25.1

2 1

[PATCH] Fix i.MX IPU-v3 offset calculations for (semi)planar U/V formats
by Krzysztof Hałasa 27 Jul '21

27 Jul '21

Video captured in 1400x1050 resolution (bytesperline aka stride = 1408 bytes) is invalid. Fix it. Signed-off-by: Krzysztof Halasa <khalasa(a)piap.pl> --- a/drivers/gpu/ipu-v3/ipu-cpmem.c +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c @@ -585,21 +585,21 @@ static const struct ipu_rgb def_bgra_16 = { .bits_per_pixel = 16, }; -#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) -#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * ((y) / 2) / 2) + (x) / 2) -#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * pix->height / 4) + \ - (pix->width * ((y) / 2) / 2) + (x) / 2) -#define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * (y) / 2) + (x) / 2) -#define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * pix->height / 2) + \ - (pix->width * (y) / 2) + (x) / 2) -#define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * ((y) / 2)) + (x)) -#define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * y) + (x)) +#define Y_OFFSET(pix, x, y) ((x) + pix->bytesperline * (y)) +#define U_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * ((y) / 2) / 2) + (x) / 2) +#define V_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * pix->height / 4) + \ + (pix->bytesperline * ((y) / 2) / 2) + (x) / 2) +#define U2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * (y) / 2) + (x) / 2) +#define V2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * pix->height / 2) + \ + (pix->bytesperline * (y) / 2) + (x) / 2) +#define UV_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * ((y) / 2)) + (x)) +#define UV2_OFFSET(pix, x, y) ((pix->bytesperline * pix->height) + \ + (pix->bytesperline * y) + (x)) #define NUM_ALPHA_CHANNELS 7 -- Krzysztof Hałasa Sieć Badawcza Łukasiewicz Przemysłowy Instytut Automatyki i Pomiarów PIAP Al. Jerozolimskie 202, 02-486 Warszawa

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[PATCH AUTOSEL 5.10 16/17] drm/amd/display: Fix max vstartup calculation for modes with borders
by Sasha Levin 27 Jul '21

27 Jul '21

From: Nicholas Kazlauskas <nicholas.kazlauskas(a)amd.com> [ Upstream commit d7940911fc0754d99b208f0e3098762d39f403a0 ] [Why] Vertical and horizontal borders in timings are treated as increasing the active area - vblank and hblank actually shrink. Our input into DML does not include these borders so it incorrectly assumes it has more time than available for vstartup and tmdl calculations for some modes with borders. An example of such a timing would be 640x480@72Hz: h_total: 832 h_border_left: 8 h_addressable: 640 h_border_right: 8 h_front_porch: 16 h_sync_width: 40 v_total: 520 v_border_top: 8 v_addressable: 480 v_border_bottom: 8 v_front_porch: 1 v_sync_width: 3 pix_clk_100hz: 315000 [How] Include borders as part of destination vactive/hactive. This change DCN20+ so it has wide impact, but the destination vactive and hactive are only really used for vstartup calculation anyway. Most modes do not have vertical or horizontal borders. Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin(a)amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira(a)amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 1812ec7ee11b..cfe85ba1018e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2077,8 +2077,10 @@ int dcn20_populate_dml_pipes_from_context( - timing->v_border_bottom; pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; pipes[pipe_cnt].pipe.dest.vtotal = v_total; - pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; - pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; + pipes[pipe_cnt].pipe.dest.hactive = + timing->h_addressable + timing->h_border_left + timing->h_border_right; + pipes[pipe_cnt].pipe.dest.vactive = + timing->v_addressable + timing->v_border_top + timing->v_border_bottom; pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) -- 2.30.2

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dri-devel July 2021