dri-devel July 2021

dri-devel@lists.freedesktop.org

321 participants
829 discussions

[PATCH 1/2] drm/amdkfd: Allow CPU access for all VRAM BOs
by Alex Deucher 12 Jul '21

12 Jul '21

From: Felix Kuehling <Felix.Kuehling(a)amd.com> The thunk needs to mmap all BOs for CPU access to allow the debugger to access them. Invisible ones are mapped with PROT_NONE. Fixes: 71df0368e9b6 ("drm/amdgpu: Implement mmap as GEM object function") Signed-off-by: Felix Kuehling <Felix.Kuehling(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 3e487e199771..2d6b2d77b738 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1404,8 +1404,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : - AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; alloc_flags = 0; -- 2.31.1

4 7

[PATCH v3 00/20] drm/sched dependency tracking and dma-resv fixes
by Daniel Vetter 12 Jul '21

12 Jul '21

Hil all, I figured I'll combine the two series, they build on top of each another anyway. Changes: - drop broken i915 patch (Matt) - typos and improvements in the dma-resv patch - bunch of fixes to the drm_sched_job_init/arm split (Melissa, Christian) - threw a drm_sched_entity doc patch on top Testing & review very much welcome. Cheers, Daniel Christian König (1): drm/msm: always wait for the exclusive fence Daniel Vetter (19): drm/sched: entity->rq selection cannot fail drm/sched: Split drm_sched_job_init drm/sched: Barriers are needed for entity->last_scheduled drm/sched: Add dependency tracking drm/sched: drop entity parameter from drm_sched_push_job drm/sched: improve docs around drm_sched_entity drm/panfrost: use scheduler dependency tracking drm/lima: use scheduler dependency tracking drm/v3d: Move drm_sched_job_init to v3d_job_init drm/v3d: Use scheduler dependency handling drm/etnaviv: Use scheduler dependency handling drm/gem: Delete gem array fencing helpers drm/sched: Don't store self-dependencies drm/sched: Check locking in drm_sched_job_await_implicit drm/msm: Don't break exclusive fence ordering drm/etnaviv: Don't break exclusive fence ordering drm/i915: delete exclude argument from i915_sw_fence_await_reservation drm/i915: Don't break exclusive fence ordering dma-resv: Give the docs a do-over Documentation/gpu/drm-mm.rst | 3 + drivers/dma-buf/dma-resv.c | 24 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +- drivers/gpu/drm/drm_gem.c | 96 --------- drivers/gpu/drm/etnaviv/etnaviv_gem.h | 5 +- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 64 +++--- drivers/gpu/drm/etnaviv/etnaviv_sched.c | 65 +----- drivers/gpu/drm/etnaviv/etnaviv_sched.h | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +- drivers/gpu/drm/i915/i915_sw_fence.c | 6 +- drivers/gpu/drm/i915/i915_sw_fence.h | 1 - drivers/gpu/drm/lima/lima_gem.c | 7 +- drivers/gpu/drm/lima/lima_sched.c | 28 +-- drivers/gpu/drm/lima/lima_sched.h | 6 +- drivers/gpu/drm/msm/msm_gem.c | 16 +- drivers/gpu/drm/msm/msm_gem_submit.c | 3 +- drivers/gpu/drm/panfrost/panfrost_drv.c | 16 +- drivers/gpu/drm/panfrost/panfrost_job.c | 39 +--- drivers/gpu/drm/panfrost/panfrost_job.h | 5 +- drivers/gpu/drm/scheduler/sched_entity.c | 140 +++++++------ drivers/gpu/drm/scheduler/sched_fence.c | 19 +- drivers/gpu/drm/scheduler/sched_main.c | 177 +++++++++++++++-- drivers/gpu/drm/v3d/v3d_drv.h | 6 +- drivers/gpu/drm/v3d/v3d_gem.c | 115 +++++------ drivers/gpu/drm/v3d/v3d_sched.c | 44 +---- include/drm/drm_gem.h | 5 - include/drm/gpu_scheduler.h | 186 ++++++++++++++---- include/linux/dma-buf.h | 7 + include/linux/dma-resv.h | 104 +++++++++- 32 files changed, 674 insertions(+), 538 deletions(-) -- 2.32.0

5 33

BUG: MTK DRM/HDMI broken on 5.13 (mt7623/bpi-r2)
by Frank Wunderlich 12 Jul '21

12 Jul '21

Hi, i've noticed that HDMI is broken at least on my board (Bananapi-r2,mt7623) on 5.13. after some research i noticed that it is working till commit 2e477391522354e763aa62ee3e281c1ad9e8eb1b Author: Dafna Hirschfeld <dafna.hirschfeld(a)collabora.com> Date: Tue Mar 30 13:09:02 2021 +0200 drm/mediatek: Don't support hdmi connector creation which is the last of mtk-drm-next-5.13 [1] so i guess a problem with core-patches dmesg shows the following: [ 7.071342] mediatek-drm mediatek-drm.1.auto: bound 14007000.ovl (ops mtk_dis p_ovl_component_ops) [ 7.080330] mediatek-drm mediatek-drm.1.auto: bound 14008000.rdma (ops mtk_di sp_rdma_component_ops) [ 7.089429] mediatek-drm mediatek-drm.1.auto: bound 1400b000.color (ops mtk_d isp_color_component_ops) [ 7.098689] mediatek-drm mediatek-drm.1.auto: bound 14012000.rdma (ops mtk_di sp_rdma_component_ops) [ 7.107814] mediatek-drm mediatek-drm.1.auto: bound 14014000.dpi (ops mtk_dpi _component_ops) [ 7.116338] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because com ponent 9 is disabled or missing .... [ 38.403957] Console: switching to colour frame buffer device 160x64 [ 48.516398] [drm:drm_crtc_commit_wait] *ERROR* flip_done timed out [ 48.516422] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CRTC:41:cr tc-0] commit wait timed out [ 58.756384] [drm:drm_crtc_commit_wait] *ERROR* flip_done timed out [ 58.756399] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CONNECTOR: 32:HDMI-A-1] commit wait timed out [ 68.996384] [drm:drm_crtc_commit_wait] *ERROR* flip_done timed out [ 68.996399] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [PLANE:33:p lane-0] commit wait timed out [ 68.996423] [drm:mtk_drm_crtc_atomic_begin] *ERROR* new event while there is still a pending event [ 69.106385] ------------[ cut here ]------------ [ 69.106392] WARNING: CPU: 2 PID: 7 at drivers/gpu/drm/drm_atomic_helper.c:151 1 drm_atomic_helper_wait_for_vblanks.part.0+0x2a0/0x2a8 [ 69.106414] [CRTC:41:crtc-0] vblank wait timed out so i guess the breaking commit may be this: $ git logone -S"drm_crtc_commit_wait" -- drivers/gpu/drm/ b99c2c95412c 2021-01-11 drm: Introduce a drm_crtc_commit_wait helper in drivers/gpu/drm/drm_atomic{,_helper}.c but i cannot confirm it because my git bisect does strange things (after defining 5.13 as bad and the 2e4773915223 as good, second step is before the good commit till the end, last steps are 5.11...). sorry, i'm still new to bisect. the fix is targeting to 5.12-rc2, is guess because CK Hu's tree is based on this...but the fix was not included in 5.12-rc2 (only after 5.12.0...got it by merging 5.12.14) maybe you can help me? regards Frank [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/…

5 17

[PATCH v4] drm/i915: Invoke another _DSM to enable MUX on HP Workstation laptops
by Kai-Heng Feng 12 Jul '21

12 Jul '21

On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX to discrete GFX after S3. This is not desirable, because userspace will treat connected display as a new one, losing display settings. The expected behavior is to let discrete GFX drives all external displays. The platform in question uses ACPI method \_SB.PCI0.HGME to enable MUX. The method is inside the another _DSM, so add the _DSM and call it accordingly. I also tested some MUX-less and iGPU only laptops with that _DSM, no regression was found. v4: - Rebase. - Change the DSM name to avoid confusion. - Move the function call to intel_opregion. v3: - Remove BXT from names. - Change the parameter type. - Fold the function into intel_modeset_init_hw(). v2: - Forward declare struct pci_dev. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3113 References: https://lore.kernel.org/intel-gfx/1460040732-31417-4-git-send-email-animesh… Signed-off-by: Kai-Heng Feng <kai.heng.feng(a)canonical.com> --- drivers/gpu/drm/i915/display/intel_acpi.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_acpi.h | 3 +++ drivers/gpu/drm/i915/display/intel_opregion.c | 3 +++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index 833d0c1be4f1..7cfe91fc05f2 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -19,6 +19,12 @@ static const guid_t intel_dsm_guid = GUID_INIT(0x7ed873d3, 0xc2d0, 0x4e4f, 0xa8, 0x54, 0x0f, 0x13, 0x17, 0xb0, 0x1c, 0x2c); +#define INTEL_DSM_FN_GET_BIOS_DATA_FUNCS_SUPPORTED 0 /* No args */ + +static const guid_t intel_dsm_guid2 = + GUID_INIT(0x3e5b41c6, 0xeb1d, 0x4260, + 0x9d, 0x15, 0xc7, 0x1f, 0xba, 0xda, 0xe4, 0x14); + static char *intel_dsm_port_name(u8 id) { switch (id) { @@ -176,6 +182,19 @@ void intel_unregister_dsm_handler(void) { } +void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + acpi_handle dhandle; + + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return; + + acpi_evaluate_dsm(dhandle, &intel_dsm_guid2, INTEL_DSM_REVISION_ID, + INTEL_DSM_FN_GET_BIOS_DATA_FUNCS_SUPPORTED, NULL); +} + /* * ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices * Attached to the Display Adapter). diff --git a/drivers/gpu/drm/i915/display/intel_acpi.h b/drivers/gpu/drm/i915/display/intel_acpi.h index e8b068661d22..9f197401c313 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.h +++ b/drivers/gpu/drm/i915/display/intel_acpi.h @@ -11,11 +11,14 @@ struct drm_i915_private; #ifdef CONFIG_ACPI void intel_register_dsm_handler(void); void intel_unregister_dsm_handler(void); +void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915); void intel_acpi_device_id_update(struct drm_i915_private *i915); #else static inline void intel_register_dsm_handler(void) { return; } static inline void intel_unregister_dsm_handler(void) { return; } static inline +void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) { return; } +static inline void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; } #endif /* CONFIG_ACPI */ diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index dfd724e506b5..3855fba70980 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -1078,6 +1078,9 @@ void intel_opregion_resume(struct drm_i915_private *i915) opregion->asle->ardy = ASLE_ARDY_READY; } + /* Some platforms abuse the _DSM to enable MUX */ + intel_dsm_get_bios_data_funcs_supported(i915); + intel_opregion_notify_adapter(i915, PCI_D0); } -- 2.31.1

2 3

[PATCH 5.13 407/800] drm/i915: Merge fix for "drm: Switch to %p4cc format modifier"
by Greg Kroah-Hartman 12 Jul '21

12 Jul '21

From: Stephen Rothwell <sfr(a)canb.auug.org.au> [ Upstream commit e3c2f1870af43fc95f6fe141537f5142c5fe4717 ] Signed-off-by: Stephen Rothwell <sfr(a)canb.auug.org.au> Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 92f1d09ca4ed ("drm: Switch to %p4cc format modifier") Cc: Sakari Ailus <sakari.ailus(a)linux.intel.com> Cc: Petr Mladek <pmladek(a)suse.com> Cc: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> Cc: dri-devel(a)lists.freedesktop.org Link: https://lore.kernel.org/dri-devel/20210514115307.4364aff9@canb.auug.org.au/… Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7ffd7b570b54..538682f882b1 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1082,7 +1082,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; - struct drm_format_name_buf format_name; if (!fb) return 0; @@ -1130,9 +1129,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: drm_dbg_kms(&dev_priv->drm, - "Unsupported pixel format %s for 90/270!\n", - drm_get_format_name(fb->format->format, - &format_name)); + "Unsupported pixel format %p4cc for 90/270!\n", + &fb->format->format); return -EINVAL; default: break; -- 2.30.2

1 0

[v1] drm/msm/disp/dpu1: add safe lut config in dpu driver
by Kalyan Thota 12 Jul '21

12 Jul '21

Add safe lut configuration for all the targets in dpu driver as per QOS recommendation. Issue reported on SC7280: With wait-for-safe feature in smmu enabled, RT client buffer levels are checked to be safe before smmu invalidation. Since display was always set to unsafe it was delaying the invalidaiton process thus impacting the performance on NRT clients such as eMMC and NVMe. Validated this change on SC7280, With this change eMMC performance has improved significantly. Signed-off-by: Kalyan Thota <kalyan_t(a)codeaurora.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index d01c4c9..2e482cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = { .amortizable_threshold = 25, .min_prefill_lines = 24, .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sdm845_qos_linear), .entries = sdm845_qos_linear @@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = { .min_dram_ib = 1600000, .min_prefill_lines = 24, .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sc7180_qos_linear), .entries = sc7180_qos_linear @@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = { .min_dram_ib = 800000, .min_prefill_lines = 24, .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sm8150_qos_linear), .entries = sm8150_qos_linear @@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .min_dram_ib = 800000, .min_prefill_lines = 35, .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sc7180_qos_linear), .entries = sc7180_qos_linear @@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = { .min_dram_ib = 1600000, .min_prefill_lines = 24, .danger_lut_tbl = {0xffff, 0xffff, 0x0}, + .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), .entries = sc7180_qos_macrotile -- 2.7.4

3 2

drm/amd/display: Simplify hdcp validate_bksv
by Joe Perches 12 Jul '21

12 Jul '21

commit 06888d571b51 ("drm/amd/display: Avoid HDCP over-read and corruption") fixed an overread with an invalid buffer length but added an unnecessary buffer and copy. Simplify the code by using a single uint64_t and __builtin_popcountll to count the number of bits set in the original bksv buffer instead of a loop. This also avoid a possible unaligned access of the temporary bksv. Signed-off-by: Joe Perches <joe(a)perches.com> --- It seems quite odd 20 bits set is a magic number here. Should it be a specific be/le value instead? drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c index de872e7958b06..78a4c6dd95d99 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c @@ -28,17 +28,10 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp) { uint64_t n = 0; - uint8_t count = 0; - u8 bksv[sizeof(n)] = { }; - memcpy(bksv, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv)); - n = *(uint64_t *)bksv; + memcpy(&n, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv)); - while (n) { - count++; - n &= (n - 1); - } - return (count == 20) ? MOD_HDCP_STATUS_SUCCESS : + return (__builtin_popcountll(n) == 20) ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_HDCP1_INVALID_BKSV; }

2 3

[drm/i915/gem] d9d29c747d: assertion_failure
by kernel test robot 12 Jul '21

12 Jul '21

Greeting, FYI, we noticed the following commit (built with gcc-9): commit: d9d29c747df844e946ecd6089893be80c5d32403 ("drm/i915/gem: Don't allow changing the engine set on running contexts (v3)") git://anongit.freedesktop.org/drm-intel drm-intel-gt-next in testcase: igt version: igt-x86_64-098d0b82-1_20210701 with following parameters: group: group-09 ucode: 0xe2 on test machine: 8 threads Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz with 28G memory caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace): If you fix the issue, kindly add following tag Reported-by: kernel test robot <oliver.sang(a)intel.com> [ 61.793502] [ 61.799687] - With timeslicing enabled [ 61.799689] [ 61.805694] Starting subtest: default-virtual [ 61.805696] [ 61.813914] (gem_watchdog:1648) CRITICAL: Test assertion failure function set_load_balancer, file ../tests/i915/gem_watchdog.c:244: [ 61.813917] [ 61.827334] Console: switching to colour dummy device 80x25 [ 61.829275] (gem_watchdog:1648) CRITICAL: Failed assertion: __set_load_balancer(i915, ctx, ci, count, ext) == 0 [ 61.832911] [ 61.833008] [IGT] kms_cdclk: executing To reproduce: git clone https://github.com/intel/lkp-tests.git cd lkp-tests bin/lkp install job.yaml # job file is attached in this email bin/lkp split-job --compatible job.yaml # generate the yaml file for lkp run bin/lkp run generated-yaml-file --- 0DAY/LKP+ Test Infrastructure Open Source Technology Center https://lists.01.org/hyperkitty/list/lkp@lists.01.org Intel Corporation Thanks, Oliver Sang

1 0

[RESEND PATCH v4] drm/panel: simple: add SGD GKTW70SDAD1SD
by Oliver Graute 11 Jul '21

11 Jul '21

Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD to panel-simple. The panel spec from Variscite can be found at: https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf Signed-off-by: Oliver Graute <oliver.graute(a)gmail.com> Reviewed-by: Marco Felsch <m.felsch(a)pengutronix.de> Reviewed-by: Fabio Estevam <festevam(a)gmail.com> --- v4: - added the datasheet labels - added Reviewed-by v3: - added flags - added delay v2: - changed bpc to 6 - set max value of pixelclock - increased hfront_porch and hback_porch - dropped connector-type adding of bus_format = MEDIA_BUS_FMT_RGB666_1X18 results in wrong colors. omitting bus_format and using some default is better (Tux Pinguin is colored fine) drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 2be358f..c63f6a8 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -3336,6 +3336,36 @@ static const struct panel_desc satoz_sat050at40h12r2 = { .connector_type = DRM_MODE_CONNECTOR_LVDS, }; +static const struct display_timing sgd_gktw70sdad1sd_timing = { + .pixelclock = {30000000, 30000000, 40000000}, + .hactive = { 800, 800, 800}, + .hfront_porch = {40, 40, 40}, + .hback_porch = {40, 40, 40}, + .hsync_len = {48, 48, 48}, + .vactive = {480, 480, 480}, + .vfront_porch = {13, 13, 13}, + .vback_porch = {29, 29, 29}, + .vsync_len = {3, 3, 3}, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + +static const struct panel_desc sgd_gktw70sdad1sd = { + .timings = &sgd_gktw70sdad1sd_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 153, + .height = 86, + }, + .delay = { + .prepare = 20 + 20 + 10 + 10, /* T0 + T2 + T3 + T4 */ + .enable = 50, /* T5 */ + .disable = 50, /* T5 */ + .unprepare = 10 + 10 + 20 + 20, /* T4 + T3 + T2 + T0 */ + }, +}; + static const struct drm_display_mode sharp_ld_d5116z01b_mode = { .clock = 168480, .hdisplay = 1920, @@ -4222,6 +4252,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "satoz,sat050at40h12r2", .data = &satoz_sat050at40h12r2, }, { + .compatible = "sgd,gktw70sdad1sd", + .data = &sgd_gktw70sdad1sd, + }, { .compatible = "sharp,ld-d5116z01b", .data = &sharp_ld_d5116z01b, }, { -- 2.7.4

2 1

[PATCH] drm/amd/display: Fix identical code for different branches
by Len Baker 11 Jul '21

11 Jul '21

The ternary expression: vrr->state == VRR_STATE_ACTIVE_VARIABLE ? max_refresh : max_refresh; has identical then and else expressions. So, simplify the code. Addresses-Coverity-ID: 1471122 ("Identical code for different branches") Fixes: 9bc4162665827 ("drm/amd/display: Implement VSIF V3 extended refresh rate feature") Signed-off-by: Len Baker <len.baker(a)gmx.com> --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 3f4f44b44e6a..54374c7d309b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -613,9 +613,8 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, (vrr->state == VRR_STATE_INACTIVE) ? min_refresh : max_refresh; // Non-fs case, program nominal range - max_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh : - (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? max_refresh : - max_refresh;// Non-fs case, program nominal range + max_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? + fixed_refresh : max_refresh; /* PB7 = FreeSync Minimum refresh rate (Hz) */ infopacket->sb[7] = min_programmed & 0xFF; -- 2.25.1

1 0

← Newer
1
...
64
65
66
67
68
69
70
...
83
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel July 2021