dri-devel September 2021

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[PATCH] drm/i915: Make wa list per-gt
by Matt Roper 20 Sep '21

20 Sep '21

From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota(a)intel.com> Support for multiple GT's within a single i915 device will be arriving soon. Since each GT may have its own fusing and require different workarounds, we need to make the GT workaround functions and multicast steering setup per-gt. Cc: Tvrtko Ursulin <tvrtko.ursulin(a)linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio(a)intel.com> Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota(a)intel.com> Signed-off-by: Matt Roper <matthew.d.roper(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 143 +++++++++--------- drivers/gpu/drm/i915/gt/intel_workarounds.h | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 2 - drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/i915_gem.c | 2 - 8 files changed, 81 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 55e87aff51d2..449ff6e83543 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt) if (err) return err; + intel_gt_init_workarounds(gt); + /* * This is just a security blanket to placate dragons. * On some systems, we very sporadically observe that the first TLBs @@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt) if (vm) /* FIXME being called twice on error paths :( */ i915_vm_put(vm); + intel_wa_list_free(&gt->wa_list); intel_gt_pm_fini(gt); intel_gt_fini_scratch(gt); intel_gt_fini_buffer_pool(gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 6fdcde64c180..ce127cae9e49 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -72,6 +72,8 @@ struct intel_gt { struct intel_uc uc; + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index c314d4917b6b..1f0a54b383d9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) } static void -gen4_gt_workarounds_init(struct drm_i915_private *i915, +gen4_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ @@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915, } static void -g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen4_gt_workarounds_init(i915, wal); + gen4_gt_workarounds_init(gt, wal); /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); } static void -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - g4x_gt_workarounds_init(i915, wal); + g4x_gt_workarounds_init(gt, wal); wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); } static void -snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { } static void -ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ wa_masked_dis(wal, @@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* WaForceL3Serialization:vlv */ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); @@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); @@ -878,15 +878,15 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* WaDisableKillLogic:bxt,skl,kbl */ - if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) + if (!IS_COFFEELAKE(gt->i915) && !IS_COMETLAKE(gt->i915)) wa_write_or(wal, GAM_ECOCHK, ECOCHK_DIS_TLB); - if (HAS_LLC(i915)) { + if (HAS_LLC(gt->i915)) { /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl * * Must match Display Engine. See @@ -904,9 +904,9 @@ gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal } static void -skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen9_gt_workarounds_init(i915, wal); + gen9_gt_workarounds_init(gt, wal); /* WaDisableGafsUnitClkGating:skl */ wa_write_or(wal, @@ -914,19 +914,19 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); /* WaInPlaceDecompressionHang:skl */ - if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0)) + if (IS_SKL_GT_STEP(gt->i915, STEP_A0, STEP_H0)) wa_write_or(wal, GEN9_GAMT_ECO_REG_RW_IA, GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); } static void -kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen9_gt_workarounds_init(i915, wal); + gen9_gt_workarounds_init(gt, wal); /* WaDisableDynamicCreditSharing:kbl */ - if (IS_KBL_GT_STEP(i915, 0, STEP_C0)) + if (IS_KBL_GT_STEP(gt->i915, 0, STEP_C0)) wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); @@ -943,15 +943,15 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen9_gt_workarounds_init(i915, wal); + gen9_gt_workarounds_init(gt, wal); } static void -cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen9_gt_workarounds_init(i915, wal); + gen9_gt_workarounds_init(gt, wal); /* WaDisableGafsUnitClkGating:cfl */ wa_write_or(wal, @@ -976,21 +976,21 @@ static void __set_mcr_steering(struct i915_wa_list *wal, wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); } -static void __add_mcr_wa(struct drm_i915_private *i915, struct i915_wa_list *wal, +static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, unsigned int slice, unsigned int subslice) { - drm_dbg(&i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); + drm_dbg(&gt->i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); } static void -icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) +icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) { - const struct sseu_dev_info *sseu = &i915->gt.info.sseu; + const struct sseu_dev_info *sseu = &gt->info.sseu; unsigned int slice, subslice; - GEM_BUG_ON(GRAPHICS_VER(i915) < 11); + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); slice = 0; @@ -1010,16 +1010,15 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) * then we can just rely on the default steering and won't need to * worry about explicitly re-steering L3BANK reads later. */ - if (i915->gt.info.l3bank_mask & BIT(subslice)) - i915->gt.steering_table[L3BANK] = NULL; + if (gt->info.l3bank_mask & BIT(subslice)) + gt->steering_table[L3BANK] = NULL; - __add_mcr_wa(i915, wal, slice, subslice); + __add_mcr_wa(gt, wal, slice, subslice); } static void xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) { - struct drm_i915_private *i915 = gt->i915; const struct sseu_dev_info *sseu = &gt->info.sseu; unsigned long slice, subslice = 0, slice_mask = 0; u64 dss_mask = 0; @@ -1083,7 +1082,7 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) WARN_ON(subslice > GEN_DSS_PER_GSLICE); WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); - __add_mcr_wa(i915, wal, slice, subslice); + __add_mcr_wa(gt, wal, slice, subslice); /* * SQIDI ranges are special because they use different steering @@ -1099,9 +1098,11 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) } static void -icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - icl_wa_init_mcr(i915, wal); + struct drm_i915_private *i915 = gt->i915; + + icl_wa_init_mcr(gt, wal); /* WaModifyGamTlbPartitioning:icl */ wa_write_clr_set(wal, @@ -1152,10 +1153,9 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) * the engine-specific workaround list. */ static void -wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) +wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) { struct intel_engine_cs *engine; - struct intel_gt *gt = &i915->gt; int id; for_each_engine(engine, gt, id) { @@ -1169,22 +1169,23 @@ wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -gen12_gt_workarounds_init(struct drm_i915_private *i915, - struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - icl_wa_init_mcr(i915, wal); + icl_wa_init_mcr(gt, wal); /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ - wa_14011060649(i915, wal); + wa_14011060649(gt, wal); /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen12_gt_workarounds_init(i915, wal); + struct drm_i915_private *i915 = gt->i915; + + gen12_gt_workarounds_init(gt, wal); /* Wa_1409420604:tgl */ if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) @@ -1205,9 +1206,11 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - gen12_gt_workarounds_init(i915, wal); + struct drm_i915_private *i915 = gt->i915; + + gen12_gt_workarounds_init(gt, wal); /* Wa_1607087056:dg1 */ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0)) @@ -1229,60 +1232,62 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -xehpsdv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - xehp_init_mcr(&i915->gt, wal); + xehp_init_mcr(gt, wal); } static void -gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) +gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) { + struct drm_i915_private *i915 = gt->i915; + if (IS_XEHPSDV(i915)) - xehpsdv_gt_workarounds_init(i915, wal); + xehpsdv_gt_workarounds_init(gt, wal); else if (IS_DG1(i915)) - dg1_gt_workarounds_init(i915, wal); + dg1_gt_workarounds_init(gt, wal); else if (IS_TIGERLAKE(i915)) - tgl_gt_workarounds_init(i915, wal); + tgl_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) == 12) - gen12_gt_workarounds_init(i915, wal); + gen12_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) == 11) - icl_gt_workarounds_init(i915, wal); + icl_gt_workarounds_init(gt, wal); else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) - cfl_gt_workarounds_init(i915, wal); + cfl_gt_workarounds_init(gt, wal); else if (IS_GEMINILAKE(i915)) - glk_gt_workarounds_init(i915, wal); + glk_gt_workarounds_init(gt, wal); else if (IS_KABYLAKE(i915)) - kbl_gt_workarounds_init(i915, wal); + kbl_gt_workarounds_init(gt, wal); else if (IS_BROXTON(i915)) - gen9_gt_workarounds_init(i915, wal); + gen9_gt_workarounds_init(gt, wal); else if (IS_SKYLAKE(i915)) - skl_gt_workarounds_init(i915, wal); + skl_gt_workarounds_init(gt, wal); else if (IS_HASWELL(i915)) - hsw_gt_workarounds_init(i915, wal); + hsw_gt_workarounds_init(gt, wal); else if (IS_VALLEYVIEW(i915)) - vlv_gt_workarounds_init(i915, wal); + vlv_gt_workarounds_init(gt, wal); else if (IS_IVYBRIDGE(i915)) - ivb_gt_workarounds_init(i915, wal); + ivb_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) == 6) - snb_gt_workarounds_init(i915, wal); + snb_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) == 5) - ilk_gt_workarounds_init(i915, wal); + ilk_gt_workarounds_init(gt, wal); else if (IS_G4X(i915)) - g4x_gt_workarounds_init(i915, wal); + g4x_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) == 4) - gen4_gt_workarounds_init(i915, wal); + gen4_gt_workarounds_init(gt, wal); else if (GRAPHICS_VER(i915) <= 8) ; else MISSING_CASE(GRAPHICS_VER(i915)); } -void intel_gt_init_workarounds(struct drm_i915_private *i915) +void intel_gt_init_workarounds(struct intel_gt *gt) { - struct i915_wa_list *wal = &i915->gt_wa_list; + struct i915_wa_list *wal = &gt->wa_list; wa_init_start(wal, "GT", "global"); - gt_init_workarounds(i915, wal); + gt_init_workarounds(gt, wal); wa_init_finish(wal); } @@ -1353,7 +1358,7 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) void intel_gt_apply_workarounds(struct intel_gt *gt) { - wa_list_apply(gt, &gt->i915->gt_wa_list); + wa_list_apply(gt, &gt->wa_list); } static bool wa_list_verify(struct intel_gt *gt, @@ -1385,7 +1390,7 @@ static bool wa_list_verify(struct intel_gt *gt, bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) { - return wa_list_verify(gt, &gt->i915->gt_wa_list, from); + return wa_list_verify(gt, &gt->wa_list, from); } __maybe_unused diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h index 15abb68b6c00..9beaab77c7f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h @@ -24,7 +24,7 @@ static inline void intel_wa_list_free(struct i915_wa_list *wal) void intel_engine_init_ctx_wa(struct intel_engine_cs *engine); int intel_engine_emit_ctx_wa(struct i915_request *rq); -void intel_gt_init_workarounds(struct drm_i915_private *i915); +void intel_gt_init_workarounds(struct intel_gt *gt); void intel_gt_apply_workarounds(struct intel_gt *gt); bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from); diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index e623ac45f4aa..962e91ba3be4 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -66,7 +66,7 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists) memset(lists, 0, sizeof(*lists)); wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); - gt_init_workarounds(gt->i915, &lists->gt_wa_list); + gt_init_workarounds(gt, &lists->gt_wa_list); wa_init_finish(&lists->gt_wa_list); for_each_engine(engine, gt, id) { diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 59fb4c710c8c..3cf61bead2f6 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -588,8 +588,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) pci_set_master(pdev); - intel_gt_init_workarounds(dev_priv); - /* On the 945G/GM, the chipset reports the MSI capability on the * integrated graphics even though the support isn't actually there * according to the published specs. It doesn't appear to function diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcd..93c23eaf3fc7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -998,8 +998,6 @@ struct drm_i915_private { struct list_head global_obj_list; - struct i915_wa_list gt_wa_list; - struct i915_frontbuffer_tracking fb_tracking; struct intel_atomic_helper { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 590efc8b0265..981e383d1a5d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1139,8 +1139,6 @@ void i915_gem_driver_release(struct drm_i915_private *dev_priv) { intel_gt_driver_release(&dev_priv->gt); - intel_wa_list_free(&dev_priv->gt_wa_list); - intel_uc_cleanup_firmwares(&dev_priv->gt.uc); i915_gem_drain_freed_objects(dev_priv); -- 2.33.0

4 3

[PATCH] agp: define proper stubs for empty helpers
by Arnd Bergmann 20 Sep '21

20 Sep '21

From: Arnd Bergmann <arnd(a)arndb.de> The empty unmap_page_from_agp() macro causes a warning when building with 'make W=1' on a couple of architectures: drivers/char/agp/generic.c: In function 'agp_generic_destroy_page': drivers/char/agp/generic.c:1265:28: error: suggest braces around empty body in an 'if' statement [-Werror=empty-body] 1265 | unmap_page_from_agp(page); Change the definitions to a 'do { } while (0)' construct to make these more reliable. Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- arch/parisc/include/asm/agp.h | 4 ++-- arch/powerpc/include/asm/agp.h | 4 ++-- arch/sparc/include/asm/agp.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/parisc/include/asm/agp.h b/arch/parisc/include/asm/agp.h index cb04470e63d0..14ae54cfd368 100644 --- a/arch/parisc/include/asm/agp.h +++ b/arch/parisc/include/asm/agp.h @@ -8,8 +8,8 @@ * */ -#define map_page_into_agp(page) /* nothing */ -#define unmap_page_from_agp(page) /* nothing */ +#define map_page_into_agp(page) do { } while (0) +#define unmap_page_from_agp(page) do { } while (0) #define flush_agp_cache() mb() /* GATT allocation. Returns/accepts GATT kernel virtual address. */ diff --git a/arch/powerpc/include/asm/agp.h b/arch/powerpc/include/asm/agp.h index b29b1186f819..6b6485c988dd 100644 --- a/arch/powerpc/include/asm/agp.h +++ b/arch/powerpc/include/asm/agp.h @@ -5,8 +5,8 @@ #include <asm/io.h> -#define map_page_into_agp(page) -#define unmap_page_from_agp(page) +#define map_page_into_agp(page) do {} while (0) +#define unmap_page_from_agp(page) do {} while (0) #define flush_agp_cache() mb() /* GATT allocation. Returns/accepts GATT kernel virtual address. */ diff --git a/arch/sparc/include/asm/agp.h b/arch/sparc/include/asm/agp.h index efe0d6a12e5a..2d0ff84cee3f 100644 --- a/arch/sparc/include/asm/agp.h +++ b/arch/sparc/include/asm/agp.h @@ -4,9 +4,9 @@ /* dummy for now */ -#define map_page_into_agp(page) -#define unmap_page_from_agp(page) -#define flush_agp_cache() mb() +#define map_page_into_agp(page) do { } while (0) +#define unmap_page_from_agp(page) do { } while (0) +#define flush_agp_cache() mb() /* GATT allocation. Returns/accepts GATT kernel virtual address. */ #define alloc_gatt_pages(order) \ -- 2.29.2

3 2

[PATCH libdrm 00/25] Update Tegra support
by Thierry Reding 20 Sep '21

20 Sep '21

From: Thierry Reding <treding(a)nvidia.com> Hi all, this is the userspace part of the kernel patches that were recently merged into drm-next: https://patchwork.freedesktop.org/series/92378/ The goal is to provide a userspace implementation of the UAPI exposed by the kernel and show its usage in some test programs that can also be used for basic sanity testing. More complete userspace implementations are available here: * https://github.com/cyndis/vaapi-tegra-driver * https://github.com/grate-driver/xf86-video-opentegra * https://github.com/grate-driver/grate Thierry Thierry Reding (25): tegra: Indent according to .editorconfig tegra: Remove unused IOCTL implementations tegra: Extract common buffer object allocation code tegra: Fix mmap() of GEM buffer objects tegra: Add flink helpers tegra: Add PRIME support helpers tegra: Make API more consistent tegra: Install tegra-openclose test tegra: Update for new UABI tegra: Include private.h in list of source files tegra: Add channel APIs tegra: Add job and push buffer APIs tegra: Add syncpoint APIs tests: tegra: Add helper library for tests tests: tegra: Add gr2d-fill test tests: tegra: Add syncpt-wait test tests: tegra: Add syncpoint timeout test tests: tegra: Add VIC support tests: tegra: Add VIC 3.0 support tests: tegra: Add VIC 4.0 support tests: tegra: Add VIC 4.1 support tests: tegra: Add VIC 4.2 support tests: tegra: Add VIC clear test tests: tegra: Add VIC blit test tests: tegra: Add VIC flip test include/drm/tegra_drm.h | 429 +++++++++++++++++++++++-- tegra/channel.c | 195 ++++++++++++ tegra/job.c | 187 +++++++++++ tegra/meson.build | 7 +- tegra/private.h | 85 ++++- tegra/pushbuf.c | 184 +++++++++++ tegra/syncpt.c | 101 ++++++ tegra/tegra-symbols.txt | 27 +- tegra/tegra.c | 392 ++++++++++++----------- tegra/tegra.h | 95 +++++- tests/tegra/.gitignore | 3 +- tests/tegra/drm-test-tegra.c | 147 +++++++++ tests/tegra/drm-test-tegra.h | 55 ++++ tests/tegra/drm-test.c | 248 +++++++++++++++ tests/tegra/drm-test.h | 72 +++++ tests/tegra/gr2d-fill.c | 146 +++++++++ tests/tegra/host1x.h | 34 ++ tests/tegra/meson.build | 88 +++++- tests/tegra/openclose.c | 52 +-- tests/tegra/syncpt-timeout.c | 163 ++++++++++ tests/tegra/syncpt-wait.c | 151 +++++++++ tests/tegra/vic-blit.c | 333 +++++++++++++++++++ tests/tegra/vic-clear.c | 173 ++++++++++ tests/tegra/vic-flip.c | 333 +++++++++++++++++++ tests/tegra/vic.c | 177 +++++++++++ tests/tegra/vic.h | 181 +++++++++++ tests/tegra/vic30.c | 509 +++++++++++++++++++++++++++++ tests/tegra/vic30.h | 439 ++++++++++++++++++++++++++ tests/tegra/vic40.c | 412 ++++++++++++++++++++++++ tests/tegra/vic40.h | 285 +++++++++++++++++ tests/tegra/vic41.c | 416 ++++++++++++++++++++++++ tests/tegra/vic41.h | 372 ++++++++++++++++++++++ tests/tegra/vic42.c | 423 +++++++++++++++++++++++++ tests/tegra/vic42.h | 597 +++++++++++++++++++++++++++++++++++ 34 files changed, 7248 insertions(+), 263 deletions(-) create mode 100644 tegra/channel.c create mode 100644 tegra/job.c create mode 100644 tegra/pushbuf.c create mode 100644 tegra/syncpt.c create mode 100644 tests/tegra/drm-test-tegra.c create mode 100644 tests/tegra/drm-test-tegra.h create mode 100644 tests/tegra/drm-test.c create mode 100644 tests/tegra/drm-test.h create mode 100644 tests/tegra/gr2d-fill.c create mode 100644 tests/tegra/host1x.h create mode 100644 tests/tegra/syncpt-timeout.c create mode 100644 tests/tegra/syncpt-wait.c create mode 100644 tests/tegra/vic-blit.c create mode 100644 tests/tegra/vic-clear.c create mode 100644 tests/tegra/vic-flip.c create mode 100644 tests/tegra/vic.c create mode 100644 tests/tegra/vic.h create mode 100644 tests/tegra/vic30.c create mode 100644 tests/tegra/vic30.h create mode 100644 tests/tegra/vic40.c create mode 100644 tests/tegra/vic40.h create mode 100644 tests/tegra/vic41.c create mode 100644 tests/tegra/vic41.h create mode 100644 tests/tegra/vic42.c create mode 100644 tests/tegra/vic42.h -- 2.32.0

3 27

[PATCH] staging: fbtft: add docs for fbtft_write_spi()
by Zachary Mayhew 20 Sep '21

20 Sep '21

Subject: [PATCH] staging: fbtft: add docs for fbtft_write_spi() This patch adds documentation for fbtft_write_spi() to make its calling context clear and explain what it does. Signed-off-by: Zachary Mayhew <zacklukem.kernel(a)gmail.com> --- drivers/staging/fbtft/fbtft-io.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/staging/fbtft/fbtft-io.c b/drivers/staging/fbtft/fbtft-io.c index de1904a443c2..985d7cf8c774 100644 --- a/drivers/staging/fbtft/fbtft-io.c +++ b/drivers/staging/fbtft/fbtft-io.c @@ -5,6 +5,19 @@ #include <linux/spi/spi.h> #include "fbtft.h" +/** + * fbtft_write_spi() - write data to current spi + * @par: Driver data including driver &struct spi_device + * @buf: Buffer to write to spi + * @len: Length of the buffer + * Context: can sleep + * + * Builds an &struct spi_transfer and &struct spi_message object based on the + * given @buf and @len. These are then used in a call to spi_sync() which will + * write to the spi. + * + * Return: zero on success or else a negative error code + */ int fbtft_write_spi(struct fbtft_par *par, void *buf, size_t len) { struct spi_transfer t = { -- 2.33.0

2 4

Re: BUG: unable to handle kernel paging request in drm_fb_helper_damage_work
by Borislav Petkov 20 Sep '21

20 Sep '21

On Mon, Sep 20, 2021 at 08:55:28PM +0800, Hao Sun wrote: > Hello, > > When using Healer to fuzz the latest Linux kernel, the following crash Your Healer thing - or whatever that next automated thing is which is trying to be smart - is not CCing the proper people: $ ./scripts/get_maintainer.pl -f drivers/gpu/drm/drm_fb_helper.c --no-rolestats Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Maxime Ripard <mripard(a)kernel.org> Thomas Zimmermann <tzimmermann(a)suse.de> David Airlie <airlied(a)linux.ie> Daniel Vetter <daniel(a)ffwll.ch> dri-devel(a)lists.freedesktop.org linux-kernel(a)vger.kernel.org I'll Cc them now but you should fix it. The syzcaller mails at least Cc more people and I'm sure you can figure out how to do that when you have the stack trace and get_maintainer.pl. > was triggered. > > HEAD commit: 4357f03d6611 Merge tag 'pm-5.15-rc2 > git tree: upstream > console output: > https://drive.google.com/file/d/13NUxvBLIswpoS8NOOAaq9PjOKgTYN19K/view?usp=… > kernel config: https://drive.google.com/file/d/1HKZtF_s3l6PL3OoQbNq_ei9CdBus-Tz0/view?usp=… > > Sorry, I don't have a reproducer for this crash, hope the symbolized > report can help. > If you fix this issue, please add the following tag to the commit: > Reported-by: Hao Sun <sunhao.th(a)gmail.com> > > BUG: unable to handle page fault for address: ffffc90003d79000 > #PF: supervisor read access in kernel mode > #PF: error_code(0x0000) - not-present page > PGD 8c00067 P4D 8c00067 PUD 8d63067 PMD 104409067 PTE 0 > Oops: 0000 [#1] PREEMPT SMP > CPU: 2 PID: 3032 Comm: kworker/2:2 Not tainted 5.15.0-rc1+ #19 > Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS > rel-1.12.0-59-gc9ba5276e321-prebuilt.qemu.org 04/01/2014 > Workqueue: events drm_fb_helper_damage_work > RIP: 0010:rep_movs arch/x86/lib/iomem.c:12 [inline] > RIP: 0010:memcpy_toio+0x48/0xa0 arch/x86/lib/iomem.c:57 > Code: 01 75 41 e8 4a 0d 04 ff 49 83 fc 01 76 0a e8 3f 0d 04 ff f6 c3 > 02 75 44 e8 35 0d 04 ff 4c 89 e1 48 89 df 48 89 ee 48 c1 e9 02 <f3> a5 > 41 f6 c4 02 74 02 66 a5 41 f6 c4 01 74 01 a4 5b 5d 41 5c e9 > RSP: 0018:ffffc9000088fda8 EFLAGS: 00010206 > RAX: 0000000000000000 RBX: ffffc90005aff000 RCX: 0000000000000100 > RDX: ffff88800f132240 RSI: ffffc90003d79000 RDI: ffffc90005b00000 > RBP: ffffc90003d78000 R08: 0000000000000001 R09: 0000000000000000 > R10: ffffc9000088fdc8 R11: 0000000000000004 R12: 0000000000001400 > R13: ffff888101fc7000 R14: 00000000000002ff R15: ffffc90003d78000 > FS: 0000000000000000(0000) GS:ffff88807dd00000(0000) knlGS:0000000000000000 > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > CR2: ffffc90003d79000 CR3: 000000010ea77000 CR4: 0000000000750ee0 > DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > PKRU: 55555554 > Call Trace: > dma_buf_map_memcpy_to include/linux/dma-buf-map.h:245 [inline] > drm_fb_helper_damage_blit_real drivers/gpu/drm/drm_fb_helper.c:388 [inline] > drm_fb_helper_damage_blit drivers/gpu/drm/drm_fb_helper.c:419 [inline] > drm_fb_helper_damage_work+0x30e/0x380 drivers/gpu/drm/drm_fb_helper.c:450 > process_one_work+0x359/0x850 kernel/workqueue.c:2297 > worker_thread+0x41/0x4d0 kernel/workqueue.c:2444 > kthread+0x178/0x1b0 kernel/kthread.c:319 > ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:295 > Modules linked in: > Dumping ftrace buffer: > (ftrace buffer empty) > CR2: ffffc90003d79000 > ---[ end trace e1f0ecb0884517c4 ]--- > RIP: 0010:rep_movs arch/x86/lib/iomem.c:12 [inline] > RIP: 0010:memcpy_toio+0x48/0xa0 arch/x86/lib/iomem.c:57 > Code: 01 75 41 e8 4a 0d 04 ff 49 83 fc 01 76 0a e8 3f 0d 04 ff f6 c3 > 02 75 44 e8 35 0d 04 ff 4c 89 e1 48 89 df 48 89 ee 48 c1 e9 02 <f3> a5 > 41 f6 c4 02 74 02 66 a5 41 f6 c4 01 74 01 a4 5b 5d 41 5c e9 > RSP: 0018:ffffc9000088fda8 EFLAGS: 00010206 > RAX: 0000000000000000 RBX: ffffc90005aff000 RCX: 0000000000000100 > RDX: ffff88800f132240 RSI: ffffc90003d79000 RDI: ffffc90005b00000 > RBP: ffffc90003d78000 R08: 0000000000000001 R09: 0000000000000000 > R10: ffffc9000088fdc8 R11: 0000000000000004 R12: 0000000000001400 > R13: ffff888101fc7000 R14: 00000000000002ff R15: ffffc90003d78000 > FS: 0000000000000000(0000) GS:ffff88807dd00000(0000) knlGS:0000000000000000 > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > CR2: ffffc90003d79000 CR3: 000000010ea77000 CR4: 0000000000750ee0 > DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > PKRU: 55555554 > ---------------- > Code disassembly (best guess): > 0: 01 75 41 add %esi,0x41(%rbp) > 3: e8 4a 0d 04 ff callq 0xff040d52 > 8: 49 83 fc 01 cmp $0x1,%r12 > c: 76 0a jbe 0x18 > e: e8 3f 0d 04 ff callq 0xff040d52 > 13: f6 c3 02 test $0x2,%bl > 16: 75 44 jne 0x5c > 18: e8 35 0d 04 ff callq 0xff040d52 > 1d: 4c 89 e1 mov %r12,%rcx > 20: 48 89 df mov %rbx,%rdi > 23: 48 89 ee mov %rbp,%rsi > 26: 48 c1 e9 02 shr $0x2,%rcx > * 2a: f3 a5 rep movsl %ds:(%rsi),%es:(%rdi) <-- > trapping instruction > 2c: 41 f6 c4 02 test $0x2,%r12b > 30: 74 02 je 0x34 > 32: 66 a5 movsw %ds:(%rsi),%es:(%rdi) > 34: 41 f6 c4 01 test $0x1,%r12b > 38: 74 01 je 0x3b > 3a: a4 movsb %ds:(%rsi),%es:(%rdi) > 3b: 5b pop %rbx > 3c: 5d pop %rbp > 3d: 41 5c pop %r12 > 3f: e9 .byte 0xe9 -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette

1 0

[PATCH] drm/radeon: fix uninitialized bool variable
by Zhiwei Yang 20 Sep '21

20 Sep '21

The bool variable detected_hpd_without_ddc in struct radeon_connector is uninitialized when first used, that may cause unnecessary ddc ops. Make it as false when a new connector is alloced. Signed-off-by: Zhiwei Yang <yangzhiwei(a)uniontech.com> --- drivers/gpu/drm/radeon/radeon_connectors.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index fe12d9d91d7a..c1987a66373f 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -1866,6 +1866,7 @@ radeon_add_atom_connector(struct drm_device *dev, bool shared_ddc = false; bool is_dp_bridge = false; bool has_aux = false; + bool detected_hpd_without_ddc = false; if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; @@ -1923,6 +1924,7 @@ radeon_add_atom_connector(struct drm_device *dev, radeon_connector->shared_ddc = shared_ddc; radeon_connector->connector_object_id = connector_object_id; radeon_connector->hpd = *hpd; + radeon_connector->detected_hpd_without_ddc = detected_hpd_without_ddc; radeon_connector->router = *router; if (router->ddc_valid || router->cd_valid) { @@ -2384,6 +2386,7 @@ radeon_add_legacy_connector(struct drm_device *dev, struct radeon_connector *radeon_connector; struct i2c_adapter *ddc = NULL; uint32_t subpixel_order = SubPixelNone; + bool detected_hpd_without_ddc = false; if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; @@ -2414,6 +2417,7 @@ radeon_add_legacy_connector(struct drm_device *dev, radeon_connector->devices = supported_device; radeon_connector->connector_object_id = connector_object_id; radeon_connector->hpd = *hpd; + radeon_connector->detected_hpd_without_ddc = detected_hpd_without_ddc; switch (connector_type) { case DRM_MODE_CONNECTOR_VGA: -- 2.20.1

3 2

[PATCH v4 0/6] drm/i915: Suspend / resume backup- and restore of LMEM.
by Thomas Hellström 20 Sep '21

20 Sep '21

Implement backup and restore of LMEM during suspend / resume. What complicates things a bit is handling of pinned LMEM memory during suspend and the fact that we might be dealing with unmappable LMEM in the future, which makes us want to restrict the number of pinned objects that need memcpy resume. The first two patches are prereq patches implementing object content copy and a generic means of iterating through all objects in a region. The third patch adds the backup / recover / restore functions and the two last patches deal with restricting the number of objects we need to use memcpy for. v2: - Some polishing of patch 4/6, see patch commit message for details (Chris Wilson) - Rework of patch 3/6. v3: - Comment changes in patch 2/6 (Matthew Auld) - A number of changes to patch 3/6, see commit message. - Slightly reword comment in patch 5/6. (Matthew Auld). v4: - Various cleanups, among other things reworking the ttm / lmem backup- and resume interfaces somewhat. Thomas Hellström (6): drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects drm/i915/gem: Implement a function to process all gem objects of a region drm/i915 Implement LMEM backup and restore for suspend / resume drm/i915/gt: Register the migrate contexts with their engines drm/i915: Don't back up pinned LMEM context images and rings during suspend drm/i915: Reduce the number of objects subject to memcpy recover drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 21 +- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 91 ++++++++ drivers/gpu/drm/i915/gem/i915_gem_pm.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++ drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++ drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 99 +++++++-- drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 14 ++ drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 206 ++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 26 +++ .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 8 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 + drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 ++ drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 + .../drm/i915/gt/intel_execlists_submission.c | 2 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 3 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 +- drivers/gpu/drm/i915/gt/intel_ring.c | 3 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 3 + drivers/gpu/drm/i915/gt/mock_engine.c | 2 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +- drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +- 37 files changed, 644 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h -- 2.31.1

1 6

[PATCH i-g-t v11 00/15] Introduce PXP Test
by Alan Previn 20 Sep '21

20 Sep '21

This series adds gem_pxp tests for the new PXP subsystem currently being reviewed at https://patchwork.freedesktop.org/series/90504/. This series currently includes 4 groups of tests addressing the features and restrictions described by Daniele's series : 1. test i915 interfaces for allocation of protected bo's and contexts and enforcement of UAPI rule disallowing the modification of parameters after it's been created. 2. verify PXP subsystem protected sessions generate encrypted content on protected output buffers and decrypt protected inputs buffers. 3. verify i915 PXP auto-teardown succeeds on suspend-resume cycles and gem-exec of stale protected assets fail. Ensure protected-contexts adhere to stricter invalidation enforcement upon teardown event. 4. Ensure that display plane decryption works as expected with protected buffers. NOTE: This series is on the tenth revision. All R-v-b's have been received except UAPI patch which will be dropped at merge time (after kernel patches gets merged and igt's drm UAPI gets sync'd). Changes from prior rev1 to now: v11: - When detecting hw support, retry pxp context creation multiple times a timeout as per HW SLA. - initialize bo or ctx handles to zero before calling creation ioctl wrapper. v10: - In patch #2, reuse existing gem_create_ext wrapper. - In patch #10, kernel side changed the debugfs file name (but no difference in behavior / usage). - Removed patch #14 from Rev9 as decision on kernel side was to drop the usage of RESET_STATS IOCTL to track invalidated pxp contexts. v9: - Remove patch #2 from rev7 as it was duplicating an existing ioctl wrapper helper - Fix the false-negative warnings when triggering auto-suspend-resume (remove checking if we are suspending after the system has already resumed). v8: - Nothing - mistaken detection from patchwork v7: - In prior rev, Patches #11->13 was testing expected results from calling gem_execbuf with stale pxp-context, pxp-buffer or combinations of them (including an opt-out usage). All of them used a single suspend-resume power state cycles to trigger the PXP teardown event. These patches have been combined into patch #14 that continues to carry the prior rev Rvb. - In its place, the new patches of #11->#13 do the identical set of tests as before (results from gem_execbuf with various combinations of stale pxp context and buffer), but this time using a debugfs file handle that triggers the same code path taken when the HW triggers the pxp teardown. That said, the code is nearly identical as v6 but I did not keep the Rvb's. - In patch #15, RESET_STAT now reports invalidated / banned pxp contexts via the existing batch_active's lost count. v6: - Addressed rev5 review comments for patch #1, #7, #14 and #17. - For #17, I'm using Rodrigo's Rv-b because offline discussions concluded that we couldn't use those test sequences with HDCP and so it was removed it. - Added Rv-b into all patches that received it. - Modified the test requirement from a list of device ids to checking if runtime PXP interface succeeds due to kernel's build config dependency. v5: - Addressed all rev4 review comments. No changes to overall flow and logic compared to the last rev. v4: - Addressed all rev3 review comments. NOTE: that all test cases and code logic are the same but a decent amount of refactoring has occured due to address v3 comments to break out subtests into separate functions while combining certain checks into the same function to reduce test time by minimizing number of suspend-resume power cycles. v3: - Addressed all rev2 review comments. - In line with one of the rev2 comments, a thorough fixup of all line-breaks in function calls was made for a more consistent styling. - Rebased on igt upstream repo and updated to latest kernel UAPI that added GEM_CREATE_EXT. v2: - Addressed all rev1 review comments except these: 1.Chris Wilson : "...have the caller do 1-3 once for its protected context. Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it should be reversible.". - This couldn't be implemented because [1] HW needs different instruction sequences for enabling/disabling PXP depending on the engine class and [2] the pair of "pxp-enable" and "pxp- disable" instructions need to be contained within the same batch that is dispatched to the hardware. That said, implementing internal intel_batchbuffer funtionality for this would conflict with how rendercopy_gen9 uses batch buffer memory by repositioing the pointer and consuming unused portions of the batch buffer as 3d state offsets that batchbuffer has no visibility. - Added these additional subtests: 1. verify that buffer sharing works across testing pxp context. 2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT. 3. verify display plane decryption of protected buffers. Alan Previn (14): Add PXP UAPI support in i915_drm.h Add basic PXP testing of buffer and context alloc Perform a regular 3d copy as a control checkpoint Add PXP attribute support in batchbuffer and buffer_ops libs Add MI_SET_APPID instruction definition Enable protected session cmd in gen12_render_copyfunc Add subtest to copy raw source to protected dest Add test where both src and dest are protected Verify PXP teardown occurred through suspend-resume Verify execbuf fails with stale PXP context after teardown Verify execbuf fails with stale PXP buffer after teardown Verify execbuf ok with stale PXP buf in opt-out use Verify execution behavior with stale PXP assets through suspend-resume Verify protected surfaces are dma buffer sharable Karthik B S (1): tests/i915_pxp: CRC validation for display tests. lib/i915/i915_drm_local.h | 102 +++ lib/intel_batchbuffer.c | 23 +- lib/intel_batchbuffer.h | 31 + lib/intel_bufops.h | 15 + lib/intel_reg.h | 8 + lib/rendercopy_gen9.c | 57 ++ tests/i915/gem_pxp.c | 1283 +++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 8 files changed, 1519 insertions(+), 1 deletion(-) create mode 100644 tests/i915/gem_pxp.c -- 2.25.1

2 1

[PATCH v2 00/12] Context types
by Gurchetan Singh 20 Sep '21

20 Sep '21

Version 2 of context types: https://lists.oasis-open.org/archives/virtio-dev/202108/msg00141.html Changes since RFC: * le32 info --> {u8 ring_idx + u8 padding[3]). * Max rings is now 64. Changes since v1: * Document plan regarding context types + display combinations that need implicit sync in patch 9 commit message. Anthoine Bourgeois (2): drm/virtio: implement context init: probe for feature drm/virtio: implement context init: support init ioctl Gurchetan Singh (10): virtio-gpu api: multiple context types with explicit initialization drm/virtgpu api: create context init feature drm/virtio: implement context init: track valid capabilities in a mask drm/virtio: implement context init: track {ring_idx, emit_fence_info} in virtio_gpu_fence drm/virtio: implement context init: plumb {base_fence_ctx, ring_idx} to virtio_gpu_fence_alloc drm/virtio: implement context init: stop using drv->context when creating fence drm/virtio: implement context init: allocate an array of fence contexts drm/virtio: implement context init: handle VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK drm/virtio: implement context init: add virtio_gpu_fence_event drm/virtio: implement context init: advertise feature to userspace drivers/gpu/drm/virtio/virtgpu_debugfs.c | 1 + drivers/gpu/drm/virtio/virtgpu_drv.c | 44 ++++- drivers/gpu/drm/virtio/virtgpu_drv.h | 28 +++- drivers/gpu/drm/virtio/virtgpu_fence.c | 30 +++- drivers/gpu/drm/virtio/virtgpu_ioctl.c | 195 +++++++++++++++++++++-- drivers/gpu/drm/virtio/virtgpu_kms.c | 26 ++- drivers/gpu/drm/virtio/virtgpu_plane.c | 3 +- drivers/gpu/drm/virtio/virtgpu_vq.c | 19 +-- include/uapi/drm/virtgpu_drm.h | 27 ++++ include/uapi/linux/virtio_gpu.h | 18 ++- 10 files changed, 355 insertions(+), 36 deletions(-) -- 2.33.0.464.g1972c5931b-goog

3 14

[PATCH] drm/amd/display: fix empty debug macros
by Arnd Bergmann 20 Sep '21

20 Sep '21

From: Arnd Bergmann <arnd(a)arndb.de> Using an empty macro expansion as a conditional expression produces a W=1 warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c: In function 'dce_aux_transfer_with_retries': drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:775:156: error: suggest braces around empty body in an 'if' statement [-Werror=empty-body] 775 | "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER"); | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:783:155: error: suggest braces around empty body in an 'if' statement [-Werror=empty-body] 783 | "dce_aux_transfer_with_retries: AUX_RET_SUCCESS: AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK"); | ^ Expand it to "do { } while (0)" instead to make the expression more robust and avoid the warning. Fixes: 56aca2309301 ("drm/amd/display: Add AUX I2C tracing.") Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index e14f99b4b0c3..3c3347341103 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -42,7 +42,7 @@ #define DC_LOGGER \ engine->ctx->logger -#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0) #define IS_DC_I2CAUX_LOGGING_ENABLED() (false) #define LOG_FLAG_Error_I2cAux LOG_ERROR #define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX @@ -76,7 +76,7 @@ enum { #define DEFAULT_AUX_ENGINE_MULT 0 #define DEFAULT_AUX_ENGINE_LENGTH 69 -#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0) static void release_engine( struct dce_aux *engine) -- 2.29.2

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dri-devel September 2021