dri-devel September 2021

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817 discussions

[RFC v2 00/22] Add Support for Plane Color Lut and CSC features
by Uma Shankar 03 Feb '22

03 Feb '22

This is how a typical display color hardware pipeline looks like: +-------------------------------------------+ | RAM | | +------+ +---------+ +---------+ | | | FB 1 | | FB 2 | | FB N | | | +------+ +---------+ +---------+ | +-------------------------------------------+ | Plane Color Hardware Block | +--------------------------------------------+ | +---v-----+ +---v-------+ +---v------+ | | | Plane A | | Plane B | | Plane N | | | | DeGamma | | Degamma | | Degamma | | | +---+-----+ +---+-------+ +---+------+ | | | | | | | +---v-----+ +---v-------+ +---v------+ | | |Plane A | | Plane B | | Plane N | | | |CSC/CTM | | CSC/CTM | | CSC/CTM | | | +---+-----+ +----+------+ +----+-----+ | | | | | | | +---v-----+ +----v------+ +----v-----+ | | | Plane A | | Plane B | | Plane N | | | | Gamma | | Gamma | | Gamma | | | +---+-----+ +----+------+ +----+-----+ | | | | | | +--------------------------------------------+ +------v--------------v---------------v-------| || || || Pipe Blender || +--------------------+------------------------+ | | | | +-----------v----------+ | | | Pipe DeGamma | | | | | | | +-----------+----------+ | | | Pipe Color | | +-----------v----------+ Hardware | | | Pipe CSC/CTM | | | | | | | +-----------+----------+ | | | | | +-----------v----------+ | | | Pipe Gamma | | | | | | | +-----------+----------+ | | | | +---------------------------------------------+ | v Pipe Output This patch series adds properties for plane color features. It adds properties for degamma used to linearize data and CSC used for gamut conversion. It also includes Gamma support used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to another, one color space to another etc. Userspace can take smart blending decisions and utilize these hardware supported plane color features to get accurate color profile. The same can help in consistent color quality from source to panel taking advantage of advanced color features in hardware. These patches add the property interfaces and enable helper functions. This series adds Intel's XE_LPD hw specific plane gamma feature. We can build up and add other platform/hardware specific implementation on top of this series. Credits: Special mention and credits to Ville Syrjala for coming up with a design for this feature and inputs. This series is based on his original design and idea. Note: Userspace support for this new UAPI will be done on Chrome in alignment with weston and general opensource community. Discussion ongoing with Harry Wentland, Pekka and community on color pipeline and UAPI design. Harry's RFC below: https://patchwork.freedesktop.org/series/89506/ We need to converge on a common UAPI interface which caters to all the modern color hardware pipelines. ToDo: State readout for this feature will be added next. v2: Added UAPI description and added change in the rfc section of kernel Documentation folder Uma Shankar (22): drm: RFC for Plane Color Hardware Pipeline drm: Add Enhanced Gamma and color lut range attributes drm: Add Plane Degamma Mode property drm: Add Plane Degamma Lut property drm/i915/xelpd: Define Degamma Lut range struct for HDR planes drm/i915/xelpd: Add register definitions for Plane Degamma drm/i915/xelpd: Enable plane color features drm/i915/xelpd: Add color capabilities of SDR planes drm/i915/xelpd: Program Plane Degamma Registers drm/i915/xelpd: Add plane color check to glk_plane_color_ctl drm/i915/xelpd: Initialize plane color features drm/i915/xelpd: Load plane color luts from atomic flip drm: Add Plane CTM property drm: Add helper to attach Plane ctm property drm/i915/xelpd: Define Plane CSC Registers drm/i915/xelpd: Enable Plane CSC drm: Add Plane Gamma Mode property drm: Add Plane Gamma Lut property drm/i915/xelpd: Define and Initialize Plane Gamma Lut range drm/i915/xelpd: Add register definitions for Plane Gamma drm/i915/xelpd: Program Plane Gamma Registers drm/i915/xelpd: Enable plane gamma Documentation/gpu/drm-kms.rst | 90 +++ Documentation/gpu/rfc/drm_color_pipeline.rst | 167 ++++++ drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 12 + drivers/gpu/drm/drm_atomic_uapi.c | 38 ++ drivers/gpu/drm/drm_color_mgmt.c | 177 +++++- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 + .../gpu/drm/i915/display/intel_atomic_plane.h | 2 + drivers/gpu/drm/i915/display/intel_color.c | 513 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_color.h | 2 + .../drm/i915/display/skl_universal_plane.c | 15 +- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 176 +++++- include/drm/drm_mode_object.h | 2 +- include/drm/drm_plane.h | 81 +++ include/uapi/drm/drm_mode.h | 58 ++ 16 files changed, 1337 insertions(+), 6 deletions(-) create mode 100644 Documentation/gpu/rfc/drm_color_pipeline.rst -- 2.26.2

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[PATCH v3] drm/dp: Add Additional DP2 Headers
by Fangzhi Zuo 03 Feb '22

03 Feb '22

Include FEC, DSC, Link Training related headers. Change since v2 - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT Signed-off-by: Fangzhi Zuo <Jerry.Zuo(a)amd.com> --- This patch is based on top of the other DP2.0 work in "drm/dp: add LTTPR DP 2.0 DPCD addresses" --- include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..a1df35aa6e68 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -453,6 +453,7 @@ struct drm_panel; # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ @@ -537,6 +538,9 @@ struct drm_panel; #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 +/* DFP Capability Extension */ +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -688,6 +692,7 @@ struct drm_panel; #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ # define DP_DECOMPRESSION_EN (1 << 0) +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE BIT(0) @@ -743,6 +748,7 @@ struct drm_panel; # define DP_RECEIVE_PORT_0_STATUS (1 << 0) # define DP_RECEIVE_PORT_1_STATUS (1 << 1) # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 @@ -865,6 +871,8 @@ struct drm_panel; # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 # define DP_PHY_TEST_PATTERN_CP2520 0x5 +#define DP_PHY_SQUARE_PATTERN 0x249 + #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 @@ -1109,6 +1117,18 @@ struct drm_panel; #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 + +/* DSC Extended Capability Branch Total DSC Resources */ +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +# define DP_DSC_DECODER_COUNT_SHIFT 5 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 + /* Protocol Converter Extension */ /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ #define DP_CEC_TUNNELING_CAPABILITY 0x3000 -- 2.25.1

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[PARCH v2 0/7] drm/msm/dpu: merge dpu_core_irq into dpu_hw_interrupts
by Dmitry Baryshkov 01 Feb '22

01 Feb '22

This patch series reworks DPU's irq handling code by merging dpu_core_irq into dpu_hw_intr, reworking/dropping irq-related helpers and wrappers, etc. Changes since v1: - Rework callbacks registration code to allow just single callback per interrupt. This removes need to do any memory allocation in reg/unreg code and simplifies handling of interrupts. The following changes since commit 7e0230fd096c03e9662e66150f951075dd16e496: drm/msm/mdp5: provide dynamic bandwidth management (2021-06-17 09:51:44 -0700) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git dpu-irq-simplify-5 for you to fetch changes up to b2ae835c61b2065037c55b4596e16053484f4904: drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx (2021-06-18 01:12:04 +0300) ---------------------------------------------------------------- Dmitry Baryshkov (7): drm/msm/dpu: squash dpu_core_irq into dpu_hw_interrupts drm/msm/dpu: don't clear IRQ register twice drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr drm/msm/dpu: allow just single IRQ callback drm/msm/dpu: remove extra wrappers around dpu_core_irq drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 256 -------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 30 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 111 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 66 +----- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 99 ++++---- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 56 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 264 +++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 96 +------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 27 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 25 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 51 ++-- 12 files changed, 334 insertions(+), 748 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c

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[Bug 214197] New: [Asus G713QY] RX6800M not usable after exiting Vulkan application
by bugzilla-daemon＠bugzilla.kernel.org 30 Jan '22

30 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=214197 Bug ID: 214197 Summary: [Asus G713QY] RX6800M not usable after exiting Vulkan application Product: Drivers Version: 2.5 Kernel Version: 5.13.13 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: velemas(a)gmail.com Regression: No Asus ROG Strix G17 Advantage Edition (G713QY) has hybrid-graphics with dGPU RX6800M. After exiting any Vulkan application, it becomes unusable. Vulkaninfo sees dGPU before Vulkan app and does not see RX6800M after. After Vulkan app close, dmesg reports: [ 154.385749] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available [ 154.401405] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available [ 154.401409] amdgpu 0000:03:00.0: amdgpu: SMU is resuming... [ 159.038150] amdgpu 0000:03:00.0: amdgpu: message: RunDcBtc (54) param: 0x00000000 is timeout (no response) [ 159.038154] amdgpu 0000:03:00.0: amdgpu: Failed to setup smc hw! [ 159.038156] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <smu> failed -62 [ 159.038220] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_resume failed (-62). Using amdgpu.runpm=0 parameter fixes the issue. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

2 9

[Bug 204611] New: amdgpu error scheduling IBs when waking from sleep
by bugzilla-daemon＠bugzilla.kernel.org 30 Jan '22

30 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=204611 Bug ID: 204611 Summary: amdgpu error scheduling IBs when waking from sleep Product: Drivers Version: 2.5 Kernel Version: 5.2.9 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: tones111(a)hotmail.com Regression: No Created attachment 284485 --> https://bugzilla.kernel.org/attachment.cgi?id=284485&action=edit journalctl: amdgpu lockup on resume from sleep. My system locks up when trying to wake from sleep (open lid). The screen remains black and is unresponsive to keyboard/mouse input. I'm able to ssh from another machine and have attached the output from journalctl -b. The log shows scrolling errors... kernel: [drm:amdgpu_job_run [amdgpu]] *ERROR* Error scheduling IBs (-22) kernel: amdgpu 0000:05:00.0: couldn't schedule ib on ring <gfx> This is a Lenovo E585 laptop with an AMD R5 2500U APU. -- You are receiving this mail because: You are watching the assignee of the bug.

2 15

[PATCH v3] drm/ast: Don't check new mode if CRTC is being disabled
by Thomas Zimmermann 24 Jan '22

24 Jan '22

Suspending failed because there's no mode if the CRTC is being disabled. Early-out in this case. This fixes runtime PM for ast. v3: * fixed commit message v2: * added Tested-by/Reported-by tags * added Fixes tags and CC (Sam) * improved comment Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Reported-by: Cary Garrett <cogarre(a)gmail.com> Tested-by: Cary Garrett <cogarre(a)gmail.com> Fixes: b48e1b6ffd28 ("drm/ast: Add CRTC helpers for atomic modesetting") Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Gerd Hoffmann <kraxel(a)redhat.com> Cc: Dave Airlie <airlied(a)redhat.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: <stable(a)vger.kernel.org> # v5.6+ --- drivers/gpu/drm/ast/ast_mode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 7a9f20a2fd303..0cbbb21edb4e1 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -801,6 +801,9 @@ static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } + if (!state->enable) + return 0; /* no mode checks if CRTC is being disabled */ + ast_state = to_ast_crtc_state(state); format = ast_state->format; -- 2.26.0

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[Bug 211277] New: sometimes crash at s2ram-wake (Ryzen 3500U): amdgpu, drm, commit_tail, amdgpu_dm_atomic_commit_tail
by bugzilla-daemon＠bugzilla.kernel.org 23 Jan '22

23 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=211277 Bug ID: 211277 Summary: sometimes crash at s2ram-wake (Ryzen 3500U): amdgpu, drm, commit_tail, amdgpu_dm_atomic_commit_tail Product: Drivers Version: 2.5 Kernel Version: 5.10.4 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: kolAflash(a)kolahilft.de Regression: No I'm currently on Debian-11-Testing (Bullseye). And since a few weeks the system sometimes (not always) doesn't wake up from suspend. Most of the time suspend works. But about 1 in 10 times it crashes. I attached /var/log/kern.log which holds plenty of information about the crash. Looks like the crash happened in amdgpu_dm.c:7273 (amdgpu_dm_atomic_commit_tail, Linux-5.10.4). I'm pretty sure this behavior didn't appeared a few month before. So I guess a recent change is causing it. This may either be: 1. an updated package by Debian-Testing Indeed I'm pretty sure the problem didn't appeared before Linux-5.9. So maybe this is being caused by a change between Linux-5.8 and Linux-5.9. I'll try to test going back to Linux-5.8 in the next days. 2. a BIOS update In November 2020 I installed the BIOS update sp110770.exe. Before I was using sp107599.exe. You can find the BIOS history attached. I'll also see if I can test a BIOS downgrade in the next days. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI
by Neil Armstrong 20 Jan '22

20 Jan '22

The Amlogic AXG SoC family has a downgraded VPU with the following changes : - Only a single OSD plane, no overlay video plane - The primary plane doesn't support HW scaling - The pixels are read directly from DDR without any Canvas module - Doesn't support HDMI or CVBS - Ouputs only with ENCL encoder to a DPI-to-DSI Synopsys DW-MIPI-DSI transceiver The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock is derived and feeds the ENCL encoder and the VIU pixel reader. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. Neil Armstrong (6): dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings drm/meson: add support for VPU found in AXG SoCs drm/meson: venc: add ENCL encoder setup for MIPI-DSI output drm/meson: remove useless recursive components matching drm/meson: add support for MIPI-DSI transceiver .../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++ .../bindings/display/amlogic,meson-vpu.yaml | 36 +- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_crtc.c | 8 +- drivers/gpu/drm/meson/meson_drv.c | 163 ++--- drivers/gpu/drm/meson/meson_drv.h | 10 +- drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++ drivers/gpu/drm/meson/meson_plane.c | 74 ++- drivers/gpu/drm/meson/meson_registers.h | 1 + drivers/gpu/drm/meson/meson_venc.c | 230 ++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_viu.c | 50 +- drivers/gpu/drm/meson/meson_vpp.c | 6 +- drivers/gpu/drm/meson/meson_vpp.h | 2 + 15 files changed, 1176 insertions(+), 95 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c -- 2.22.0

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[Bug 213561] New: [bisected] AMD GPU can no longer idle state after commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3
by bugzilla-daemon＠bugzilla.kernel.org 20 Jan '22

20 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=213561 Bug ID: 213561 Summary: [bisected] AMD GPU can no longer idle state after commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3 Product: Drivers Version: 2.5 Kernel Version: 5.13rc7 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: untaintableangel(a)hotmail.co.uk Regression: No Nature of the problem: RX 5700 is unable to enter low power state at idle (see below for usual behaviour) Sensors at idle prior to the commit: amdgpu-pci-0f00 Adapter: PCI adapter vddgfx: 775.00 mV fan1: 0 RPM (min = 0 RPM, max = 3200 RPM) edge: +48.0°C (crit = +100.0°C, hyst = -273.1°C) (emerg = +105.0°C) junction: +48.0°C (crit = +110.0°C, hyst = -273.1°C) (emerg = +115.0°C) mem: +52.0°C (crit = +105.0°C, hyst = -273.1°C) (emerg = +110.0°C) power1: 8.00 W (cap = 165.00 W) After the commit, the lowest is: amdgpu-pci-0f00 Adapter: PCI adapter vddgfx: 1.03 V fan1: 0 RPM (min = 0 RPM, max = 3200 RPM) edge: +54.0°C (crit = +100.0°C, hyst = -273.1°C) (emerg = +105.0°C) junction: +56.0°C (crit = +110.0°C, hyst = -273.1°C) (emerg = +115.0°C) mem: +52.0°C (crit = +105.0°C, hyst = -273.1°C) (emerg = +110.0°C) power1: 31.00 W (cap = 165.00 W) This problem wasn't present in rc6 but is present in 5.13rc7 and bisects to: 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3 is the first bad commit commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3 Author: Yifan Zhang <yifan1.zhang(a)amd.com> Date: Thu Jun 10 10:10:07 2021 +0800 drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell. If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <yifan1.zhang(a)amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling(a)amd.com> Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Cc: stable(a)vger.kernel.org The device is a Sapphire Pulse RX5700 and this problem is seen even with one monitor set at 60Hz. GPU: 0f:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 [Radeon RX 5600 OEM/5600 XT / 5700/5700 XT] [1002:731f] (rev c4) -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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[Bug 204559] New: amdgpu: kernel oops with constant gpu resets while using mpv
by bugzilla-daemon＠bugzilla.kernel.org 17 Jan '22

17 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=204559 Bug ID: 204559 Summary: amdgpu: kernel oops with constant gpu resets while using mpv Product: Drivers Version: 2.5 Kernel Version: 5.2.7 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: shoegaze(a)tutanota.com Regression: No Created attachment 284335 --> https://bugzilla.kernel.org/attachment.cgi?id=284335&action=edit oops.txt While watching a video using mpv (default config) the system will hang eventually - this is actually a kernel oops that happens after lots of GPU resets every second or so (in the span of ~5 minutes; it seems to be alright in the beginning): > Aug 12 00:46:49 mashedpotato kernel: [drm] UVD and UVD ENC initialized > successfully. > Aug 12 00:46:49 mashedpotato kernel: [drm] VCE initialized successfully. > Aug 12 00:46:56 mashedpotato kernel: amdgpu 0000:01:00.0: GPU pci config > reset > Aug 12 00:46:59 mashedpotato kernel: [drm] PCIE GART of 256M enabled (table > at 0x000000F400000000). This block of warnings repeats itself many times and then it is this error: > Aug 12 00:52:20 mashedpotato kernel: amdgpu 0000:01:00.0: > [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring sdma0 test failed (-110) > Aug 12 00:52:20 mashedpotato kernel: [drm:amdgpu_device_resume [amdgpu]] > *ERROR* resume of IP block <sdma_v3_0> failed -110 > Aug 12 00:52:20 mashedpotato kernel: [drm:amdgpu_device_resume [amdgpu]] > *ERROR* amdgpu_device_ip_resume failed (-110). > Aug 12 00:52:25 mashedpotato kernel: BUG: kernel NULL pointer dereference, > address: 0000000000000000 > Aug 12 00:52:25 mashedpotato kernel: #PF: supervisor instruction fetch in > kernel mode > Aug 12 00:52:25 mashedpotato kernel: #PF: error_code(0x0010) - not-present > page In the end it is a kernel oops, log is in the attachment. The system is only recoverable via a hard reset afterwards, though the sound from a video keeps playing just fine. My system is a ASUS laptop, TUF FX505-DY with the latest BIOS. lspci: > 00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Root > Complex > 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 IOMMU > 00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models > 00h-1fh) PCIe Dummy Host Bridge > 00:01.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 PCIe GPP > Bridge [6:0] > 00:01.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 PCIe GPP > Bridge [6:0] > 00:01.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 PCIe GPP > Bridge [6:0] > 00:01.4 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 PCIe GPP > Bridge [6:0] > 00:08.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models > 00h-1fh) PCIe Dummy Host Bridge > 00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Internal > PCIe GPP Bridge 0 to Bus A > 00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev > 61) > 00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev > 51) > 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 0 > 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 1 > 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 2 > 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 3 > 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 4 > 00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 5 > 00:18.6 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 6 > 00:18.7 Host bridge: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 Device > 24: Function 7 > 01:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Baffin > [Radeon RX 460/560D / Pro 450/455/460/555/555X/560/560X] (rev e5) > 02:00.0 Non-Volatile memory controller: Kingston Technology Company, Inc. > Device 5008 (rev 01) > 03:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8821CE > 802.11ac PCIe Wireless Network Adapter > 04:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. > RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) > 05:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] > Picasso (rev c2) > 05:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] > Raven/Raven2/Fenghuang HDMI/DP Audio Controller > 05:00.2 Encryption controller: Advanced Micro Devices, Inc. [AMD] Family 17h > (Models 10h-1fh) Platform Security Processor > 05:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Raven USB 3.1 > 05:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Raven USB 3.1 > 05:00.6 Audio device: Advanced Micro Devices, Inc. [AMD] Family 17h (Models > 10h-1fh) HD Audio Controller I have amdgpu.gpu_reset=1 in my kernel commandline as I want to figure out another issue - sometimes the system hangs after locking and disabling screen, and I guess it is GPU reset-related. -- You are receiving this mail because: You are watching the assignee of the bug.

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dri-devel September 2021