dri-devel September 2021

dri-devel@lists.freedesktop.org

348 participants
817 discussions

[PATCH 00/14] drm/hdcp: Pull HDCP auth/exchange/check into
by Sean Paul 14 Sep '21

14 Sep '21

From: Sean Paul <seanpaul(a)chromium.org> Hello, This patchset pulls the HDCP protocol auth/exchange/check logic out from i915 into a HDCP helper library which drivers can use to implement the proper protocol and UAPI interactions for achieving HDCP. Originally this was all stuffed into i915 since it was the only driver supporting HDCP. Over the last while I've been working on HDCP support in the msm driver and have identified the parts which can/should be shared between drivers and the parts which are hw-specific. We can generalize all of the sink interactions in the helper as well as state handling and link checks. This tends to be the trickiest part of adding HDCP support, since the property state and locking is a bit of a nightmare. The driver need only implement the more mechanical display controller register accesses. The first third of the pachset is establishing the helpers, the next third is converting the i915 driver to use the helpers, and the last third is the msm driver implementation. I've left out HDCP 2.x support, since we still only have i915 as the reference implementation and I'm not super comfortable speculating on which parts are platform independent. Please take a look, Sean Sean Paul (14): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 drm/msm/dpu_kms: Re-order dpu includes drm/msm/dpu: Remove useless checks in dpu_encoder drm/msm/dpu: Remove encoder->enable() hack drm/msm/dp: Re-order dp_audio_put in deinit_sub_modules dt-bindings: msm/dp: Add bindings for HDCP registers drm/msm: Add hdcp register ranges to sc7180 device tree drm/msm: Implement HDCP 1.x using the new drm HDCP helpers .../bindings/display/msm/dp-controller.yaml | 11 +- drivers/gpu/drm/drm_hdcp.c | 1198 ++++++++++++++++- drivers/gpu/drm/i915/display/intel_atomic.c | 7 +- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- .../drm/i915/display/intel_display_debugfs.c | 11 +- .../drm/i915/display/intel_display_types.h | 58 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 341 ++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 1011 +++----------- drivers/gpu/drm/i915/display/intel_hdcp.h | 35 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 256 ++-- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 30 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 4 - drivers/gpu/drm/msm/dp/dp_debug.c | 49 +- drivers/gpu/drm/msm/dp/dp_debug.h | 6 +- drivers/gpu/drm/msm/dp/dp_display.c | 47 +- drivers/gpu/drm/msm/dp/dp_display.h | 5 + drivers/gpu/drm/msm/dp/dp_drm.c | 68 +- drivers/gpu/drm/msm/dp/dp_drm.h | 5 + drivers/gpu/drm/msm/dp/dp_hdcp.c | 433 ++++++ drivers/gpu/drm/msm/dp/dp_hdcp.h | 27 + drivers/gpu/drm/msm/dp/dp_parser.c | 30 +- drivers/gpu/drm/msm/dp/dp_parser.h | 4 + drivers/gpu/drm/msm/dp/dp_reg.h | 44 +- drivers/gpu/drm/msm/msm_atomic.c | 15 + include/drm/drm_hdcp.h | 194 +++ 29 files changed, 2570 insertions(+), 1385 deletions(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h -- Sean Paul, Software Engineer, Google / Chromium OS

6 22

[v5 0/5] drm/panel: boe-tv101wum-nl6: Support enabling a 3.3V rail
by yangcong 14 Sep '21

14 Sep '21

Compared to v4, update init code and porch setting and revert DSI LS mode in drm/panel: boe-tv101wum-nl6 - .clock = 162383, + .clock = 166594, .hdisplay = 1200, .hsync_start = 1200 + 40, .hsync_end = 1200 + 40 + 8, .htotal = 1200 + 40 + 8 + 28, .vdisplay = 2000, .vsync_start = 2000 + 26, - .vsync_end = 2000 + 26 + 1, - .vtotal = 2000 + 26 + 1 + 94, + .vsync_end = 2000 + 26 + 2, + .vtotal = 2000 + 26 + 2 + 148, .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, }; - .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM, + .mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO + | MIPI_DSI_MODE_VIDEO_HSE + | MIPI_DSI_CLOCK_NON_CONTINUOUS + | MIPI_DSI_MODE_VIDEO_BURST, ... ... ... yangcong (5): drm/panel: boe-tv101wum-nl6: Support enabling a 3.3V rail dt-bindings: drm/panel: boe-tv101wum-nl6: Support enabling a 3.3V rail drm/panel: support for BOE and INX video mode panel dt-bindings: boe, tv101wum-n16: Add compatible for boe tv110c9m-ll3 and inx hj110iz-01a drm/panel: Update BOE and INX init code to support touch function .../display/panel/boe,tv101wum-nl6.yaml | 7 + .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 745 +++++++++++++++++- 2 files changed, 750 insertions(+), 2 deletions(-) -- 2.25.1

3 7

[PATCH 0/4] Do error capture async, flush G2H processing on reset
by Matthew Brost 14 Sep '21

14 Sep '21

Rather allocating an error capture in nowait context to break a lockdep splat [1], do the error capture async compared to the G2H processing. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> [1] https://patchwork.freedesktop.org/patch/451415/?series=93704&rev=5 John Harrison (1): drm/i915/guc: Refcount context during error capture Matthew Brost (3): drm/i915/guc: Move guc_ids under submission_state sub-structure drm/i915/guc: Do error capture asynchronously drm/i915/guc: Flush G2H work queue during reset drivers/gpu/drm/i915/gt/intel_context.c | 2 + drivers/gpu/drm/i915/gt/intel_context_types.h | 16 ++- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 36 +++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 133 ++++++++++++------ 4 files changed, 128 insertions(+), 59 deletions(-) -- 2.32.0

1 4

[PATCH v2 0/1] lib, stackdepot: Add helper to print stack entries into buffer.
by Imran Khan 14 Sep '21

14 Sep '21

Changes in v2: - Addressed review comment. - Added Acked from Vlastimil. - Fixed one mistake, due to which stack_trace_snprint was always getting invoked with 0 as space value. Changed it to make use of space argument, because users that are printing stack entries into buffer, may intend to specify indentation as well. I also observed build error reported at [4]. This is happening due to failure in cherry-picking this patch and this happens because the earlier patches (mentioned in original cover lette), are not there in the tree. Please let me know, if it would be better if I send earlier patches with this change as well. I can resend those patches keeping the Acked-by and Reviewed-by tags, obtained in those patches. [4] https://urldefense.com/v3/__https://patchwork.freedesktop.org/series/94553/… Original cover letter ---------------------- This change is in response to discussion at [1]. The patch has been created on top of my earlier changes [2] and [3]. If needed I can resend all of these patches together, though my earlier patches have been Acked. [1] https://lore.kernel.org/lkml/e6f6fb85-1d83-425b-9e36-b5784cc9e69a@suse.cz/ [2] https://lore.kernel.org/lkml/fe94ffd8-d235-87d8-9c3d-80f7f73e0c4e@suse.cz/ [3] https://lore.kernel.org/lkml/85f4f073-0b5a-9052-0ba9-74d450608656@suse.cz/ Imran Khan (1): lib, stackdepot: Add helper to print stack entries into buffer. drivers/gpu/drm/drm_dp_mst_topology.c | 5 +---- drivers/gpu/drm/drm_mm.c | 5 +---- drivers/gpu/drm/i915/i915_vma.c | 5 +---- drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++++--------------- include/linux/stackdepot.h | 3 +++ lib/stackdepot.c | 24 ++++++++++++++++++++++++ mm/page_owner.c | 5 +---- 7 files changed, 36 insertions(+), 31 deletions(-) -- 2.30.2

1 1

[PATCH] drm/rockchip: cdn-dp-core: Fix cdn_dp_resume unused warning
by Palmer Dabbelt 14 Sep '21

14 Sep '21

From: Palmer Dabbelt <palmerdabbelt(a)google.com> cdn_dp_resume is only used under PM_SLEEP, and now that it's static an unused function warning is triggered undner !PM_SLEEP. This conditionally enables the function to avoid the warning. Fixes: 7c49abb4c2f8 ("drm/rockchip: cdn-dp-core: Make cdn_dp_core_suspend/resume static") Signed-off-by: Palmer Dabbelt <palmerdabbelt(a)google.com> --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index a4a45daf93f2..063a60d213ba 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -1121,6 +1121,7 @@ static int cdn_dp_suspend(struct device *dev) return ret; } +#ifdef CONFIG_PM_SLEEP static int cdn_dp_resume(struct device *dev) { struct cdn_dp_device *dp = dev_get_drvdata(dev); @@ -1133,6 +1134,7 @@ static int cdn_dp_resume(struct device *dev) return 0; } +#endif static int cdn_dp_probe(struct platform_device *pdev) { -- 2.20.1

2 1

[PATCH v1 0/2] Add support for eDP on SC7280
by Sankeerth Billakanti 14 Sep '21

14 Sep '21

This series will add eDP controller support for Qualcomm SC7280 platform. These patches are baseline changes with which we can enable eDP display on sc7280. The sc7280 eDP controller can also support additional features such as backlight control, PSR etc. which will be enabled in subsequent patch series. This is based on Bjorn's changes in the below mentioned series to support both eDP and DP programming through the same driver: v1 of https://patchwork.freedesktop.org/series/92860/ v1 of https://patchwork.freedesktop.org/series/92992/ Summary of changes: Add support for eDP on SC7280 platform. Add the new compatible string to documentation. Sankeerth Billakanti (2): drm/msm/dp: Add support for SC7280 eDP dt-bindings: Add SC7280 compatible string .../bindings/display/msm/dp-controller.yaml | 3 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +++++++++++++ drivers/gpu/drm/msm/dp/dp_display.c | 32 ++++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.c | 31 +++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_parser.h | 5 ++++ 6 files changed, 90 insertions(+), 4 deletions(-) -- The Qualcomm Innovatin Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

6 11

Re: [PATCH] kernel/locking: Add context to ww_mutex_trylock.
by kernel test robot 14 Sep '21

14 Sep '21

Hi Maarten, I love your patch! Perhaps something to improve: [auto build test WARNING on regulator/for-next] [also build test WARNING on tegra-drm/drm/tegra/for-next v5.14] [cannot apply to tip/locking/core linus/master next-20210909] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/kernel-locking-A… base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-next :::::: branch date: 2 days ago :::::: commit date: 2 days ago config: x86_64-randconfig-c007-20210908 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 9c476172b93367d2cb88d7d3f4b1b5b456fa6020) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/1e66afa09b0aa7d6db3122f0312e10d36f6… git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Maarten-Lankhorst/kernel-locking-Add-context-to-ww_mutex_trylock/20210907-212220 git checkout 1e66afa09b0aa7d6db3122f0312e10d36f6fa217 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 clang-analyzer If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com> clang-analyzer warnings: (new ones prefixed by >>) >> kernel/locking/test-ww_mutex.c:172:2: warning: Undefined or garbage value returned to caller [clang-analyzer-core.uninitialized.UndefReturn] return ret; ^ kernel/locking/test-ww_mutex.c:639:8: note: Calling 'test_aa' ret = test_aa(true); ^~~~~~~~~~~~~ kernel/locking/test-ww_mutex.c:125:2: note: 'ret' declared without an initial value int ret; ^~~~~~~ kernel/locking/test-ww_mutex.c:126:21: note: 'trylock' is true const char *from = trylock ? "trylock" : "lock"; ^~~~~~~ kernel/locking/test-ww_mutex.c:126:21: note: '?' condition is true kernel/locking/test-ww_mutex.c:131:7: note: 'trylock' is true if (!trylock) { ^~~~~~~ kernel/locking/test-ww_mutex.c:131:2: note: Taking false branch if (!trylock) { ^ kernel/locking/test-ww_mutex.c:138:7: note: Assuming the condition is true if (!ww_mutex_trylock(&mutex, &ctx)) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/locking/test-ww_mutex.c:138:3: note: Taking true branch if (!ww_mutex_trylock(&mutex, &ctx)) { ^ kernel/locking/test-ww_mutex.c:140:4: note: Control jumps to line 171 goto out; ^ kernel/locking/test-ww_mutex.c:172:2: note: Undefined or garbage value returned to caller return ret; ^ ~~~ vim +172 kernel/locking/test-ww_mutex.c f2a5fec17395f2 Chris Wilson 2016-12-01 120 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 121 static int test_aa(bool trylock) c22fb3807fd0a3 Chris Wilson 2016-12-01 122 { c22fb3807fd0a3 Chris Wilson 2016-12-01 123 struct ww_mutex mutex; c22fb3807fd0a3 Chris Wilson 2016-12-01 124 struct ww_acquire_ctx ctx; c22fb3807fd0a3 Chris Wilson 2016-12-01 125 int ret; 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 126 const char *from = trylock ? "trylock" : "lock"; c22fb3807fd0a3 Chris Wilson 2016-12-01 127 c22fb3807fd0a3 Chris Wilson 2016-12-01 128 ww_mutex_init(&mutex, &ww_class); c22fb3807fd0a3 Chris Wilson 2016-12-01 129 ww_acquire_init(&ctx, &ww_class); c22fb3807fd0a3 Chris Wilson 2016-12-01 130 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 131 if (!trylock) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 132 ret = ww_mutex_lock(&mutex, &ctx); 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 133 if (ret) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 134 pr_err("%s: initial lock failed!\n", __func__); 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 135 goto out; 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 136 } 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 137 } else { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 138 if (!ww_mutex_trylock(&mutex, &ctx)) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 139 pr_err("%s: initial trylock failed!\n", __func__); 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 140 goto out; 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 141 } 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 142 } 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 143 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 144 if (ww_mutex_trylock(&mutex, NULL)) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 145 pr_err("%s: trylocked itself without context from %s!\n", __func__, from); 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 146 ww_mutex_unlock(&mutex); 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 147 ret = -EINVAL; 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 148 goto out; 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 149 } c22fb3807fd0a3 Chris Wilson 2016-12-01 150 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 151 if (ww_mutex_trylock(&mutex, &ctx)) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 152 pr_err("%s: trylocked itself with context from %s!\n", __func__, from); c22fb3807fd0a3 Chris Wilson 2016-12-01 153 ww_mutex_unlock(&mutex); c22fb3807fd0a3 Chris Wilson 2016-12-01 154 ret = -EINVAL; c22fb3807fd0a3 Chris Wilson 2016-12-01 155 goto out; c22fb3807fd0a3 Chris Wilson 2016-12-01 156 } c22fb3807fd0a3 Chris Wilson 2016-12-01 157 c22fb3807fd0a3 Chris Wilson 2016-12-01 158 ret = ww_mutex_lock(&mutex, &ctx); c22fb3807fd0a3 Chris Wilson 2016-12-01 159 if (ret != -EALREADY) { 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 160 pr_err("%s: missed deadlock for recursing, ret=%d from %s\n", 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 161 __func__, ret, from); c22fb3807fd0a3 Chris Wilson 2016-12-01 162 if (!ret) c22fb3807fd0a3 Chris Wilson 2016-12-01 163 ww_mutex_unlock(&mutex); c22fb3807fd0a3 Chris Wilson 2016-12-01 164 ret = -EINVAL; c22fb3807fd0a3 Chris Wilson 2016-12-01 165 goto out; c22fb3807fd0a3 Chris Wilson 2016-12-01 166 } c22fb3807fd0a3 Chris Wilson 2016-12-01 167 1e66afa09b0aa7 Maarten Lankhorst 2021-09-07 168 ww_mutex_unlock(&mutex); c22fb3807fd0a3 Chris Wilson 2016-12-01 169 ret = 0; c22fb3807fd0a3 Chris Wilson 2016-12-01 170 out: c22fb3807fd0a3 Chris Wilson 2016-12-01 171 ww_acquire_fini(&ctx); c22fb3807fd0a3 Chris Wilson 2016-12-01 @172 return ret; c22fb3807fd0a3 Chris Wilson 2016-12-01 173 } c22fb3807fd0a3 Chris Wilson 2016-12-01 174 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

1 0

[PATCH 1/8] drm/i915/gem: Break out some shmem backend utils
by Matthew Auld 14 Sep '21

14 Sep '21

From: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Break out some shmem backend utils for future reuse by the TTM backend: shmem_alloc_st(), shmem_free_st() and __shmem_writeback() which we can use to provide a shmem-backed TTM page pool for cached-only TTM buffer objects. Main functional change here is that we now compute the page sizes using the dma segments rather than using the physical page address segments. Signed-off-by: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> Reviewed-by: Matthew Auld <matthew.auld(a)intel.com> Signed-off-by: Matthew Auld <matthew.auld(a)intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 182 +++++++++++++--------- 1 file changed, 107 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 11f072193f3b..ab02309f0752 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -25,46 +25,61 @@ static void check_release_pagevec(struct pagevec *pvec) cond_resched(); } -static int shmem_get_pages(struct drm_i915_gem_object *obj) +static void shmem_free_st(struct sg_table *st, struct address_space *mapping, + bool dirty, bool backup) { - struct drm_i915_private *i915 = to_i915(obj->base.dev); - struct intel_memory_region *mem = obj->mm.region; - const unsigned long page_count = obj->base.size / PAGE_SIZE; + struct sgt_iter sgt_iter; + struct pagevec pvec; + struct page *page; + + mapping_clear_unevictable(mapping); + + pagevec_init(&pvec); + for_each_sgt_page(page, sgt_iter, st) { + if (dirty) + set_page_dirty(page); + + if (backup) + mark_page_accessed(page); + + if (!pagevec_add(&pvec, page)) + check_release_pagevec(&pvec); + } + if (pagevec_count(&pvec)) + check_release_pagevec(&pvec); + + sg_free_table(st); + kfree(st); +} + +static struct sg_table *shmem_alloc_st(struct drm_i915_private *i915, + size_t size, struct intel_memory_region *mr, + struct address_space *mapping, + unsigned int max_segment) +{ + const unsigned long page_count = size / PAGE_SIZE; unsigned long i; - struct address_space *mapping; struct sg_table *st; struct scatterlist *sg; - struct sgt_iter sgt_iter; struct page *page; unsigned long last_pfn = 0; /* suppress gcc warning */ - unsigned int max_segment = i915_sg_segment_size(); - unsigned int sg_page_sizes; gfp_t noreclaim; int ret; - /* - * Assert that the object is not currently in any GPU domain. As it - * wasn't in the GTT, there shouldn't be any way it could have been in - * a GPU cache - */ - GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); - GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); - /* * If there's no chance of allocating enough pages for the whole * object, bail early. */ - if (obj->base.size > resource_size(&mem->region)) - return -ENOMEM; + if (size > resource_size(&mr->region)) + return ERR_PTR(-ENOMEM); st = kmalloc(sizeof(*st), GFP_KERNEL); if (!st) - return -ENOMEM; + return ERR_PTR(-ENOMEM); -rebuild_st: if (sg_alloc_table(st, page_count, GFP_KERNEL)) { kfree(st); - return -ENOMEM; + return ERR_PTR(-ENOMEM); } /* @@ -73,14 +88,12 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) * * Fail silently without starting the shrinker */ - mapping = obj->base.filp->f_mapping; mapping_set_unevictable(mapping); noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM); noreclaim |= __GFP_NORETRY | __GFP_NOWARN; sg = st->sgl; st->nents = 0; - sg_page_sizes = 0; for (i = 0; i < page_count; i++) { const unsigned int shrink[] = { I915_SHRINK_BOUND | I915_SHRINK_UNBOUND, @@ -135,10 +148,9 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) if (!i || sg->length >= max_segment || page_to_pfn(page) != last_pfn + 1) { - if (i) { - sg_page_sizes |= sg->length; + if (i) sg = sg_next(sg); - } + st->nents++; sg_set_page(sg, page, PAGE_SIZE, 0); } else { @@ -149,14 +161,66 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) /* Check that the i965g/gm workaround works. */ GEM_BUG_ON(gfp & __GFP_DMA32 && last_pfn >= 0x00100000UL); } - if (sg) { /* loop terminated early; short sg table */ - sg_page_sizes |= sg->length; + if (sg) /* loop terminated early; short sg table */ sg_mark_end(sg); - } /* Trim unused sg entries to avoid wasting memory. */ i915_sg_trim(st); + return st; +err_sg: + sg_mark_end(sg); + if (sg != st->sgl) { + shmem_free_st(st, mapping, false, false); + } else { + mapping_clear_unevictable(mapping); + sg_free_table(st); + kfree(st); + } + + /* + * shmemfs first checks if there is enough memory to allocate the page + * and reports ENOSPC should there be insufficient, along with the usual + * ENOMEM for a genuine allocation failure. + * + * We use ENOSPC in our driver to mean that we have run out of aperture + * space and so want to translate the error from shmemfs back to our + * usual understanding of ENOMEM. + */ + if (ret == -ENOSPC) + ret = -ENOMEM; + + return ERR_PTR(ret); +} + +static int shmem_get_pages(struct drm_i915_gem_object *obj) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct intel_memory_region *mem = obj->mm.region; + const unsigned long page_count = obj->base.size / PAGE_SIZE; + struct address_space *mapping; + struct sg_table *st; + struct sgt_iter sgt_iter; + struct page *page; + unsigned int max_segment = i915_sg_segment_size(); + int ret; + + /* + * Assert that the object is not currently in any GPU domain. As it + * wasn't in the GTT, there shouldn't be any way it could have been in + * a GPU cache + */ + GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); + GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); + +rebuild_st: + st = shmem_alloc_st(i915, obj->base.size, mem, + obj->base.filp->f_mapping, max_segment); + if (IS_ERR(st)) { + ret = PTR_ERR(st); + goto err_st; + } + ret = i915_gem_gtt_prepare_pages(obj, st); if (ret) { /* @@ -168,6 +232,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) for_each_sgt_page(page, sgt_iter, st) put_page(page); sg_free_table(st); + kfree(st); max_segment = PAGE_SIZE; goto rebuild_st; @@ -200,28 +265,12 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) if (IS_JSL_EHL(i915) && obj->flags & I915_BO_ALLOC_USER) obj->cache_dirty = true; - __i915_gem_object_set_pages(obj, st, sg_page_sizes); + __i915_gem_object_set_pages(obj, st, i915_sg_dma_sizes(st->sgl)); return 0; -err_sg: - sg_mark_end(sg); err_pages: - mapping_clear_unevictable(mapping); - if (sg != st->sgl) { - struct pagevec pvec; - - pagevec_init(&pvec); - for_each_sgt_page(page, sgt_iter, st) { - if (!pagevec_add(&pvec, page)) - check_release_pagevec(&pvec); - } - if (pagevec_count(&pvec)) - check_release_pagevec(&pvec); - } - sg_free_table(st); - kfree(st); - + shmem_free_st(st, mapping, false, false); /* * shmemfs first checks if there is enough memory to allocate the page * and reports ENOSPC should there be insufficient, along with the usual @@ -231,6 +280,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) * space and so want to translate the error from shmemfs back to our * usual understanding of ENOMEM. */ +err_st: if (ret == -ENOSPC) ret = -ENOMEM; @@ -251,10 +301,8 @@ shmem_truncate(struct drm_i915_gem_object *obj) obj->mm.pages = ERR_PTR(-EFAULT); } -static void -shmem_writeback(struct drm_i915_gem_object *obj) +static void __shmem_writeback(size_t size, struct address_space *mapping) { - struct address_space *mapping; struct writeback_control wbc = { .sync_mode = WB_SYNC_NONE, .nr_to_write = SWAP_CLUSTER_MAX, @@ -270,10 +318,9 @@ shmem_writeback(struct drm_i915_gem_object *obj) * instead of invoking writeback so they are aged and paged out * as normal. */ - mapping = obj->base.filp->f_mapping; /* Begin writeback on each dirty page */ - for (i = 0; i < obj->base.size >> PAGE_SHIFT; i++) { + for (i = 0; i < size >> PAGE_SHIFT; i++) { struct page *page; page = find_lock_page(mapping, i); @@ -296,6 +343,12 @@ shmem_writeback(struct drm_i915_gem_object *obj) } } +static void +shmem_writeback(struct drm_i915_gem_object *obj) +{ + __shmem_writeback(obj->base.size, obj->base.filp->f_mapping); +} + void __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, struct sg_table *pages, @@ -316,11 +369,6 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_table *pages) { - struct sgt_iter sgt_iter; - struct pagevec pvec; - struct page *page; - - GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev))); __i915_gem_object_release_shmem(obj, pages, true); i915_gem_gtt_finish_pages(obj, pages); @@ -328,25 +376,9 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_ if (i915_gem_object_needs_bit17_swizzle(obj)) i915_gem_object_save_bit_17_swizzle(obj, pages); - mapping_clear_unevictable(file_inode(obj->base.filp)->i_mapping); - - pagevec_init(&pvec); - for_each_sgt_page(page, sgt_iter, pages) { - if (obj->mm.dirty) - set_page_dirty(page); - - if (obj->mm.madv == I915_MADV_WILLNEED) - mark_page_accessed(page); - - if (!pagevec_add(&pvec, page)) - check_release_pagevec(&pvec); - } - if (pagevec_count(&pvec)) - check_release_pagevec(&pvec); + shmem_free_st(pages, file_inode(obj->base.filp)->i_mapping, + obj->mm.dirty, obj->mm.madv == I915_MADV_WILLNEED); obj->mm.dirty = false; - - sg_free_table(pages); - kfree(pages); } static void -- 2.26.3

2 8

[RFC][PATCH] drm/amdgpu/powerplay/smu10: Add custom profile
by Daniel Gomez 14 Sep '21

14 Sep '21

Add custom power profile mode support on smu10. Update workload bit list. --- Hi, I'm trying to add custom profile for the Raven Ridge but not sure if I'd need a different parameter than PPSMC_MSG_SetCustomPolicy to configure the custom values. The code seemed to support CUSTOM for workload types but it didn't show up in the menu or accept any user input parameter. So far, I've added that part but a bit confusing to me what is the policy I need for setting these parameters or if it's maybe not possible at all. After applying the changes I'd configure the CUSTOM mode as follows: echo manual > /sys/class/drm/card0/device/hwmon/hwmon1/device/power_dpm_force_performance_level echo "6 70 90 0 0" > /sys/class/drm/card0/device/hwmon/hwmon1/device/pp_power_profile_mode Then, using Darren Powell script for testing modes I get the following output: 05:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Raven Ridge [Radeon Vega Series / Radeon Vega Mobile Series] [1002:15dd] (rev 83) === pp_dpm_sclk === 0: 200Mhz 1: 400Mhz * 2: 1100Mhz === pp_dpm_mclk === 0: 400Mhz 1: 933Mhz * 2: 1067Mhz 3: 1200Mhz === pp_power_profile_mode === NUM MODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL 0 BOOTUP_DEFAULT : 70 60 0 0 1 3D_FULL_SCREEN : 70 60 1 3 2 POWER_SAVING : 90 60 0 0 3 VIDEO : 70 60 0 0 4 VR : 70 90 0 0 5 COMPUTE : 30 60 0 6 6 CUSTOM*: 70 90 0 0 As you can also see in my changes, I've also updated the workload bit table but I'm not completely sure about that change. With the tests I've done, using bit 5 for the WORKLOAD_PPLIB_CUSTOM_BIT makes the gpu sclk locked around ~36%. So, maybe I'm missing a clock limit configuraton table somewhere. Would you give me some hints to proceed with this? Thanks in advance, Daniel drivers/gpu/drm/amd/pm/inc/smu10.h | 14 +++-- .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 57 +++++++++++++++++-- .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 1 + 3 files changed, 61 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h b/drivers/gpu/drm/amd/pm/inc/smu10.h index 9e837a5014c5..b96520528240 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu10.h +++ b/drivers/gpu/drm/amd/pm/inc/smu10.h @@ -136,12 +136,14 @@ #define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT) /* Workload bits */ -#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 -#define WORKLOAD_PPLIB_VIDEO_BIT 2 -#define WORKLOAD_PPLIB_VR_BIT 3 -#define WORKLOAD_PPLIB_COMPUTE_BIT 4 -#define WORKLOAD_PPLIB_CUSTOM_BIT 5 -#define WORKLOAD_PPLIB_COUNT 6 +#define WORKLOAD_DEFAULT_BIT 0 +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 +#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 +#define WORKLOAD_PPLIB_VIDEO_BIT 3 +#define WORKLOAD_PPLIB_VR_BIT 4 +#define WORKLOAD_PPLIB_COMPUTE_BIT 5 +#define WORKLOAD_PPLIB_CUSTOM_BIT 6 +#define WORKLOAD_PPLIB_COUNT 7 typedef struct { /* MP1_EXT_SCRATCH0 */ diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 1de3ae77e03e..fef9f9ac1c56 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -110,6 +110,11 @@ static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) smu10_data->num_active_display = 0; smu10_data->deep_sleep_dcefclk = 0; + smu10_data->custom_profile_mode[0] = 0; + smu10_data->custom_profile_mode[1] = 0; + smu10_data->custom_profile_mode[2] = 0; + smu10_data->custom_profile_mode[3] = 0; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); @@ -544,6 +549,10 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) hwmgr->backend = data; + hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; + hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; + hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; + result = smu10_initialize_dpm_defaults(hwmgr); if (result != 0) { pr_err("smu10_initialize_dpm_defaults failed\n"); @@ -1408,9 +1417,15 @@ static int conv_power_profile_to_pplib_workload(int power_profile) int pplib_workload = 0; switch (power_profile) { + case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: + pplib_workload = WORKLOAD_DEFAULT_BIT; + break; case PP_SMC_POWER_PROFILE_FULLSCREEN3D: pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; break; + case PP_SMC_POWER_PROFILE_POWERSAVING: + pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; + break; case PP_SMC_POWER_PROFILE_VIDEO: pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; break; @@ -1430,22 +1445,24 @@ static int conv_power_profile_to_pplib_workload(int power_profile) static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) { + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); uint32_t i, size = 0; static const uint8_t - profile_mode_setting[6][4] = {{70, 60, 0, 0,}, + profile_mode_setting[7][4] = {{70, 60, 0, 0,}, {70, 60, 1, 3,}, {90, 60, 0, 0,}, {70, 60, 0, 0,}, {70, 90, 0, 0,}, {30, 60, 0, 6,}, }; - static const char *profile_name[6] = { + static const char *profile_name[7] = { "BOOTUP_DEFAULT", "3D_FULL_SCREEN", "POWER_SAVING", "VIDEO", "VR", - "COMPUTE"}; + "COMPUTE", + "CUSTOM"}; static const char *title[6] = {"NUM", "MODE_NAME", "BUSY_SET_POINT", @@ -1459,11 +1476,15 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], title[1], title[2], title[3], title[4], title[5]); - for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++) + for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", profile_mode_setting[i][0], profile_mode_setting[i][1], profile_mode_setting[i][2], profile_mode_setting[i][3]); + size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, + profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", + smu10_data->custom_profile_mode[0], smu10_data->custom_profile_mode[1], + smu10_data->custom_profile_mode[2], smu10_data->custom_profile_mode[3]); return size; } @@ -1480,16 +1501,42 @@ static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) { + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); + uint8_t busy_set_point, FPS, use_rlc_busy, min_active_level; + uint32_t power_profile_mode = input[size]; int workload_type = 0; int result = 0; - if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) { + if (input[size] > PP_SMC_POWER_PROFILE_CUSTOM) { pr_err("Invalid power profile mode %ld\n", input[size]); return -EINVAL; } if (hwmgr->power_profile_mode == input[size]) return 0; + if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 0 && size != 4) + return -EINVAL; + + if (size == 0) { + if (smu10_data->custom_profile_mode[0] != 0) + goto out; + else + return -EINVAL; + } + + smu10_data->custom_profile_mode[0] = busy_set_point = input[0]; + smu10_data->custom_profile_mode[1] = FPS = input[1]; + smu10_data->custom_profile_mode[2] = use_rlc_busy = input[2]; + smu10_data->custom_profile_mode[3] = min_active_level = input[3]; + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetCustomPolicy, + busy_set_point | FPS<<8 | + use_rlc_busy << 16 | min_active_level<<24, + NULL); + } + +out: /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ workload_type = conv_power_profile_to_pplib_workload(input[size]); diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h index 808e0ecbe1f0..4c4b2b1b510a 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h @@ -302,6 +302,7 @@ struct smu10_hwmgr { uint32_t num_active_display; bool fine_grain_enabled; + uint8_t custom_profile_mode[4]; }; struct pp_hwmgr; -- 2.30.2

3 4

[PATCH 1/2] drm/bridge: parade-ps8640: Use regmap APIs
by Philip Chen 13 Sep '21

13 Sep '21

Replace the direct i2c access (i2c_smbus_* functions) with regmap APIs, which will simplify the future update on ps8640 driver. Signed-off-by: Philip Chen <philipchen(a)chromium.org> --- drivers/gpu/drm/bridge/parade-ps8640.c | 66 +++++++++++++++----------- 1 file changed, 39 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 685e9c38b2db..a16725dbf912 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -9,6 +9,7 @@ #include <linux/i2c.h> #include <linux/module.h> #include <linux/of_graph.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <drm/drm_bridge.h> @@ -64,12 +65,29 @@ struct ps8640 { struct drm_bridge *panel_bridge; struct mipi_dsi_device *dsi; struct i2c_client *page[MAX_DEVS]; + struct regmap *regmap[MAX_DEVS]; struct regulator_bulk_data supplies[2]; struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; bool powered; }; +static const struct regmap_range ps8640_volatile_ranges[] = { + { .range_min = 0, .range_max = 0xff }, +}; + +static const struct regmap_access_table ps8640_volatile_table = { + .yes_ranges = ps8640_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(ps8640_volatile_ranges), +}; + +static const struct regmap_config ps8640_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &ps8640_volatile_table, + .cache_type = REGCACHE_NONE, +}; + static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) { return container_of(e, struct ps8640, bridge); @@ -78,13 +96,13 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, const enum ps8640_vdo_control ctrl) { - struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; - u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; + struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; + u8 vdo_ctrl_buf[] = {VDO_CTL_ADD, ctrl}; int ret; - ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD, - sizeof(vdo_ctrl_buf), - vdo_ctrl_buf); + ret = regmap_bulk_write(map, PAGE3_SET_ADD, + vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); + if (ret < 0) { DRM_ERROR("failed to %sable VDO: %d\n", ctrl == ENABLE ? "en" : "dis", ret); @@ -96,8 +114,7 @@ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) { - struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; - unsigned long timeout; + struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; int ret, status; if (ps_bridge->powered) @@ -121,18 +138,12 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) */ msleep(200); - timeout = jiffies + msecs_to_jiffies(200) + 1; + ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, + status & PS_GPIO9, 20 * 1000, 200 * 1000); - while (time_is_after_jiffies(timeout)) { - status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H); - if (status < 0) { - DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status); - goto err_regulators_disable; - } - if ((status & PS_GPIO9) == PS_GPIO9) - break; - - msleep(20); + if (ret < 0) { + DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); + goto err_regulators_disable; } msleep(50); @@ -144,22 +155,15 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) * disabled by the manufacturer. Once disabled, all MCS commands are * ignored by the display interface. */ - status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN); - if (status < 0) { - DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status); - goto err_regulators_disable; - } - ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN, - status & ~MCS_EN); + ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); if (ret < 0) { DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); goto err_regulators_disable; } /* Switch access edp panel's edid through i2c */ - ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS, - I2C_BYPASS_EN); + ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); if (ret < 0) { DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); goto err_regulators_disable; @@ -361,6 +365,10 @@ static int ps8640_probe(struct i2c_client *client) ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; ps_bridge->page[PAGE0_DP_CNTL] = client; + ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, + &ps8640_regmap_config); + if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) + return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, @@ -371,6 +379,10 @@ static int ps8640_probe(struct i2c_client *client) client->addr + i); return PTR_ERR(ps_bridge->page[i]); } + ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], + &ps8640_regmap_config); + if (IS_ERR(ps_bridge->regmap)) + return PTR_ERR(ps_bridge->regmap[i]); } i2c_set_clientdata(client, ps_bridge); -- 2.33.0.153.gba50c8fa24-goog

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dri-devel September 2021