dri-devel January 2022

dri-devel@lists.freedesktop.org

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[PATCH] dt-bindings: display: enable port jdi,lt070me05000
by David Heidelberg 04 Jan '22

04 Jan '22

Enable port inside panel bindings. Fixes warnings generated by `make qcom-apq8064-asus-nexus7-flo.dtb` as: arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml: panel@0: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml Signed-off-by: David Heidelberg <david(a)ixit.cz> --- .../devicetree/bindings/display/panel/jdi,lt070me05000.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml index 4f92365e888a..63c82a4378ff 100644 --- a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml +++ b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml @@ -35,6 +35,8 @@ properties: phandle of the gpio for power ic line Power IC supply enable, High active + port: true + required: - compatible - reg -- 2.34.1

2 1

[PATCH] dt-bindings: display/msm: hdmi: split and convert to yaml
by David Heidelberg 04 Jan '22

04 Jan '22

Convert Qualcomm HDMI binding into HDMI TX and PHY yaml bindings. Other changes: - fixed reg-names numbering to match 0..3 instead 0,1,3,4 Signed-off-by: David Heidelberg <david(a)ixit.cz> --- .../devicetree/bindings/display/msm/hdmi.txt | 99 --------- .../bindings/display/msm/qcom,hdmi-phy.yaml | 119 +++++++++++ .../bindings/display/msm/qcom,hdmi.yaml | 201 ++++++++++++++++++ 3 files changed, 320 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,hdmi-phy.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt deleted file mode 100644 index 5f90a40da51b..000000000000 --- a/Documentation/devicetree/bindings/display/msm/hdmi.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm adreno/snapdragon hdmi output - -Required properties: -- compatible: one of the following - * "qcom,hdmi-tx-8996" - * "qcom,hdmi-tx-8994" - * "qcom,hdmi-tx-8084" - * "qcom,hdmi-tx-8974" - * "qcom,hdmi-tx-8660" - * "qcom,hdmi-tx-8960" -- reg: Physical base address and length of the controller's registers -- reg-names: "core_physical" -- interrupts: The interrupt signal from the hdmi block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- core-vdda-supply: phandle to supply regulator -- hdmi-mux-supply: phandle to mux regulator -- phys: the phandle for the HDMI PHY device -- phy-names: the name of the corresponding PHY device - -Optional properties: -- hpd-gpios: hpd pin -- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin -- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin -- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin -- power-domains: reference to the power domain(s), if available. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-1: the "sleep" pinctrl state - -HDMI PHY: -Required properties: -- compatible: Could be the following - * "qcom,hdmi-phy-8660" - * "qcom,hdmi-phy-8960" - * "qcom,hdmi-phy-8974" - * "qcom,hdmi-phy-8084" - * "qcom,hdmi-phy-8996" -- #phy-cells: Number of cells in a PHY specifier; Should be 0. -- reg: Physical base address and length of the registers of the PHY sub blocks. -- reg-names: The names of register regions. The following regions are required: - * "hdmi_phy" - * "hdmi_pll" - For HDMI PHY on msm8996, these additional register regions are required: - * "hdmi_tx_l0" - * "hdmi_tx_l1" - * "hdmi_tx_l3" - * "hdmi_tx_l4" -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- core-vdda-supply: phandle to vdda regulator device node - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - reg-names = "core_physical"; - reg = <0x04a00000 0x2f0>; - interrupts = <GIC_SPI 79 0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "master_iface", - "slave_iface"; - clocks = - <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - hdmi-mux-supply = <&ext_3p3v>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hpd_active &ddc_active &cec_active>; - pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg-names = "hdmi_phy", - "hdmi_pll"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - #phy-cells = <0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = "slave_iface"; - clocks = <&mmcc HDMI_S_AHB_CLK>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,hdmi-phy.yaml b/Documentation/devicetree/bindings/display/msm/qcom,hdmi-phy.yaml new file mode 100644 index 000000000000..be08fc767435 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,hdmi-phy.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: "http://devicetree.org/schemas/display/msm/qcom,hdmi-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Adreno/Snapdragon HDMI phy + +maintainers: + - Rob Clark <robdclark(a)gmail.com> + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,hdmi-phy-8996 + then: + properties: + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: hdmi_pll + - const: hdmi_tx_l0 + - const: hdmi_tx_l1 + - const: hdmi_tx_l2 + - const: hdmi_tx_l3 + - const: hdmi_phy + + else: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: hdmi_phy + - const: hdmi_pll + - if: + properties: + compatible: + contains: + const: qcom,hdmi-phy-8960 + then: + properties: + clock-names: + const: slave_iface + + - if: + properties: + compatible: + contains: + const: qcom,hdmi-phy-8996 + then: + properties: + clock-names: + items: + - const: iface + - const: ref + +properties: + compatible: + contains: + enum: + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8994 + - qcom,hdmi-phy-8996 + + reg: true + + reg-names: true + + clocks: true + + clock-names: true + + power-domains: + maxItems: 1 + + core-vdda-supply: true + + vcca-supply: true + + vddio-supply: true + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - reg + - reg-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + hdmi_phy: phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + #phy-cells = <0>; + power-domains = <&mmcc 1>; + clock-names = "slave_iface"; + clocks = <&clk 21>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,hdmi.yaml b/Documentation/devicetree/bindings/display/msm/qcom,hdmi.yaml new file mode 100644 index 000000000000..72f7a58c078a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,hdmi.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: "http://devicetree.org/schemas/display/msm/qcom,hdmi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Adreno/Snapdragon HDMI output + +maintainers: + - Rob Clark <robdclark(a)gmail.com> + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,hdmi-tx-8996 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: mdp_core + - const: iface + - const: core + - const: alt_iface + - const: extp + else: + properties: + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + +properties: + compatible: + enum: + - qcom,hdmi-tx-8996 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + + clocks: true + + clock-names: true + + reg: + minItems: 1 + maxItems: 3 + description: Physical base address and length of the controller's registers + + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical + + interrupts: + description: The interrupt signal from the hdmi block. + + power-domains: + description: should be <&mmcc MDSS_GDSC> + + core-vdda-supply: true + + core-vcc-supply: true + + hdmi-mux-supply: + description: phandle to mux regulator + + phys: + description: the phandle for the HDMI PHY device + + phy-names: + description: the name of the corresponding PHY device + + hpd-gpios: + description: hpd pin + + qcom,hdmi-tx-ddc-clk-gpios: + description: HDMI DDC clock + + qcom,hdmi-tx-ddc-data-gpios: + description: HDMI DDC data + + qcom,hdmi-tx-mux-en-gpios: + description: HDMI mux enable pin + + qcom,hdmi-tx-mux-sel-gpios: + description: HDMI mux select pin + + qcom,hdmi-tx-mux-lpm-gpios: + description: HDMI mux lpm pin + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + anyOf: + - items: + - const: default + - items: + - const: default + - const: sleep + + '#phy-cells': + const: 0 + + '#sound-dai-cells': + const: 1 + + ports: + type: object + $ref: "/schemas/graph.yaml#/properties/ports" + properties: + port@0: + $ref: "/schemas/graph.yaml#/$defs/port-base" + unevaluatedProperties: false + description: | + Input endpoints of the controller. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + maxItems: 4 + minItems: 4 + items: + enum: [0, 1, 2, 3] + + port@1: + $ref: "/schemas/graph.yaml#/$defs/port-base" + unevaluatedProperties: false + description: | + Output endpoints of the controller. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + maxItems: 4 + minItems: 4 + items: + enum: [0, 1, 2, 3] + + required: + - port@0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - interrupts + - phys + - phy-names + +additionalProperties: false + +examples: + - | + hdmi: hdmi@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x2f0>; + interrupts = <0 79 0>; + power-domains = <&mmcc 1>; + clock-names = + "core", + "master_iface", + "slave_iface"; + clocks = + <&clk 61>, + <&clk 72>, + <&clk 98>; + qcom,hdmi-tx-ddc-clk-gpios = <&msmgpio 70 0>; + qcom,hdmi-tx-ddc-data-gpios = <&msmgpio 71 0>; + hpd-gpios = <&msmgpio 72 0>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + }; -- 2.34.1

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[PATCH] dt-bindings: display: simple: Add Multi-Inno Technology MI0700S4T-6 panel
by Marek Vasut 04 Jan '22

04 Jan '22

Add Multi-Inno Technology MI0700S4T-6 7" 800x480 DPI panel compatible string. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Sam Ravnborg <sam(a)ravnborg.org> Cc: devicetree(a)vger.kernel.org To: dri-devel(a)lists.freedesktop.org --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 62f5f050c1bc..9cf5588a09d8 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -222,6 +222,8 @@ properties: - logictechno,lttd800480070-l6wh-rt # Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel - mitsubishi,aa070mc01-ca1 + # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module + - multi-inno,mi0700s4t-6 # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod. - multi-inno,mi1010ait-1cp # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel -- 2.34.1

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[PATCH] dt-bindings: display: st, stm32-dsi: Fix panel node name in example
by Rob Herring 04 Jan '22

04 Jan '22

With 'unevaluatedProperties' support enabled, the st,stm32-dsi binding has a new warning: Documentation/devicetree/bindings/display/st,stm32-dsi.example.dt.yaml: dsi@5a000000: Unevaluated properties are not allowed ('panel-dsi@0' was unexpected) The documented child node name is 'panel', so update the example. Signed-off-by: Rob Herring <robh(a)kernel.org> --- Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index ce1ef93cce93..54f67cb51040 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -110,7 +110,7 @@ examples: }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; @@ -125,4 +125,3 @@ examples: }; ... - -- 2.32.0

1 1

[PATCH v3 0/5] Panel replay phase1 implementation
by Animesh Manna 04 Jan '22

04 Jan '22

Panel Replay is a power saving feature for DP 2.0 monitor and similar to PSR on EDP. These patches are basic enablement patches and reused psr framework to add panel replay related new changes which may need further fine tuning to fill the gap if there is any. Note: The patches are not tested due to unavailability of monitor Animesh Manna (5): drm/i915/panelreplay: dpcd register definition for panelreplay drm/i915/panelreplay: HAS_PR() macro added for panel replay drm/i915/panelreplay: Initializaton and compute config for panel replay drm/i915/panelreplay: enable/disable panel replay drm/i915/panelreplay: Added state checker for panel replay state drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++-- drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_psr.h | 3 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + include/drm/drm_dp_helper.h | 6 ++ 8 files changed, 128 insertions(+), 13 deletions(-) -- 2.29.0

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[PATCH] drm/bridge: parade-ps8640: Link device to ensure suspend/resume order
by AngeloGioacchino Del Regno 04 Jan '22

04 Jan '22

Entering suspend while the display attached to this bridge is still on makes the resume sequence to resume the bridge first, display last: when this happens, we get a timeout while resuming the bridge, as its MCU will get stuck due to the display being unpowered. On the other hand, on mt8173-elm, closing the lid makes the display to get powered off first, bridge last, so at resume time the sequence is swapped (compared to the first example) and everything just works as expected. Add a stateless device link to the DRM device that this bridge belongs to, ensuring a correct resume sequence and solving the unability to correctly resume bridge operation in the first mentioned example. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)collabora.com> --- drivers/gpu/drm/bridge/parade-ps8640.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 45100edd745b..191cc196c9d1 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -100,6 +100,7 @@ struct ps8640 { struct regulator_bulk_data supplies[2]; struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; + struct device_link *link; bool powered; }; @@ -460,10 +461,23 @@ static int ps8640_bridge_attach(struct drm_bridge *bridge, goto err_aux_register; } + ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS); + if (!ps_bridge->link) { + dev_err(dev, "failed to create device link"); + ret = -EINVAL; + goto err_devlink; + } + /* Attach the panel-bridge to the dsi bridge */ - return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, + ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, &ps_bridge->bridge, flags); + if (ret) + goto err_bridge_attach; +err_bridge_attach: + device_link_del(ps_bridge->link); +err_devlink: + drm_dp_aux_unregister(&ps_bridge->aux); err_aux_register: mipi_dsi_detach(dsi); err_dsi_attach: @@ -473,7 +487,11 @@ static int ps8640_bridge_attach(struct drm_bridge *bridge, static void ps8640_bridge_detach(struct drm_bridge *bridge) { - drm_dp_aux_unregister(&bridge_to_ps8640(bridge)->aux); + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + + drm_dp_aux_unregister(&ps_bridge->aux); + if (ps_bridge->link) + device_link_del(ps_bridge->link); } static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, -- 2.33.1

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[PATCH] drm/bridge: anx7625: Fix null vs IS_ERR() checking in anx7625_register_i2c_dummy_clients
by Miaoqian Lin 04 Jan '22

04 Jan '22

Since i2c_new_client_device() function return error pointers. The i2c_new_dummy_device() function does not return NULL, It returns error pointers too. Using IS_ERR() to check the return value to fix this. Fixes: 8bdfc5dae4e3("drm/bridge: anx7625: Add anx7625 MIPI DSI/DPI to DP") Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> --- drivers/gpu/drm/bridge/analogix/anx7625.c | 32 ++++++++++++++++------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 1a871f6b6822..eb72aa6aedd6 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1637,40 +1637,54 @@ static const struct drm_bridge_funcs anx7625_bridge_funcs = { static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, struct i2c_client *client) { + int err = 0; + ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter, TX_P0_ADDR >> 1); - if (!ctx->i2c.tx_p0_client) - return -ENOMEM; + if (IS_ERR(ctx->i2c.tx_p0_client)) + return PTR_ERR(ctx->i2c.tx_p0_client); ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter, TX_P1_ADDR >> 1); - if (!ctx->i2c.tx_p1_client) + if (IS_ERR(ctx->i2c.tx_p1_client)) { + err = PTR_ERR(ctx->i2c.tx_p1_client); goto free_tx_p0; + } ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter, TX_P2_ADDR >> 1); - if (!ctx->i2c.tx_p2_client) + if (IS_ERR(ctx->i2c.tx_p2_client)) { + err = PTR_ERR(ctx->i2c.tx_p2_client); goto free_tx_p1; + } ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter, RX_P0_ADDR >> 1); - if (!ctx->i2c.rx_p0_client) + if (IS_ERR(ctx->i2c.rx_p0_client)) { + err = PTR_ERR(ctx->i2c.rx_p0_client); goto free_tx_p2; + } ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter, RX_P1_ADDR >> 1); - if (!ctx->i2c.rx_p1_client) + if (IS_ERR(ctx->i2c.rx_p1_client)) { + err = PTR_ERR(ctx->i2c.rx_p1_client); goto free_rx_p0; + } ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter, RX_P2_ADDR >> 1); - if (!ctx->i2c.rx_p2_client) + if (IS_ERR(ctx->i2c.rx_p2_client)) { + err = PTR_ERR(ctx->i2c.rx_p2_client); goto free_rx_p1; + } ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter, TCPC_INTERFACE_ADDR >> 1); - if (!ctx->i2c.tcpc_client) + if (IS_ERR(ctx->i2c.tcpc_client)) { + err = PTR_ERR(ctx->i2c.tcpc_client); goto free_rx_p2; + } return 0; @@ -1687,7 +1701,7 @@ static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, free_tx_p0: i2c_unregister_device(ctx->i2c.tx_p0_client); - return -ENOMEM; + return err; } static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx) -- 2.17.1

2 2

[PATCH] drm: bridge: cdns-mhdp8546: Fix a NULL pointer dereference in cdns_mhdp_atomic_enable()
by Zhou Qingyang 04 Jan '22

04 Jan '22

In cdns_mhdp_atomic_enable(), the return value of drm_mode_duplicate() is assigned to mhdp_state->current_mode and used in drm_mode_set_name(). There is a dereference of it in drm_mode_set_name(), which could lead to a NULL pointer dereference on failure of drm_mode_duplicate(). Fix this bug by adding a check of mhdp_state->current_mode. This bug was found by a static analyzer. The analysis employs differential checking to identify inconsistent security operations (e.g., checks or kfrees) between two code paths and confirms that the inconsistent operations are not recovered in the current function or the callers, so they constitute bugs. Note that, as a bug found by static analysis, it can be a false positive or hard to trigger. Multiple researchers have cross-reviewed the bug. Builds with CONFIG_DRM_CDNS_MHDP8546=m show no new warnings, and our static analyzer no longer warns about this code. Fixes: fb43aa0acdfd ("drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge") Signed-off-by: Zhou Qingyang <zhou1615(a)umn.edu> --- drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 5530fbf64f1e..347fbecf76a4 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -2040,6 +2040,11 @@ static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, mhdp_state = to_cdns_mhdp_bridge_state(new_state); mhdp_state->current_mode = drm_mode_duplicate(bridge->dev, mode); + if (!mhdp_state->current_mode) { + ret = -ENOMEM; + goto out; + } + drm_mode_set_name(mhdp_state->current_mode); dev_dbg(mhdp->dev, "%s: Enabling mode %s\n", __func__, mode->name); -- 2.25.1

2 1

[PATCH] drm/stm: ltdc: support of new hardware version
by Yannick Fertre 04 Jan '22

04 Jan '22

Add support of new hardware version 0x40100. Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/ltdc.c | 172 ++++++++++++++++++++++++++++++------- drivers/gpu/drm/stm/ltdc.h | 3 +- 2 files changed, 145 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index dbdee954692a..c0619f372630 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -46,15 +46,15 @@ #define HWVER_10200 0x010200 #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 +#define HWVER_40100 0x040100 /* * The address of some registers depends on the HW version: such registers have - * an extra offset specified with reg_ofs. + * an extra offset specified with layer_ofs. */ -#define REG_OFS_NONE 0 -#define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ -#define REG_OFS (ldev->caps.reg_ofs) -#define LAY_OFS 0x80 /* Register Offset between 2 layers */ +#define LAY_OFS_0 0x80 +#define LAY_OFS_1 0x100 +#define LAY_OFS (ldev->caps.layer_ofs) /* Global register offsets */ #define LTDC_IDR 0x0000 /* IDentification */ @@ -75,29 +75,34 @@ #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ #define LTDC_CPSR 0x0044 /* Current Position Status */ #define LTDC_CDSR 0x0048 /* Current Display Status */ +#define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ /* Layer register offsets */ -#define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ -#define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ -#define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ -#define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ -#define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ -#define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ -#define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ -#define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ -#define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ -#define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ -#define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ -#define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ -#define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ -#define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ -#define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ -#define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ -#define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ -#define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ -#define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ -#define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ -#define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ +#define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ +#define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ +#define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ +#define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ +#define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ +#define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ +#define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ +#define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ +#define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ +#define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ +#define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ +#define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ +#define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ +#define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ +#define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ +#define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ +#define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ +#define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ +#define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ +#define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ +#define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ +#define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ +#define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ +#define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ +#define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ /* Bit definitions */ #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ @@ -208,7 +213,10 @@ enum ltdc_pix_fmt { /* Indexed formats */ PF_L8, /* Indexed 8 bits [8 bits] */ PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ - PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ + PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */ + PF_ABGR8888, /* ABGR [32 bits] */ + PF_BGRA8888, /* BGRA [32 bits] */ + PF_BGR565 /* RGB [16 bits] */ }; /* The index gives the encoding of the pixel format for an HW version */ @@ -234,6 +242,102 @@ static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { PF_ARGB4444 /* 0x07 */ }; +static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_ABGR8888, /* 0x01 */ + PF_RGBA8888, /* 0x02 */ + PF_BGRA8888, /* 0x03 */ + PF_RGB565, /* 0x04 */ + PF_BGR565, /* 0x05 */ + PF_RGB888, /* 0x06 */ + PF_ARGB1555 /* 0x07 */ +}; + +/* Layer register offsets */ +static const u32 ltdc_layer_regs_a0[] = { + 0x80, /* L1 configuration 0 */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x84, /* L1 control register */ + 0x88, /* L1 window horizontal position configuration */ + 0x8c, /* L1 window vertical position configuration */ + 0x90, /* L1 color keying configuration */ + 0x94, /* L1 pixel format configuration */ + 0x98, /* L1 constant alpha configuration */ + 0x9c, /* L1 default color configuration */ + 0xa0, /* L1 blending factors configuration */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xc4, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 ltdc_layer_regs_a1[] = { + 0x80, /* L1 configuration 0 */ + 0x84, /* L1 configuration 1 */ + 0x00, /* L1 reload control */ + 0x88, /* L1 control register */ + 0x8c, /* L1 window horizontal position configuration */ + 0x90, /* L1 window vertical position configuration */ + 0x94, /* L1 color keying configuration */ + 0x98, /* L1 pixel format configuration */ + 0x9c, /* L1 constant alpha configuration */ + 0xa0, /* L1 default color configuration */ + 0xa4, /* L1 blending factors configuration */ + 0xa8, /* L1 burst length configuration */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0xb8, /* L1 auxiliary frame buffer address 0 */ + 0xbc, /* L1 auxiliary frame buffer address 1 */ + 0xc0, /* L1 auxiliary frame buffer length */ + 0xc4, /* L1 auxiliary frame buffer line number */ + 0xc8, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 ltdc_layer_regs_a2[] = { + 0x100, /* L1 configuration 0 */ + 0x104, /* L1 configuration 1 */ + 0x108, /* L1 reload control */ + 0x10c, /* L1 control register */ + 0x110, /* L1 window horizontal position configuration */ + 0x114, /* L1 window vertical position configuration */ + 0x118, /* L1 color keying configuration */ + 0x11c, /* L1 pixel format configuration */ + 0x120, /* L1 constant alpha configuration */ + 0x124, /* L1 default color configuration */ + 0x128, /* L1 blending factors configuration */ + 0x12c, /* L1 burst length configuration */ + 0x130, /* L1 planar configuration */ + 0x134, /* L1 color frame buffer address */ + 0x138, /* L1 color frame buffer length */ + 0x13c, /* L1 color frame buffer line number */ + 0x140, /* L1 auxiliary frame buffer address 0 */ + 0x144, /* L1 auxiliary frame buffer address 1 */ + 0x148, /* L1 auxiliary frame buffer length */ + 0x14c, /* L1 auxiliary frame buffer line number */ + 0x150, /* L1 CLUT write */ + 0x16c, /* L1 Conversion YCbCr RGB 0 */ + 0x170, /* L1 Conversion YCbCr RGB 1 */ + 0x174, /* L1 Flexible Pixel Format 0 */ + 0x178 /* L1 Flexible Pixel Format 1 */ +}; + static const u64 ltdc_format_modifiers[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID @@ -1158,7 +1262,8 @@ static int ltdc_get_caps(struct drm_device *ddev) switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: - ldev->caps.reg_ofs = REG_OFS_NONE; + ldev->caps.layer_ofs = LAY_OFS_0; + ldev->caps.layer_regs = ltdc_layer_regs_a0; ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; /* * Hw older versions support non-alpha color formats derived @@ -1174,12 +1279,21 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.nb_irq = 2; break; case HWVER_20101: - ldev->caps.reg_ofs = REG_OFS_4; + ldev->caps.layer_ofs = LAY_OFS_0; + ldev->caps.layer_regs = ltdc_layer_regs_a1; ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; ldev->caps.non_alpha_only_l1 = false; ldev->caps.pad_max_freq_hz = 150000000; ldev->caps.nb_irq = 4; break; + case HWVER_40100: + ldev->caps.layer_ofs = LAY_OFS_1; + ldev->caps.layer_regs = ltdc_layer_regs_a2; + ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; + ldev->caps.non_alpha_only_l1 = false; + ldev->caps.pad_max_freq_hz = 90000000; + ldev->caps.nb_irq = 2; + break; default: return -ENODEV; } diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index f153b908c70e..55a125f89af6 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -14,7 +14,8 @@ struct ltdc_caps { u32 hw_version; /* hardware version */ u32 nb_layers; /* number of supported layers */ - u32 reg_ofs; /* register offset for applicable regs */ + u32 layer_ofs; /* layer offset for applicable regs */ + const u32 *layer_regs; /* layer register offset */ u32 bus_width; /* bus width (32 or 64 bits) */ const u32 *pix_fmt_hw; /* supported pixel formats */ bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ -- 2.17.1

3 4

[PATCH] drm/stm: remove conflicting framebuffers
by Yannick Fertre 04 Jan '22

04 Jan '22

In case of using simplefb or another conflicting framebuffer, call drm_aperture_remove_framebuffers() to remove memory allocated. Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/gpu/drm/stm/drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 222869b232ae..9f441aadf2d5 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -14,6 +14,7 @@ #include <linux/of_platform.h> #include <linux/pm_runtime.h> +#include <drm/drm_aperture.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_drv.h> @@ -183,6 +184,10 @@ static int stm_drm_platform_probe(struct platform_device *pdev) DRM_DEBUG("%s\n", __func__); + ret = drm_aperture_remove_framebuffers(false, &drv_driver); + if (ret) + return ret; + dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); ddev = drm_dev_alloc(&drv_driver, dev); -- 2.17.1

3 3

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dri-devel January 2022